JPH0223626A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lower contact resistance on a hetero-interface by selectively forming a graded layer in a specified region in the depth direction after crystal growth. CONSTITUTION:Undoped GaAs 2, undoped Al0.3Ga0.7As (20nm) 3, Si-doped Al0.3 Ga0.7As (21nm) 4 and Si-doped GaAs are epitaxial-grown successively onto a semi-insulating substrate 1 through an MBE method. An SiO2 film 7 is deposited onto a crystal surface through a CVD method, and annealed in an H2 air flow. 800 deg.C and fifteen min are used as the conditions of annealing. The disordered state is brought between the Si-doped Al0.3Ga0.7As 4 and the Si-doped GaAs 5 through annealing, and a graded layer 6 is shaped. Since the thickness of the graded layer 6 on a hetero-interface coincides with the diffusion length of Si, the film thickness of the Si-doped Al0.3Ga0.7As 4 is brought to 35nm and the film thickness of the undoped Al0.3Ga0.7As 3 to 6nm by Si diffused from the Si-doped Al0.3Ga0.7As 4 to the undoped Al0.3Ga0.7As 3. Each electrode of a source, a drain and a gate is formed through a normal method, thus shaping a field-effect transistor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device using a heterojunction, and is made of a ■-■ group compound semiconductor suitable for a field effect transistor with particularly low parasitic resistance. The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

Afl, which has been well known as an m-v group compound semiconductor,
In order to reduce contact resistance due to band discontinuity in a GaAs/GaAs heterostructure FET, An Ga A in contact with the GaAs layer is grown during crystal growth by MBE.
A structure in which the composition of the s layer is graded is used. Incidentally, examples related to this type of graded structure include Proceedings of the 48th Japan Society of Applied Physics Academic Conference 17p-Z F-8, 1987.

In addition, techniques for disordering hetero-interfaces by ion implantation etc. are also available, for example, in Journal of Applied Physics, Vol. 25, No. 5, L385.
~L387 pages, 1986 (Japanese of
Applied Physics vol, 25. N
o, 5. ppL385-L387 (1986)).

[Problem to be solved by the invention]

The above conventional technology is based on MBE (Molecular B
A graded structure of GaAs is fabricated by eamE (abbreviation of molecular beam epitaxy), but in this method, the An composition is graded by changing the temperature of the An cell, so the growth rate is also changed at the same time, making it difficult to control the film thickness. It is extremely difficult.

In addition, in the method of forming a graded layer by disordering the hetero-interface by ion implantation, since implanted ions are used, it is possible to selectively form a graded layer only in the required region in the depth direction. First, there is a problem in that the implanted ions diffuse outside the target area, resulting in effects such as short channel effects. As described above, the problem to be solved by the invention is to control the thickness of the graded layer and to accurately form the graded layer only in a specific region in the depth direction within the multilayer epitaxial structure.

An object of the present invention is to solve the above-mentioned problems, and is a method for manufacturing a semiconductor device in which film thickness can be controlled and a graded layer can be selectively formed only in a predetermined region in the depth direction. Our goal is to provide the following.

[Means to solve the problem]

The above object is to provide a group IV compound semiconductor layer doped with an impurity element that determines the conductivity type on a semiconductor substrate;
- A step of sequentially epitaxially growing a ■-■ group compound semiconductor layer which forms a heterojunction with the ■-group compound semiconductor layer and is doped with the same impurity element as the impurity element, and then the step of forming a heterojunction with the ■-■ group compound semiconductor layer; A step of forming a cap layer on top of which the group (I) elements constituting the m-v group compound semiconductor can be easily diffused in a subsequent annealing step, and annealing the thus obtained multilayer film structure in a non-oxidizing atmosphere. A method for manufacturing a semiconductor device, comprising the step of: forming a graded layer which is disordered at the interface where the heterojunction is formed and has a concentration gradient of group (I) elements in the thickness direction; , Further, a first m-v group compound semiconductor layer and a second ■-■ group compound semiconductor layer forming a heterojunction with the first I[-V group compound semiconductor layer, on the semiconductor substrate, a third m-v group compound semiconductor doped with an impurity element that determines the conductivity type and made of a compound semiconductor of the same type as the second m-v group compound semiconductor;
a compound semiconductor of the same type as the first ■-■ group compound semiconductor doped with the same impurity element as the impurity element forming a heterojunction with the V group compound semiconductor layer and the third M-V group compound semiconductor layer; A step of sequentially epitaxially growing a fourth m-v group compound semiconductor layer consisting of
- a step of forming a cap layer in which the group II elements constituting the group V compound semiconductor can be easily diffused in a subsequent annealing step;
By annealing the thus obtained multilayer film structure in a non-oxidizing atmosphere, disorder is created between the third and fourth group ■-■ compound semiconductor layers, and a concentration gradient of group ■ elements is created in the thickness direction. This is achieved by a method for manufacturing a semiconductor device, which is characterized by comprising the steps of: forming a graded layer having the following steps:

The semiconductor substrate used is, for example, a compound semiconductor substrate typified by a semi-insulating GaAs substrate, but is not limited to this, and may be any substrate as long as a group I[IV compound semiconductor can be grown epitaxially. Further, as the first III-V compound semiconductor, for example, G
aAs, the second ■-■ group compound semiconductor, for example, a part of the ■-group element Ga of the first ■-■ group compound semiconductor, such as AIl, Ga□-, As, is replaced by another group-■ group element. M
Examples include mixed crystal systems substituted with GaAs, but it goes without saying that this is not limited to these GaAs systems, and other compound systems may also be used. Furthermore, the impurity element doped into the fourth and third m-v group compound semiconductor layers, which are made of the same type of compound semiconductor as the first and second m-v group compound semiconductors, determines the conductivity type. , n-type or p-type impurity elements are used, and in this specification, an example using Si, which is an n-type impurity, will be explained.

The above-mentioned cap layer may be made of, for example, Ga in the base to prevent the underlying compound semiconductor constituent elements, such as As, from evaporating during annealing during the formation of the grade 1 layer, and to promote the formation of the graded layer. Any insulator may be used as long as it has the property that group elements can be easily diffused into the cap layer, and a 5in2 film will be described here as an example.

Furthermore, the epitaxial growth of each layer of the ■-■ group compound semiconductor can be easily formed by well-known MBE or MOCVD (organometallic CVD). The cap layer, for example, an SjO□ film, can be easily formed by CVD, which is commonly used for forming insulating films in semiconductor device manufacturing processes. As the annealing conditions for forming the graded layer, a non-oxidizing atmosphere in which the laminated film structure is not oxidized, that is, a neutral or reducing gas atmosphere such as hydrogen gas, is used. Further, the thickness of the graded layer can be easily controlled by arbitrarily adjusting at least one of the annealing temperature and time.

The preferred thickness of this graded layer varies somewhat depending on the type of semiconductor device to which it is applied, but for example, in the case of an FET, it is 30 nm or less, more preferably about 15±5 nm.

In the present invention, the interface between the fourth and third m-v group compound semiconductor layers made of the same type of compound semiconductor as the first and second III-V group compound semiconductors doped with an impurity element is formed by annealing. If necessary, a thin film consisting of at least one layer of an undoped first and second ■-■ group compound semiconductor and the same type of compound semiconductor layer is used as a spacer at this interface. It is also possible to intervene. However, this spacer must also have a thickness that will be disordered during annealing, and therefore its thickness should be kept within the thickness of the graded layer that would be formed without the spacer.

Although the explanation may be complicated, the thickness of the second m-v group compound semiconductor layer (undoped layer) forming the heterojunction before annealing is the same as that of the impurity doped layer (third m-v group compound semiconductor layer) formed thereon.
It is necessary to determine the distance by taking into consideration the distance from which the impurity element diffuses from the group compound semiconductor layer. In other words, the thickness must be such that even if impurities are diffused from the upper doped layer into the underlying undoped layer due to annealing, a region where the impurities will not be diffused remains. If impurity diffusion occurs in the entire region of this undoped layer, the heterojunction formed at the interface with the underlying first m-v group compound semiconductor layer will be affected by the short channel effect, which is undesirable. In other words, problems similar to those caused by the ion implantation method described in the prior art will occur. Therefore, it is better to form this undoped second ■-■ group compound semiconductor layer a little thicker than usual during epitaxial growth.

[Effect]

Hereinafter, using FIGS. 1 and 2, the first semiconductor is GaAs and the second semiconductor is An as the ■-■ group compound semiconductor.
Taking the case of GaAs as an example, the operation will be explained along with the specific configuration.

FIG. 1(a) shows a cross section of the crystal structure produced by MBE. Undoped GaAs is deposited on the semi-insulating GaAs substrate 10.
1l (1 voice), undoped AuGaAs12 (20
nm), Si-doped A11GaAs13 (30 nm)
, Si-doped GaAs14 (20 nm) are sequentially laminated, and a Si○2 film 15 (200 nm) is formed as a cap layer thereon.
nm). The above crystals were heated at 800°C11 in H2.
Anneal for 5 minutes.

By annealing, Ga in the crystal diffuses into 5in2, thereby generating Ga vacancies. Mutual diffusion of Si, An, and Ga occurs through these Ga vacancies, resulting in the result shown in Fig. 1(b).
As shown in <Si-doped AQGaAs13 and Si-doped G
A graded layer 16 is formed at the interface of the aAs 14.

Since this graded layer is formed by interdiffusion of Ga and Ga from layers 13 and 14, there is no change in the overall film thickness, and the interface between 1 and 1 (-Afl GaAs 12 and undoped GaAs 11) is a heterojunction. form,
Steepness is maintained. The thickness of the graded layer] 6 is arbitrarily controlled by the annealing temperature.

Figure 2 shows the CAT method (Composition Aral
ysjs by T hickness Fringe
Figure 2 shows the annealing temperature dependence of the graded layer thickness, as measured directly by the method.

The thickness of the graded layer shows a very controllable increase in the range from 650°C to 800°C.

Note that the annealing conditions in Figure 2 are annealing time of 15
The temperature was fixed at 10 minutes, and the processing temperature was varied. Contrary to this condition, similar results can be obtained by fixing the temperature and varying the time. Therefore, the thickness of the graded layer is
Since it is a function of temperature and time, the desired thickness can be achieved by setting either or both of them to appropriate conditions.

In addition, the thickness of the undoped All Ga As 12 changes from Si doped AAGaAs 13 to Si during annealing.
Even if there is diffusion, a region that is not sufficiently diffused remains, and no change is brought about at the interface between layer 13 and layer 12.

Therefore, the graded layer 16 is selectively and reliably realized only at the target interface between the layer 14 and the layer 13.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

First, as shown in FIG. 3(a), M is placed on the semi-insulating substrate 1.
Undoped GaAs (1ρ)2, undoped AQo, 3Gao, 7As (20nm) 3, S by BE method
i-dope A11. ．． 3Ga, 7As (21 nm,
Si concentration 2.4 x 10"cm-3) 4. Si-doped GaAs (160 nm, Si concentration 3.5 x 10
"cm-3)" is epitaxially grown in sequence.Next, the third
Turning to Figure (b), a 5 in 2 film (200 nm) 7 is deposited on the crystal surface by the CVD method and annealed in an H2 gas flow. The annealing conditions are 800° C. and 15 minutes. Si-doped All by annealing. , 3Gao, 7As
Disorder occurs between Si-doped GaAs 4 and Si-doped GaAs 5, and a graded layer 6 is formed. FIG. 4 shows the depth distribution of Af1 composition measured by the CAT method.

It can be seen from both FIG. 2 and FIG. 4 that the thickness of the graded layer 6 is approximately 14 nm, and the thickness of the graded layer 6 is approximately 14 nm. ,3Ga,
, , As3 interface does not become disordered. In addition, for reference, FIG.
wn) and after annealing are shown in comparison. This figure also shows that within the graded layer, Al
It can be seen that l has a constant concentration gradient in the thickness direction of the layer.

Returning again to FIG. 3(b). Since the thickness of the graded layer 6 at the hetero interface matches the diffusion distance of Si, it is Si-doped All. , 3Ga, , undoped Al from 7As4
l. ,3Ga(,,7As3A diffused Si makes sj
Dope An. ,,Gao,,As4 film thickness is 35 nm,
Undoped All. , 30a, , the film thickness of 7As3 is 6
nm.

Next, FIG. 3(c) shows a cross-section of a field-effect transistor (FET) formed by forming source, drain, and gate electrodes using the usual method on the crystal having the structure shown in FIG. 3(b). The figure is shown below.

The process diagram for forming each electrode has been omitted, but to explain the outline, photolithography is used to deposit and lift off the AuGe alloy that will become the source/drain electrode material.
A drain electrode 8.8' is formed. Furthermore, after recess etching the gate electrode formation region, Afl is deposited and lifted off as a gate electrode material to form the gate electrode 9.
A field effect transistor (FET) is completed. Note that the contact resistance between AAGaAs4 and GaAs5 in this FET was reduced to 1/10 compared to before annealing.

〔Effect of the invention〕

According to the invention, for example 2DEG (Two-D im
Because a graded layer can be selectively formed in a predetermined region in the depth direction after crystal growth in an FET (abbreviation for 1electron gas), it is possible to reduce the contact resistance at the hetero interface, and to reduce the film thickness between wafers. It is possible to form a graded layer with high throughput without any variation.

In addition, by controlling the annealing temperature, Si
Since the diffusion distance of can be controlled, it has the effect of suppressing short channel effects in field effect transistors.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram for explaining the present invention in detail, FIG. 2 is a characteristic diagram showing the relationship between annealing temperature and graded layer thickness, and FIG. 3 is a cross-sectional configuration diagram for explaining one embodiment of the present invention. FIG. 4 is a characteristic curve diagram showing the distribution of Al1 composition in the depth direction. 1.10... Semi-insulating GaAs substrate 2... Undoped GaAs 3.12-... Undoped M Ga As s6.16
... Graded layer 4.13-8i doped An Ga As 5.14-
=Si-doped GaAs 7.15...SiO□ film 11...Undoped GaAs Attorney Junnosuke NakamuraLr1L+Or+-0F■

Claims (1)

[Claims] 1. A III-V compound semiconductor layer doped with an impurity element that determines the conductivity type is formed on a semiconductor substrate, and a heterojunction is formed with the III-V compound layer, and the impurity element a step of sub-epitaxially growing a III-V compound semiconductor layer doped with the same impurity element as the element; By forming a cap layer that can be easily diffused in a subsequent annealing step and by annealing the thus obtained multilayer structure in a non-oxidizing atmosphere, the interface where the heterojunction is formed is disordered. and forming a graded layer having a concentration gradient of group III elements in the thickness direction. 2. On a semiconductor substrate, a first III-V compound semiconductor layer, a second III-V compound semiconductor layer forming a heterojunction with the first III-V compound semiconductor layer, and a conductivity type said second III- doped with an impurity element determining
A third compound semiconductor made of the same type of compound semiconductor as the V group compound semiconductor.
a III-V group compound semiconductor layer, which is the same type as the first III-V group compound semiconductor doped with the same impurity element as the impurity element forming a heterojunction with the third III-V group compound semiconductor layer; Fourth III-V made of compound semiconductor
A step of sequentially epitaxially growing a group III-V compound semiconductor layer, and then a group III element constituting the fourth group III-V compound semiconductor layer is easily grown on the fourth group III-V compound semiconductor layer in a subsequent annealing step. By forming a cap layer that can be diffused into the cap layer and annealing the multilayer structure obtained in this way in a non-oxidizing atmosphere, disorder is created between the third and fourth III-V compound semiconductor layers. and forming a graded layer having a concentration gradient of group III elements in the thickness direction. 3. The thickness of the second group III-V compound semiconductor layer forming the above-mentioned heterojunction is made of a compound semiconductor of the same type as the second group III-V compound semiconductor doped with an impurity element formed thereon. The thickness is set to be greater than the distance from the third III-V group compound semiconductor layer to which the impurity diffuses during annealing, and even after annealing, the second III-V
A claim characterized in that the second group III-V compound semiconductor is epitaxially grown on the first group III-V compound semiconductor layer so that a residual region in which the impurity element is not diffused is formed in the group compound semiconductor layer. Item 2. A method for manufacturing a semiconductor device according to Item 2. 4. The method of manufacturing a semiconductor device according to claim 1 or 3, wherein the thickness of the graded layer is controlled by arbitrarily controlling at least one of temperature and time during annealing. 5. The first III-V compound semiconductor is made of GaAs,
The second III-V compound semiconductor is made of AlGaAs, the impurity element is Si, and the cap layer is made of SiO.
_2. The method of manufacturing a semiconductor device according to claim 2, 3 or 4. 6. Forming source and drain electrodes on a fourth III-V compound semiconductor layer made of a compound semiconductor of the same type as the first III-V compound semiconductor doped with an impurity element that determines the conductivity type; 6. The method of manufacturing a semiconductor device according to claim 2, wherein a field effect transistor is formed by forming a gate electrode between both electrodes.