JPH02235428A - Voltage controlled oscillator - Google Patents

Abstract

PURPOSE:To attain the stable operation of an oscillator over a wide frequency range by providing a ring oscillator employing plural delay elements whose delay time is selectible and a delay time selection circuit selecting any selection time and outputting the result and making the oscillating frequency variable with the selection. CONSTITUTION:The ring oscillator 1 is constituted of plural pulse delay elements (2-1)-(2-n) connected in cascade and the output terminal of the component 2-n at the final stage is connected to the input terminal of the component of a 1st stage via an inverter 3. The output pulse width of each component 2 is controlled by a voltage applied to the input terminal VRL, and the delay time of the pulse outputted from the output terminal 01 with respect to the pulse applied to the terminal 11 is selected depending onto which terminal of terminals SA, SAB, SB, SBB, SC and SCB the signal is to be applied. The output terminal of each component 2 is connected to output terminals T0, T1-T18, T19 via a buffer 4 or an inverter 5 to extract an output clock pulse from any of the terminal T0-T19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage-controlled oscillator used in a phase-controlled loop (PLL) or the like.

[Prior Art] A digital phase control loop outputs a signal indicating +1 (lead) or -1 (lag) when a square wave input signal and output signal are input to a binary quantization phase comparator. It is input to the digital vCO.

A pulse from the oscillator is removed to retard the output when the output is leading the input, a pulse is added when the output is lagging the input, and the output is divided to output the binary quantum The pulse wave is fed back to the phase comparator, and a pulse wave whose phase is controlled in this way is obtained.

[Problems to be Solved by the Invention] However, the voltage-controlled oscillator (VCO) used in the conventional PLL has a narrow applicable frequency range, and when this frequency range is widened, the oscillation frequency becomes unstable.

Therefore, an object of the present invention is to provide a voltage controlled oscillator that operates stably over a wide frequency range.

[Means to solve the problem] The above purpose. In order to achieve this, the voltage controlled oscillator of the present invention includes a ring oscillator configured using delay elements capable of selecting a plurality of delay times, and a delay time selection circuit that outputs a signal for selecting one of the delay times. , the oscillation frequency is made variable by selecting the delay time.

[Example] In FIG. 1, a ring oscillator 1 is made up of a plurality of pulse delay elements 2 (2-1.2-2.-.2-n) connected in cascade, and the final stage delay element 2-n. The output terminal is connected via the inverter 3 to the human power terminal II of the first stage delay element 2-1. Note that inverter 3 is delay element 2
is used when there is an even number of

The output pulse width of each delay element 2 is controlled by the voltage applied to the human power terminal vRl, and the terminal! The delay time of the pulse output to the output terminal Ol with respect to the pulse applied to the terminals SA, SAB, SB. S.B.B., S.C. S
The selection can be made depending on which terminal of CB the signal is applied to.

The output terminals of each delay element 2 are connected via a buffer 4 or an inverter 5 to output terminals TO, TI. ..., Tl8. T1
9 and which of the above terminals TO. Tl...
．． TlB. The output clock pulse can also be taken out from T19. A detailed configuration of each delay element 2 is shown in FIG.

A control voltage supply circuit 10 supplies a predetermined voltage to the V[11 terminal of the delay element 2. Details of this control voltage supply circuit 10 are shown in FIGS. 3 and 4.

A decoder 20 selects the delay time fil of the delay element 2, and outputs a signal to either SA or SCB according to the input signals Sl and SO. The decoder 20 is composed of an inverter 21, a NAND gate 22, and another inverter 23.

In the circuit shown in FIG. 1, when a predetermined voltage signal VREF is applied to the input terminal It of the control voltage supply unit IO and this voltage is supplied to the VRl terminal of the delay element 2,
The delay element 2 has a . Accordingly, the time tpLH (see FIG. 5) on the terminal side of the output pulse changes, and the frequency loss of the output pulse from the delay element 2 changes. On the other hand, terminals SA, SAB.・・・． The pulse delay time in each delay element 2 is selected depending on which of sC and SCB the signal is applied to. As a result, the ring on rate l
According to the magnitude of the voltage VREF, clock pulses having various pulse frequencies and pulse delay times can be obtained from any of the terminals TO to T19.

The details of each part of the circuit shown in FIG. 1 will be explained below.

In FIG. 2, the delay element 2 is connected to an inverter 7 whose delay time tpLH at the end of the pulse changes as shown in FIG. 5 depending on the magnitude of the voltage applied to the voltage terminal VRO.
A delay circuit connected in series? 1, 72, 73.74 are connected in cascade, and the output terminals 70-1.70-2.70-3 of each delay circuit 71, 72.73 are connected to AND gates 8al, 8a2, 8a3, and An output terminal 70-4 of the delay circuit 74 is connected to an AND gate 8b3.

A NO game that receives the outputs of AND gates 8a3 and 8b3}
The output of 9-3 is connected to AND gate 8b2 via inverter 9-4. In addition, andgame}8a2.8
The output of NOR gate 9-2 receiving the output of AND gate 8b is connected to AND gate 8b via inverter 9-1. The output of the NOR gate 9 receiving the output of the AND gate 8a1.8bl is connected to the output terminal Ol. Each AND gate 8al. 8a2, 8a3.8bl. Signals SA, SAB, SB, .
It is configured such that one of the output pulses 2.70-3.70-4 is selectively output to the output terminal 01.

The configuration of the inverter 7 is shown in FIG.

71 and 72 are p-channel MOS transistors, and 73 is an N-channel MOS transistor.

An inverter is configured with transistors 72.73, the input is 11, and the output is 01. The transistor 7l is Id
s, and VRO is a control voltage terminal. As mentioned above, the VRO can control tpL}I in the time chart of FIG.
The relationship between tpt and H is shown in Figure 6. Shown below.

Next, the configuration of the control voltage supply 10 is shown in FIG. A current mirror circuit is constituted by transistors of t 1.12.13. Transistor! The circuit consisting of 4.15.16 uses p-channel transistor 2 as a current mirror circuit, and controls the current with transistors 1l and 12, or applies voltage Vcc to the gate of transistor 1l to turn it off, and transistor 11 alone controls the current. This is for selecting whether to control based on the value of the SE terminal.

Resistor 17 is the control voltage supply section manual terminal ■! Even if the voltage of transistor 13 is turned off because the voltage of
It has a resistance value such that the threshold voltage Vcc-Vtp is 1, and is made of polysilicon or diffusion.

The relationship between If and Ol of the control voltage supply section 10 is expressed as
As shown in the figure.

TO. of the VCO shown in FIG. T.I. Or T18,
A time chart of Tl9 is shown in FIG.

In the embodiment shown in FIG. 1, there are 20 variable delay elements 2, so the TO-TI phase shift is l/20fO. Human power voltage V
FIG. 9 shows the relationship between REF and rO. Each selection terminal So
, 91, and the relationship between the SE settings and the output frequency are shown in Table 1.

FIG. 10 shows an embodiment in which the above-mentioned CO according to the present invention is used in a conventional phase control loop (PLL), and 100 is a VCO according to the present invention. 101 is a frequency divider, 102 is a phase comparator, and 103 is a low-pass filter.

The input of vcotoo is the circuit in Figure 1 +7) VrtEF
is used, and the output is connected to one of TO to Tl9.

The phase comparator 102 outputs a phase difference L between the reference clock A and the clock B of the VCO 100.
Charge and discharge to PF l 0 3.

When this PLL is locked, a clock pulse at the frequency of the reference clock n signal is obtained from the CLKOUT terminal.

When using the VCO according to the present invention, the selection signal combinations shown in Table 1 result in VRE as shown in FIG.
The characteristics of F and frequency fO are obtained, the slope of VREF-[0 remains small, that is, the locked frequency is stable, and the band of fO can be set arbitrarily according to the application. This has the advantage that the upper and lower limits of the selectable frequency range are wide.

FIG. 11 shows a second embodiment using the vCO of this invention. In this embodiment, the clock pulse is VCo 1 0
0 output terminals TO to Tl9.

In the CO shown in FIG. 1, since 20 pulse delay elements 2 are connected, 20 Fl clocks having the same frequency and equally shifted phases can be extracted. These CLKOU
The phase shift ratio of the clocks T(T)0 to (T)19 is constant regardless of the frequency of the reference clock. Therefore, if one of CLKOUT(T)0 to (T)19 is used to create a delay or is used as a multiphase clock, even if the frequency of the reference clock oscillator is changed, the internal circuit will not be able to adjust the delay amount. There is no need to select a new clock. That is, regardless of the frequency of the reference clock,
The phase difference between TO and TI remains unchanged at 5%.

A third embodiment is shown in FIG. 104 is a trigger signal T
This circuit detects the rise or fall of RIG and selects from the TO-T 19 a clock pulse that falls or falls after a certain delay from the detected time.

FIG. 13 shows the relationship between the trigger signal TRIG and the clock pulse output CLKOUT obtained from this embodiment. α is an error, and a clock synchronized with TRIG can be obtained within this error range.

FIG. 13 shows an example of the operation of the selection circuit 104.

Note that in FIG. 13, the delay amount D is calculated using the following formula.

! D = -X m+α [sec] r0 * Number of terminals taken out from VCO As shown in the above-mentioned embodiments, ■CO according to the present invention can be configured with logic elements and MOS transistors, so it can be easily integrated into an integrated circuit. Also, in the PLL shown in FIGS. 10 to 12, not only the VCO 100 but also the frequency divider 1
01, the phase comparator l02 can also be integrated into an integrated circuit, and the PLL can be made compact.

The voltage controlled oscillator of the present invention includes an inverter having a manual terminal and means for controlling either the charging current or the discharging current, or both, for propagating a signal to the next stage gate. A device in which a ring oscillator is constructed by cascade-connecting variable delay units whose input terminals and output terminals have opposite logic, and the voltage value of a voltage control signal manually input from the outside and the voltage value of a voltage control signal input manually from the outside. The inverter may include a device having means for outputting a predetermined continuous voltage value to all of the inverter elements in response to a mode selection signal.

[Effects of the Invention] As detailed above, the present invention connects a plurality of stages of variable pulse width elements to form a ring oscillator to form a variable pulse frequency vCO. As shown in Figure 9, the characteristics of VREF and frequency dispersion fO are obtained, and the slope of VREF-[0 remains small,
In other words, it has the advantage that the locked frequency is stable and fixed, and that the 0 band can be set arbitrarily depending on the application, and the upper and lower limits of the selectable frequency range are wide. be.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the voltage controlled oscillator of the present invention, Figure 2 is a detailed circuit diagram of a variable element used in the embodiment of Figure X, and Figure 3 is the circuit of Figure 2. FIG. 4 is a detailed circuit diagram of the control voltage supply section used in the embodiment of FIG.
Figure 5 is a waveform diagram showing the operation of the variable circuit used in the circuit of Figure 1, Figure 6 is a graph showing the relationship between RO and tpLH, Figure 7 is the input voltage and output of the control voltage supply section. A graph showing the relationship with voltage; FIG. 8 is a waveform diagram showing an example of pulses obtained at each output terminal of the embodiment shown in FIG. 1;
FIG. 9 shows the input signal SO. Graphs showing changes in the frequency of the pulses obtained for S1 and SE, Figures 10 to 1
2 is a circuit diagram showing an example of a phase control loop using the embodiment of FIG. 1, and FIG. 13 is a waveform diagram showing the operation of the main part of the embodiment of FIG. 12. DESCRIPTION OF SYMBOLS 1... Ring oscillator, 2... Pulse delay element, 3... Inverter, 4... Buffer, 5... Inverter, IO... Control voltage supply part, 20... Decoder,

Claims (1)

[Claims] (1) Equipped with a ring oscillator configured using delay elements capable of selecting a plurality of delay times and a delay time selection circuit that outputs a signal for selecting one of the delay times, the oscillation frequency can be adjusted by selecting the delay time. A voltage controlled oscillator characterized by being variable.