JP2870839B2 - Delay circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a delay circuit device that can be used for a PLL circuit or the like.

[Prior art and its problems] In a delay circuit, it is conventionally impossible to create a signal that is delayed with a constant ratio to the period of a supplied clock signal, and a delay close to a desired delay time has been impossible. Instead of a delay circuit that generates

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a delay circuit device that creates a signal that is delayed at a fixed ratio with respect to a period of a supplied clock signal. And

[Means for Solving the Problems] According to the present invention, a voltage supply unit that generates a predetermined continuous voltage value according to the voltage value of a voltage control signal, and the voltage is supplied from the voltage supply unit An oscillator for generating a signal having a predetermined period; comparing the phase of a frequency or a frequency-divided frequency of a signal transmitted by the oscillator with a frequency of a reference clock signal supplied from outside; A delay circuit device comprising: a phase comparison unit that sends out a signal; and a delay circuit that delays an externally supplied signal based on a voltage value supplied from the voltage supply unit. A variable delay component that is cascade-connected to each of which a voltage is supplied from the voltage supply unit and delays a signal to be transmitted based on the voltage; and use of the cascade-connected variable delay components. And a decoder for transmitting a selection signal for selecting the number of stages and selecting a band at the time of delay.

[Operation] With this configuration, a circuit configured by the voltage supply unit, the oscillator, and the phase comparison unit generates a voltage to be supplied to the delay circuit. This voltage changes according to the cycle of the output signal of the oscillator which changes according to the change of the cycle of the reference clock signal supplied to the phase comparator. The delay circuit controls the delay time according to the voltage value when the voltage is supplied, and delays a signal supplied from the outside, so that the delay circuit has a fixed ratio to the output signal period of the oscillator. Delay the supplied signal.

[Embodiment] In FIG. 1 showing the configuration of an embodiment of a delay circuit device according to the present invention, a signal having a certain period transmitted by a 1 / n divider 5 and a reference clock signal serving as a reference are supplied. The output of the phase comparator 1 for comparing the phase difference between these signals is:
It is connected to a control voltage supply unit 3 via a low pulse filter (hereinafter referred to as LPF) 2. The control voltage supply unit 3 is a circuit that generates a predetermined voltage based on a signal transmitted from the LPF 2, and its output side is a voltage-controlled oscillator (hereinafter referred to as a VCO) that generates a clock signal of a predetermined cycle according to the supplied voltage. 4) and a control voltage terminal 6a of a variable delay unit 6 for delaying a signal supplied from an external device. The output side of the VCO 4 is connected to the clock signal output terminal 30 and to the input side of the 1 / n frequency divider 5.

Thus, a PLL loop is formed by the phase comparator 1, the LPF 2, the control voltage supply unit 3, the VCO 4, and the 1 / n frequency divider 5.

Among the components described above, the configuration or operation of the main components will be described below.

As shown in FIG. 2, the VCO 4 includes a variable delay component 10 for delaying a signal to be transmitted based on the voltage VR1 supplied from the control voltage supply unit 3, and a plurality of stages of the variable delay components 10 connected in cascade. It has a decoder 12 for sending a selection signal for selecting whether or not to use up to the eye to the variable delay configuration unit 10.

The output side of the control voltage supply unit 3 shown in FIG.
The output side of the inverter 11 is connected to the control voltage terminal 10a of each of the cascade-connected variable delay components 10 and is connected to the output side of the variable delay component 10-n, which is the nth variable delay component. The ring oscillator is connected to the input side of the delay configuration unit 10-1 and includes the variable delay configuration units 10-1 to 10-n and the inverter 11. The inverters 27a and 27b are connected to the output sides of the variable delay components 10 located at even-numbered positions, such as the variable delay components 10-2, 10-4,.
Are connected in series to form output sections of output signals obtained by delaying the supply signal I1 of the respective variable delay components 10. The signal transmitted by the inverter 27b in the output section of the variable delay configuration section 10-2 is T0, the signal transmitted by the inverter 27a is T0B, and the signal transmitted by the inverter 27b in the output section of the variable delay configuration section 10-4 is T1. The signal transmitted from the inverter 27a is sequentially denoted by T1B, and so on.

In addition, a signal for selecting a band at the time of variable delay, that is, a signal for selecting how many of the variable delay components 10 are used is provided to each of the variable delay components 10, and is supplied to a selection signal input terminal. Is connected to the output side of the decoder 12 that creates the selection signal by the supplied digital signal consisting of two bits S0 and S1. Table 1 shows the digital signals.
It shows the truth values of the selection signals SA, SB, SC based on the digital values of S0, S1.

As shown in FIG. 3, the variable delay configuration unit 10 includes an inverter 13 for controlling the delay time by a signal VR1 supplied from the control voltage supply unit 3, and the selection signals SA, SB,
It comprises a gate circuit 14 to which SC and the like are supplied.

Each inverter 13 is connected in series, and the output side of the even-numbered inverter 13 is connected to the input side of each gate circuit 14 connected in series.

As shown in FIG. 4, the inverter 13 includes P-channel transistors 15a and 15b and an N-channel transistor 16, and the transistor 15b and the transistor 16 constitute an inverter. 15b and the gate of the transistor 16,
The output signal O1 is sent from the drain side of the transistor 15b. Transistor 15a is the source of transistor 15a,
This is a gate for controlling the amount of current between drains, and the output voltage VR1 of the control voltage supply unit 3 is applied to the gate of the transistor 15a. As shown in FIG. 5, the output voltage VR1 is a voltage for controlling a delay time TpLH between the fall of the input signal I1 and the rise of the output signal O1, and the relationship between the output voltage VR1 and the delay time TpLH is as follows. As shown in FIG. 6, the delay time can be reduced by increasing the value of the output voltage VR1.

Next, the control voltage supply unit 3 has a configuration as shown in FIG. 7, in which the output side of the LPF 2 shown in FIG. 1 is connected to the gate of an N-channel transistor 19, and the source side of the transistor 19 is a P-channel And to the output terminal 20.
The drain of the P-channel transistor 17 is connected to the output terminal 20.

The transistors 17, 18, and 19 form a current mirror circuit. Transistors 21, 22, and 23 use transistor 17 as a current mirror circuit, and transistors 17, 18
To control the current, or to the gate of transistor 17
This is for applying the VCC to turn off the transistor 17 and controlling the current by the transistor 18 alone or selecting by the signal supplied to the SE terminal 24. Even if the voltage value supplied from the LPF 2 becomes equal to or less than the threshold value of the transistor 19 and the transistor 19 is turned off, the resistance
Have a resistance value which does not exceed the threshold value of the transistor 15a shown in FIG. FIG. 8 shows the relationship between the output voltage value I1 of the LPF 2 and the output voltage value O1 of the control voltage supply unit 3. That is,
Even if the output voltage value I1 of the LPF 2 is the same, the output voltage value O1 can be changed by the SE signal value supplied to the control voltage supply unit 3.

Control voltage supply unit 3 configured as described above
FIG. 9 shows a time chart of the output signals T0, T1,... Tn, T0B, T1B,. The phase difference between each adjacent output signal is 1 / (2 · n
・ It is expressed by f0). Fig. 10 shows the output voltage of LPF2.
The relationship between Vref and the frequency f0 of the signal sent from VCO4 is
The signals are shown according to the case of the SE signal supplied to the control voltage supply unit 3 and the signals S0 and S1 supplied to the decoder 12 of the VCO 4. The conditions for the signals SE, S0, and S1 are shown in Table 2. As shown in FIG. 10, VCO4 is selected by appropriately selecting the signal values of SE, S0, and S1.
Thus, the frequency of the transmitted signal can be changed.

Next, the configuration of the variable delay unit 6 is shown in FIG. 11, the variable delay configuration unit 28 has the same configuration as the variable delay configuration unit 10 shown in FIG. 2, and the output signal of the decoder 29 is supplied to the variable delay configuration unit 28. . decoder
Reference numeral 29 denotes a circuit having the same configuration as that of the decoder 12 and performing the same operation, and sends out a selection signal for selecting a band at the time of variable delay based on the S0 'and S1' signals supplied as described above. The variable delay unit 6 selects the band at the time of variable delay by the selection signal sent from the decoder 29, and converts the input signal I1 'supplied from the external device to the voltage value supplied from the control voltage supply unit 3. This is a circuit that delays by an appropriate delay time and sends it out as an output signal O1 '.

The operation of the delay circuit device configured as described above will be described below.

By transmitting a signal of an appropriate frequency from the VCO 4, the cycle of the reference clock signal supplied to the phase comparator 1 and the VC
The period of the signal transmitted by O4 is divided by a 1 / n frequency divider 5, and the phase difference from the period of the signal transmitted from the frequency divider 5 is detected by the phase comparator 1, and the phase comparator 1 Sends a signal having a cycle corresponding to the phase difference to the control voltage supply unit 3 via the LPF 2. The control voltage supply unit 3 generates a voltage of a predetermined value based on the supplied signal and sends it to the VCO 4. The VCO 4 sends out a signal of a certain period based on the supplied voltage value. In this manner, the PLL loop including the phase comparator 1, the LPF 2, the control voltage supply unit 3, the VCO 4, and the 1 / n frequency divider 5 gradually enters a steady state, and the control voltage supply unit 3
Is also in a steady state. The voltage in the steady state is also supplied from the control voltage supply unit 3 to the variable delay unit 6.

In the above-mentioned PLL loop, if the period of the reference clock signal supplied to the phase comparator 1 is changed, the steady state is broken, and a new steady state is generated in the PLL loop, and the control voltage supply unit 3 changes the variable delay unit. The voltage supplied to 6 will also change.

The signal sent by VCO4 is the decoder shown in FIG.
The delay time can be adjusted by changing the signals of S0 and S1 to be transmitted to 12, and by increasing or decreasing the number of stages of the variable delay configuration unit 10.

On the other hand, as described above, the control voltage supply unit 3
Since the predetermined voltage value transmitted from the VCO 4 is also supplied to the variable delay unit 6, the variable delay unit 6 changes the predetermined voltage value according to the change in the predetermined voltage value, that is, the change in the frequency of the signal transmitted from the VCO 4.
As shown in FIG. 12, as shown in FIG.
Delay 1 '. Therefore, the input signal I1 'is delayed according to the change of the frequency f0 of the output signal of the VCO4, and a delay can be obtained in which the delay ratio of the cycle of the input signal to the cycle of the output signal of the VCO4 does not change.

Note that the signals S0, supplied to the decoder 12 and the decoder 29,
When the values of S1, S0 'and S1' are the same, the delay time shown in FIG. 12 is represented by (1 / (2 · f0)) × (m / (2 · n)). . Here, m is the number of stages of the variable delay configuration unit 28 in the variable delay unit 6, and n is the variable delay configuration unit in the VCO4.
The number of stages is 10.

The delay ratio can be changed by changing the values of S1 'and S2' supplied to the decoder 29 constituting the variable delay unit 6. Further, in this embodiment, the decoder 12 provided in the VCO 4 and the decoder 29 provided in the variable delay unit 6 are separate, and the signals S
Since each of 0, S1, S0 ', and S1' can be set separately, the delay ratio can change the delay ratio in the VCO 4 and the delay ratio in the variable delay unit 6, respectively. Further, by providing only one of the decoder 12 and the decoder 29 and sharing the VCO 4 and the variable delay unit 6, the delay ratio in the VCO 4 and the delay ratio in the variable delay unit 6 can be made the same. It is possible.

In the above-described delay circuit device, the other components except the LPF 2 can be formed by CMOS, and can be incorporated in the semiconductor integrated circuit.

[Effects of the Invention] As described above in detail, according to the present invention, the voltage for controlling the operation of the delay circuit changes in accordance with the change in the signal transmitted from the oscillator, and thus the signal supplied to the delay circuit is changed. The delay ratio with respect to the oscillator transmission signal can be kept constant.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the delay circuit device of the present invention, FIG. 2 is a logic circuit diagram showing the configuration of the VCO shown in FIG. 1, and FIG. 3 is a variable delay shown in FIG. FIG. 4 is a circuit diagram showing the configuration of the inverter shown in FIG. 3, FIG. 5 and FIG. 6 are diagrams showing the operation of the inverter shown in FIG. 3, and FIG. Is a circuit diagram showing the configuration of the control voltage supply unit shown in FIG. 1, FIG. 8 is a graph showing the operation of the control voltage supply unit, and FIGS. 9 and 10 are diagrams showing the operation of the VCO shown in FIG. FIG. 11 is a block diagram showing the configuration of the variable delay unit shown in FIG.
The figure shows the operation of the variable delay unit. 1 ... Phase comparator, 3 ... Control voltage supply unit, 4
... VCO, 6 ... Variable delay unit.

Claims (1)

(57) [Claims] A voltage supply unit for generating a predetermined continuous voltage value according to a voltage value of a voltage control signal; and an oscillator for generating a signal of a predetermined cycle by supplying the voltage from the voltage supply unit. And a phase comparator for comparing the phase of the frequency or frequency-divided frequency of the signal transmitted by the oscillator with the frequency of a reference clock signal supplied from the outside, and transmitting a signal serving as a basis of the voltage control signal. A delay circuit for delaying a signal supplied from the outside based on a voltage value supplied from the voltage supply unit, wherein the delay circuits are cascaded in a plurality of stages, and each of the delay circuits has the voltage A variable delay component that is supplied with a voltage from the supply unit and delays a signal to be transmitted based on the voltage; and a band at the time of delay by selecting the number of use stages of the variable delay components connected in cascade. Delay circuit apparatus characterized in that it comprises a decoder for sending a selection signal for selecting the.