JPH02231724A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakdown of metal wirings by forming a polycrystalline silicon film on trenches formed in an insulating film and a semiconductor substrate and a recess in the surface, polishing the film, flattening the trenches and the surface, forming a hole in an inner base and an emitter by etching, and providing an external base lead-out part. CONSTITUTION:An insulating film 4 in which a hole for forming a base and an emitter is provided is formed on a semiconductor substrate 1. The insulating film 4 and the semiconductor substrate 1 are selectively etched, and trenches 1A are formed. Then, a polycrystalline silicon film 10 which fills the trenches 1A and the recess in the surface is formed. The polycrystalline silicon film 10 is mechanically polished, and the bulk surface including the trenches 1A and the recess is flattened at the same time. Then, the polycrystalline silicon film is selectively etched, and a hole for forming an inner base 17 and an emitter 19 is provided. The polycrystalline silicon film is patterned as an external base lead-out part. In this way, a ground of a metal wiring is flattened, and wire breakdown is prevented.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method that is popular for manufacturing at low cost a semiconductor device having a trench-type isolation structure between elements and having a flattened surface. A process of forming an insulating film with openings for forming a base and an emitter on a semiconductor substrate, with the aim of simultaneously filling the trench with polycrystalline silicon and planarizing the bulk. Then, a step of selectively etching the insulating film and the semiconductor substrate to form a trench for isolation between elements, and a step of forming a polycrystalline silicon film to fill the trench and the recess on the surface. then mechanically polishing the polycrystalline silicon film to simultaneously planarize the bulk surface including the trenches and recesses; The method includes the steps of selectively etching the silicon film to form openings for forming an internal base and emitter, and patterning the polycrystalline silicon film as an external base extension portion. [Industrial Application Field] The present invention relates to a method suitable for manufacturing at low cost a semiconductor device having a trench-type element isolation structure and having a flat surface. It goes without saying that semiconductor devices are now trending towards higher integration, but to achieve this it is essential to miniaturize wiring patterns and increase the number of layers of wiring. Therefore, uneven surfaces often occur in the base of metal wiring, which is causing an increasing number of accidents that lead to disconnection of metal wiring. To prevent this, it is necessary to flatten the base of the metal wiring, but flattening the metal wiring increases the number of steps and increases costs.
Problems such as decreased manufacturing yield must not occur. [Prior Art] FIGS. 11 to 19 are cross-sectional side views of essential parts of a semiconductor device at key process points to explain a conventional technique for manufacturing a high-speed bibolar semiconductor device called an ESPER type.
A detailed explanation will be given below with reference to these figures.

Refer to FIG. 11 α-1 Using a conventional technique, a silicon semiconductor substrate is fabricated with an n+ type buried layer 2, an n1 type silicon semiconductor layer 3, a field insulating film 4 made of silicon dioxide and having a thickness of, for example, about 6000 [layers]. An ni type collector contact region 5 is formed. Note that the illustrated field insulating film 4 has openings for forming a base region and emitter region, and an opening used for forming an n+ type collector contact region 5.

See Figure 12 -1 Chemical vapor deposition
By applying the deposition (CVD) method, an oxidation-resistant mask film 7 made of silicon nitride having a thickness of, for example, about 1000 (people) is formed. (b)-2 Continuing to apply the CVD method Therefore, phosphosilicate glass (phosp) having a thickness of, for example, about 5000
A hosilicate GL3SS (PSG) film 8 is formed. Incidentally, this PSG film 8 serves as an etching protection when forming a trench.

(O)-3 A photoresist film (not shown) having an opening in a portion where a trench is to be formed is formed by applying a resist process in a normal photolithography technique.

(Self)-4 Add etching gas to CF. reactive ion etching (reactive ion etching)
By applying the IE) method, the PSG film 8, the oxidation-resistant mask film 7, and the field insulation wA4 are selectively etched to form a trench IA that reaches the inside of the silicon semiconductor substrate 1. Refer to FIG. 13 a3-1 After removing the PSG film 8, by applying a thermal oxidation method, the silicon portion exposed in the trench IA is made of silicon dioxide to a thickness of, for example, 1000 to 3000.
An insulating film 9 of about (1 person) size is formed.

By applying the CVD method, the thickness can be reduced, for example, from 1 to 2 [μ
m] polycrystalline silicon film 10 is formed. Depending on this, the width is about 1 [μm] and the depth is about 5C.
The trench IA with a diameter of about [μm] is completely filled, and the surface is also covered with a polycrystalline silicon film 10. a1-3 By applying a mechanical polishing method, the polycrystalline silicon film 10 is polished and planarized. As a result, only the portion of the polycrystalline silicon film 10 that filled the trench IA remains, and the rest is removed. In this case, trench IA
Although it would be thought that the polycrystalline silicon film 10 would remain in other recesses, it actually does not. The reason for this is that the polishing puff does not penetrate into narrow parts like trench IA, but it does enter into large recesses outside of it, and the polishing is performed while the polycrystalline silicon etching solution is flowing. Depends on etc. (lm-4 By applying the thermal oxidation method, the surface of the polycrystalline silicon film 10 filling the trench lA has a thickness of, for example, 4000 mm.
Form an insulating film 4A made of silicon dioxide of about 300 ml of silicon dioxide. Remove the mask film 7.Q4)-2 By applying the CVD method, the thickness is reduced to 5000, for example.
Form a polycrystalline silicon film 10A of about 100 cm (cm). α4)-3 By applying the ion implantation method, the dose can be set to about I x 10+6 (cm-"), and the acceleration energy can be set to about 25 cm. (KsV), boron (B) ions are implanted into the polycrystalline silicon film 10A. Note that to introduce impurities into the polycrystalline silicon film 10A,
Regardless of the ion implantation method described above, impurities may be added in advance when growing the polycrystalline silicon film 10A in the step α4)-2. Q41-4 Pattern the polycrystalline silicon film 10A by applying ordinary photolithography technology, and then:
Leave the part that will become the base wiring and remove the rest. (Company)-5 By applying the CVD method, the thickness can be reduced to, for example, 5000 mm.
Form an insulating film 11 made of silicon dioxide with a thickness of about 100 ml (200 cm) thick.See Figure 15 Q!9-1 By applying the spin coating method, spin on glass (sOG) is formed.
The membrane 12 is formed to have a thickness of, for example, about 5,000 (people) on a plane. By applying a controlled etching method, for example, approximately 2,000 to 3
Perform an etch back of approximately 000 (A). In this way, the sOG film 12 is deposited thickly on the recesses and thinly on the protrusions, and the surface is flattened. See Figure 16 <119-1 Resist process in normal photolithography technology and RIE using CF4 as etching gas
By applying the method, the SOG 812, the insulating film 11 made of silicon dioxide, and the polycrystalline silicon film 10A are selectively etched to form an opening 10B in the portion where the internal base region and the emitter nozzle region are to be formed. Ql9-2 By applying a thermal oxidation method, a green-free film l3 made of silicon dioxide and having a thickness of, for example, about 500 mm is formed on the silicon portion exposed in the opening 10B. -3 By applying the ion implantation method, B ions are implanted at a dose of, for example, 3×10" (c1l one town) and an acceleration energy of 25 (KeV).The B ions implanted here are: When activated later, it operates as a p-type internal base region.
An insulating film 14 made of silicon dioxide with a thickness of approximately 1,500 mm thick and a polycrystalline silicon film 15 with a thickness of, for example, 1,500 mm thick are sequentially stacked.Q?)-2 RIE using SiCIt4+Cl as an etching gas.
By applying the method, the polycrystalline silicon film 15 is anisotropically etched and the etching gas is changed to C Fa
By applying the RIE method, the insulating films 14 and 13 are anisotropically etched. As a result, polycrystalline silicon film 15 and insulating film 14 remain only on the side wall of opening 10B. Note that since the bottom surface of the insulating film 13 is etched, an opening is formed, and a portion of the n'' type silicon semiconductor layer 3 is exposed within the opening. Refer to Fig. 18 (self)-1 By applying the CVD method, the thickness is, for example, 2000 mm.
A polycrystalline silicon film 16 having a size of approximately 1000 ml (man) is formed.

By applying the 0-2 ion implantation method, arsenic (As ) Perform ion implantation.

αIt-3 Heat treatment is performed at a temperature of about 950 ('C) and a time of about 10 minutes.

Accordingly, in the step a0-3, the polycrystalline silicon film 1
B ions implanted in 0A, B ions implanted in the step Q6)-3, As implanted in the step α8l-2
Ions are diffused or activated to form operable p-type internal base region 17, p+-type external base region 18, and n+-type emitter region 19.

a--4 Patterning the polycrystalline silicon film 16 by applying ordinary photolithography technology to remove portions other than those that will become the emitter extraction electrode. Refer to FIG. 19.1 Form a base electrode contact window and a collector electrode contact window by applying a conventional technique. a-2 By applying a vacuum evaporation method, for example, an aluminum (Aj) film is formed, and this is patterned using normal photolithography technology to form an emitter electrode 20, a base electrode 21, and a collector electrode 22. and complete it. The ESPER type semiconductor device manufactured in this manner has a flat surface and has few disconnections in the emitter electrode 20, which is a metal electrode or wiring. [Problems to be Solved by the Invention] In the method for manufacturing an ESPBR type semiconductor device explained with reference to FIGS. 11 to 19, the step α1-3 is
And process Q! As explained in 9-2, a flattening process is performed by mechanically polishing the surface, applying SOG, and etch-back, and although the flatness is excellent. , is not enough. Also,
Mechanical polishing is a very good technique for bulk planarization, and if this technique is used not only for filling polycrystalline silicon into trenches, but also for bulk planarization, it is possible to improve the planarization by SOG. It is possible to achieve superior flatness compared to conventional methods. However, from a cost perspective, mechanical polishing belongs to a process that requires a lot of money, so in order to flatten the bulk, mechanical polishing is performed separately from filling polycrystalline silicon into the trench. Introducing this process is disadvantageous in terms of cost, and manufacturing costs will increase. Therefore, if it is possible to fill the trench with polycrystalline silicon and flatten the bulk with a single mechanical polishing process, manufacturing costs can be significantly reduced, and it is also possible to achieve excellent flatness. Therefore, the plausibility improves.

The present invention makes it possible to simultaneously fill the trench with polycrystalline silicon and planarize the bulk using a single mechanical polishing step.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, an insulating film (for example, a field insulating film 4) having an opening for forming a base and an emitter is formed on a semiconductor substrate (for example, a p-type silicon semiconductor substrate 1). a step of selectively etching the insulating film and the semiconductor substrate to form a trench (for example, trench IA) for isolation between elements, and then etching polycrystalline silicon to fill the trench and the recess on the surface. forming a film (e.g. polycrystalline silicon film 10), then mechanically polishing the polysilicon film to simultaneously planarize the bulk surface including the trenches and recesses; and selectively etching the polycrystalline silicon film present on the opening for forming the emitter to form an internal base (e.g. p-type internal base region 17) and an emitter (e.g. n+-type emitter region 19). The method includes the steps of forming an opening and patterning the polycrystalline silicon film as an external base extraction portion.

[Effect]

By adopting the above method, the polycrystalline silicon film filling the trench and the polycrystalline silicon film forming the base extension portion are formed at the same time, and can be flattened by one mechanical polishing. , after that, there is no need to perform bulk planarization.

〔Example〕

Figures 1 to 10 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention for manufacturing a high-speed bibolar semiconductor device called an ESPER type, similar to the prior art. will be described in detail below with reference to these figures. Note that the same symbols as those used in FIGS. 11 to 19 indicate the same parts or have the same meanings. Refer to FIG. 1. Using a conventional technique, a p-type silicon semiconductor substrate 1 is coated with an n+-type buried layer 2, an n-type silicon semiconductor layer 3, and a field insulating film 4 made of silicon dioxide and having a thickness of, for example, about 6000 mm. , an n+ type collector contact region 5 is formed.The illustrated field insulating film 4 has an opening for forming a base region and an emitter region, and an opening for forming an n+ type collector contact region 5. By applying the CVD method (see Figure 2), a thickness of, for example, 5 mm is formed over the entire surface.
000 (people).+2)-2 The resist process and etching gas in normal photolithography technology are replaced by CF. By applying the RIE method, the insulating film 6 is anisotropically etched and patterned, leaving a portion on the field insulating film 4.

By applying the CVD method (see Fig. 3), the thickness can be reduced to, for example, 1000 mm.
An oxidation-resistant mask film 7 made of silicon nitride having a thickness of about 100 ml is formed.

+3)-2 Subsequently, by applying the CVD method, a PSG film 8 having a thickness of, for example, about 5000 (people) is formed. Incidentally, this PSG film 8 serves as a protection against etching when forming the trench. +3)-3 A photoresist film (not shown) having an opening in a portion where a trench is to be formed is formed by applying a resist process in a normal photolithography technique.

The etching gas is CF. reactive ion etching:
By applying the RIB) method, the oxidation-resistant mask film 7 made of silicon nitride, the insulating film 6 made of silicon nitride, and the field insulating film 4 are etched from the surface of the PSG film 8, and the etching gas is etched by SiCj. ! 4+Ci
By applying the RIE method, selective etching is performed to reach a part of the n-type silicon semiconductor layer 3 and the p-type silicon semiconductor substrate 1, thereby forming a trench IA. The PSG film 8 is removed by applying a dipping method using hydronic acid as the etchant (see FIG. 4). By applying a thermal oxidation method, thermal oxidation is carried out in a humid atmosphere at a temperature of, for example, 900 (t) to form a silicon dioxide layer with a thickness of, for example, 1000 m on the exposed silicon portion in the trench IA.
An insulating film 9 with a thickness of about 3,000 people is formed. In this case, the area other than the trench IA is covered with the oxidation-resistant mask film 7, so it will not be thermally oxidized. Refer to Figure 5. After removing the oxidation-resistant mask film 7 by applying a dipping method, CVD
By applying the method, a polycrystalline silicon film 10 having a thickness of, for example, about l [μm] is formed.

Due to this, the width is about 1 [μm] and the depth is about 5 [μm].
The trench IA with a diameter of about [μm] is completely filled, and the surface is also covered with a polycrystalline silicon film 10. By applying a mechanical polishing method, the polycrystalline silicon film 10 is polished and planarized. This polishing is stopped when the top surface of the insulating film 6 made of silicon nitride is exposed.

As a result, the polycrystalline silicon film 10 that fills the trench IA and the recess remains, and the rest is removed. As is clear from the figure, after this step, the bulk surface is completely flattened.

By applying the ion implantation method, P ions are implanted into the polycrystalline silicon film 10 located in the collector lead-out part, and B ions are implanted into the polycrystalline silicon film 10 located in the base lead-out part. , heat treatment is performed to activate it. In order to implant P ions, the dose is set to, for example, lXIQ''(am-''), and
The acceleration energy may be set to 70 (KeV), and in order to implant B ions, the dose may be set to, for example, 1×l Q"
(cs-”), and the acceleration energy is 25 (Ka
V) is good. By applying the CVD method (see Fig. 6), the thickness of the entire surface is, for example, 5 mm.
Grow an insulating film 1L made of silicon dioxide with a thickness of about 00G (person). See Figure 7 (?)-1 Resist process in normal photolithography technology and RIE using CF4 as etching gas
By applying the method, the insulating film l1 made of silicon dioxide and the polycrystalline silicon film 10 are selectively etched to form an opening 10B in the portion where the internal base region and emitter region are to be formed. By applying a thermal oxidation method, in a humid atmosphere at a temperature of 900 [°C], the silicon portion exposed in the opening 10B is made of silicon dioxide to a thickness of, for example, 50°C.
An insulating film 13 of approximately 0 [person] size is formed. By applying the η-3 ion implantation method, B ions are implanted at a dose of, for example, 3 X I Q ” (am-”) and an acceleration energy of 25 (KaV). The B ions implanted here act as an internal base region when activated later. By applying the CVD method (see Fig. 8), the thickness can be reduced to 2000 mm, for example.
An insulating film 14 made of silicon dioxide having a thickness of approximately 1,500 (people) thick and a polycrystalline silicon film 15 having a thickness of, for example, approximately 1,500 (people) are sequentially laminated.The etching gas is S I C I 4 + C I
The polycrystalline silicon film 15 is anisotropically etched by applying the RIE method with CF. By applying the RIE method, the insulating film 14 and the insulating film 13 are anisotropically etched. As a result, the polycrystalline silicon film 15 and the insulating film 14 remain only on the side walls of the opening 10B. Incidentally, since the bottom surface of the never-green film 13 is etched, an opening is formed, and a part of the n-type silicon semiconductor layer 3 is exposed within the opening.

By applying the CVD method (see Fig. 9), the thickness can be reduced to 200 mm, for example.
By applying the ion implantation method, the dose amount is set to, for example, 5 X I Q I6 (am-"), and the acceleration energy is set to, for example, 60 (KeV). As a step, arsenic (As) ions are implanted into the polycrystalline silicon film 16.

A heat treatment is performed at a temperature of about 950 [°C] and a time of about 10 minutes. After this step, the B injected into the polycrystalline silicon film 10 in the base extension portion in step (5)-3 is removed.
ions, the B ions implanted into the n'''' type silicon semiconductor layer 3 in the step (7)-3, and the As ions implanted into the polycrystalline silicon film 16 in the step (9)-2, respectively, are diffused or A p-type internal base region 17, a p+-type external base region 18, and an n+-type source nozzle region 19 are formed which are activated and can be operated. By applying ordinary photolithography technology, the polycrystalline silicon film 16 is patterned to remove portions other than those that will become emitter extraction electrodes. See FIG. 10 α-1 Form a base electrode contact window and a collector electrode contact window by applying a conventional technique. (II-2 By applying a vacuum evaporation method, for example, an aluminum (Aj) film is formed, and this is patterned using a normal photo-phosphorography technique to form an emitter electrode 20, a base electrode 21, and a collector electrode 22. Form and complete.

In the ESPER type semiconductor device manufactured in this manner, only the polycrystalline silicon film l6 exists under the emitter electrode 20, and the surface is completely flat in other parts, and metal electrodes and wiring are disconnected. It can be said that there is no risk. [Effects of the Invention] In the method for manufacturing a semiconductor device according to the present invention, an insulating film having an opening for forming a base and an emitter is formed, and the insulating film and the semiconductor substrate are selectively etched to form a trench. forming a polycrystalline silicon film that fills the trench and the recess on the surface, mechanically polishing the polycrystalline silicon film to simultaneously planarize the bulk surface including the trench and the recess; and selectively etching the polycrystalline silicon film existing on the opening for forming the emitter to form an opening for forming the internal base and emitter, and patterning the polycrystalline silicon film as an external base extraction part. I try to do that. By adopting the above structure, the polycrystalline silicon film filling the trench and the polycrystalline silicon film serving as the base extension portion are formed at the same time, and can be completely flattened by one mechanical polishing. After that, there is no need to perform bulk planarization. Therefore, it is possible to manufacture an ESPER type semiconductor device at low cost, which is free from disconnection of metal electrodes and wiring and has high reliability.

[Brief explanation of the drawing]

1 to 10 are cross-sectional side views of essential parts of a semiconductor device at key process points for explaining an embodiment of the present invention, and FIGS. 11 to 19 are process diagrams for explaining a conventional example. Each figure shows a cutaway side view of the main parts of a semiconductor device. In the figure, 1 is a p-type silicon semiconductor substrate, lA is a trench, 2 is an n + type buried layer, 3 is an n type silicon semiconductor layer, 4 is a field insulating film, 5 is an n + type collector contact region, 6 and 7 8 is an insulating film, 8 is a PSG film, 9 is an insulating film, 10 is a polycrystalline silicon film, 11. l3. , 14 is an insulating film, 15 and 16 are polycrystalline silicon films, 17 is a p-type internal base region, 18 is a p+-type external base region, 19 is an n+-type emitter region, 20 is an emitter electrode, 21 is a base electrode, and 22 is an Each collector electrode is shown. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Kashiwatani Representative Patent Attorney: Koichi Watanabe Side view Figure 2 Figure 4 Cutaway side view of main parts of semiconductor device Figure 5 Cutaway side view of main parts of semiconductor device Cutaway side view of main parts of semiconductor equipment Cutaway side view of main parts of semiconductor device Figure 11 Figure 15 Figure 16 Figure 13 Figure 17 Figure 18

Claims (1)

[Claims] A step of forming an insulating film having openings for forming a base and an emitter on a semiconductor substrate, and then selectively etching the insulating film and the semiconductor substrate for isolation between elements. forming a trench; then forming a polycrystalline silicon film filling the trench and surface recess; and mechanically polishing the polycrystalline silicon film to form a bulk film including the trench and recess. simultaneously planarizing the surface; and then selectively etching the polycrystalline silicon film over the openings for forming the base and emitter to form openings for forming the internal base and emitter; A method for manufacturing a semiconductor device, comprising the step of patterning the polycrystalline silicon film as an external base extraction portion.