JPH02230346A - Cache memory system - Google Patents

Abstract

PURPOSE:To clear all the entries of a cache memory by installing two storage means for storing invalid information of data stored in the cache memory and clearing the content of the other storage means when one storage means is used for a normal access. CONSTITUTION:A valid bit memory part 1 is duplicated by memory banks 11 and 12. A bank selection signal 111 from a control circuit 14 decides which bank is used in which way. The memory bank 11 is used as the normal access. An output signal 116 is selected in a multiplexer 19 and is transmitted to a gate 6 as an output signal 106 from the valid bit memory part 1. When one memory bank 11 is used for the normal access, the content of the other memory bank 12 is cleared. Thus, all the entires of the cache memory can be cleared without deteriorating the performance of the system.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cache memory system, and particularly to a method for invalidating entries in a cache memory. It is generally well known that the effective main memory access time can be sped up by installing a small, high-speed backup memory between the processor and the main memory. This method is detailed in "Computing Survey" (Vol. 14, No. 3, 1982, pp. 473-530). This method is usually called cache memory, and is used in computer systems. This method is widely used. Also, this method takes advantage of the property that memory access of programs executed on a computer system has locality, and when accessing main memory from the processor, By importing contiguous storage locations of a fixed size containing words, so-called blocks, from main memory to cache memory, the majority of memory accesses can be accessed to high-speed cache memory, so it can be transferred to slower main memory. Generally, the cache memory consists of a data memory, an address tag memory that indicates the location of the data memory in main memory, and a valid bit memory that indicates the significance of the address tag. , and their memory includes RAM (
Random access memory) is used. On the other hand, in X-machine systems that use the virtual memory method, the same virtual address may be used after switching the virtual space, and in this case, even if the virtual address is the same, the contents of the data memory in the cache memory may be changed. Therefore, it becomes necessary to clear the valid pits in the cache memory. Therefore, in such cases, access from the processor should be suspended until the valid bits of all entries in the cache memory are cleared, or
Alternatively, methods are used to bypass the cache memory and directly access main memory. In such conventional cache memory systems, when clearing the valid bits of all entries in the cache memory due to virtual space switching in a computer system using virtual memory, a write cycle is performed on all addresses in the valid bit memory. During this time, access from the processor must be suspended or the cache memory must be bypassed to directly access the main memory, which has the disadvantage of reducing system performance. SUMMARY OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional systems as described above, and aims to provide a cache memory system that can clear all cache memory entries without deteriorating system performance. Purpose. A cache memory system according to the present invention includes first and second storage means for storing invalidation information indicating the validity or invalidity of data stored in the cache memory, and the invalidation information of the first storage means. When the cache access is being performed based on the invalidation information, the cache access based on the invalidation information of the first storage means is invalidated by the second storage means in response to an invalidation instruction signal for all entries of the cache memory. a switching means for switching to information-based cache access; and a switching means for switching to information-based cache access;
and clearing means for clearing the contents of the storage means. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, when performing normal operation, when an access from a processor (not shown) occurs, the access address is stored in the address register 2, and the lower address signal 101 of the access address is sent to the valid bit memory section 1 and the address The information is transmitted to the tag memory section 3 and the data memory section 4. The upper part of the memory address is stored in the address tag memory section 3, and the upper address signal 103 of the memory address read from the address tag memory section 3 by the lower address signal 101 and the access address stored in the address register 2 The upper address signal 102 of the address is compared with the higher order address signal 102 by a comparator, and it is determined whether or not these addresses match. If these addresses match, the output signal 105 from the comparator 5 becomes "1". On the other hand, since the output signal 106 from the valid pit memory section 1 indicates whether the contents of the address tag memory section 3 are correct or not, the AND operation of this output signal 106 and the output signal 105 from the comparator 5 is performed. This is performed at the gate 6, and the result of the calculation is output as a hit signal 107. That is, the hit signal 107 is transmitted to the address tag memory section 3.
becomes “1” only when the content is a fixed value and matches the upper side of the currently accessed memory address, and output data 1 from the data memory unit 4.
04 is valid. The processor determines the significance of the output data 104 from the data memory unit 4 based on the hit signal 107 from the gate 6, and if the output data 104 is invalid, it directly accesses the main memory (not shown). Next, the operation of the variable pit memory section 1 according to an embodiment of the present invention will be explained. The valid pit memory section 1 is duplicated by memory banks 11 and 12, and which bank is used and how is determined by a bank selection signal 111 from the control circuit 14. Bank selection signal 111 is “0''
At this time, the lower address signal 101 is supplied from the multiplexer (MPX) 15 to the memory bank 11 as the address input signal 118. That is, the memory bank 11 is used for normal access, and its output signal 116 is selected by the multiplexer 19 to be used as the output signal 10 from the valid bit memory section 1.
It is sent to gate 6 as 6. Further, when data from the main memory is written to the data memory section 4, the upper address of the access address at that time is written to the address tag memory section 3, and the data from the control circuit 1114 is written to the memory bank 11. A write control signal 113 of is provided as a write signal 114 from multiplexer 17;
Information indicating the significance of the data written to the data memory section 4 is written. At this time, "1" is supplied from the inverter 20 as write data to the memory bank 11. On the other hand, address information 110 from the counter 13 is supplied as the address input signal 119 from the multiplexer 16 to the memory bank 12. That is, the memory bank 12 is supplied with a clear address for the entire area of the memory bank 12 generated by the counter 13. At this time, the memory bank 12 receives the write control signal 112 output from the control circuit 14 from the multiplexer 18. is supplied as the write signal 115, and "0" is supplied as the write data.

Therefore, in the memory bank 12, the address information 110 from the counter 13 and the write control signal 1 from the control circuit 14
12, the contents are sequentially cleared to "0". When processing is performed as described above, memory bank 1
Invalidation request signal 121 for invalidating entry 1
is sent from the processor to the control circuit 14, the bank selection signal 111 from the control circuit 14 is inverted and becomes "1".
Thus, the roles of memory banks 11 and 12 are exchanged, and memory bank 12 is used for normal access, and the contents of memory bank 11 are cleared.
That is, the lower address signal 10 is used as the address input signal 119 from the multiplexer 16 to the memory bank 12.
1 is supplied and the output signal 117 from memory bank 12
is selected by the multiplexer 19 and sent to the gate 6 as the output signal 106 from the valid bit memory section 1. On the other hand, the address information 110 from the counter 13 is supplied as the address input signal 118 from the multiplexer 15 to the memory bank 11, and the write control signal 112 from the control circuit 14 is supplied as the write signal 114 from the multiplexer 17. "0" is supplied as write data via the inverter 20, and the contents of the memory bank 11 are sequentially cleared to "0". During the period when the contents of memory banks 11 and 12 are cleared, control times 1! Since fil4 outputs the busy signal 120 to the processor, when the processor tries to invalidate the entry in memory bank 11.12 during this period, the busy signal 120 from the control circuit 14 is turned off. Invalidation request signal 121 from processor until
will be put on hold. In this way, valid pit memory section 1
By duplicating the memory bank 11 and 12 with memory banks 11 and 12, and clearing the contents of the other memory bank 12 when one memory bank 11 is used for normal access, the When clearing the valid pits of all cache memory entries due to virtual space switching, etc., all entries in the cache memory can be invalidated without degrading system performance. Ritsuka Kuhada 1 As explained above, according to the present invention, the first and second storage means are provided to store invalidation information indicating the validity or invalidity of data stored in the cache memory, and the first storage means When the means is used for normal access, the second
By clearing the contents of the storage means, it is possible to clear all entries in the cache memory without degrading system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1... Valid pit memory section 1 1, 1 1 5-1 3... Address tag memory section 4... Data memory section 2... ...Memory bank 3...Counter 4...Control circuit 9...Multiplexer 0...Inverter

Claims (1)

[Claims] (1) Cache access is performed using first and second storage means that store invalidation information indicating the validity or invalidity of data stored in the cache memory, and the invalidation information of the first storage means. switching means for switching the cache access based on the invalidation information of the first storage means to the cache access based on the invalidation information of the second storage means in response to an invalidation instruction signal for all entries of the cache memory; and clearing means for clearing the contents of the first storage means in response to the invalidation instruction signal.