JPH0223030B2 - - Google Patents
Info
- Publication number
- JPH0223030B2 JPH0223030B2 JP57223053A JP22305382A JPH0223030B2 JP H0223030 B2 JPH0223030 B2 JP H0223030B2 JP 57223053 A JP57223053 A JP 57223053A JP 22305382 A JP22305382 A JP 22305382A JP H0223030 B2 JPH0223030 B2 JP H0223030B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- substrate
- sputtering
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 67
- 238000010438 heat treatment Methods 0.000 claims description 21
- 238000004544 sputter deposition Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 32
- 238000005530 etching Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
<技術分野>
本発明はスパツタリング法によつて酸化シリコ
ン(以下SiO2と略記する)膜を作成するための
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a manufacturing method for forming a silicon oxide (hereinafter abbreviated as SiO 2 ) film by a sputtering method.
<従来技術>
SiO2は、集積回路素子における多層配線の層
間絶縁膜として、或いは表面保護膜等として広く
利用されている。最近ではこれらのSiO2膜はス
パツタリング法によつて作成されることが多くな
つてきた。しかし従来から行われているスパツタ
リング法を適用して作成したSiO2膜は、熱酸化
SiO2に比べて膜密度が低く、また膜作成後の熱
処理で膜の内部応力が大きく変化するなど熱的安
定性に大きな問題があつた。<Prior Art> SiO 2 is widely used as an interlayer insulating film for multilayer wiring in integrated circuit elements, a surface protective film, and the like. Recently, these SiO 2 films have been increasingly produced by the sputtering method. However, SiO 2 films created by applying the conventional sputtering method do not undergo thermal oxidation.
The film density was lower than that of SiO 2 , and there were major problems with thermal stability, such as the internal stress of the film changing significantly during heat treatment after film formation.
SiO2膜が上述のように表面保護膜や、1〜2
層程度の比較的少ない積層構造からなる多層配線
用の層間絶縁膜として利用している限りでは、上
記のような従来のスパツタリング法によつて作成
した膜でも利用することができる。しかし集積度
の飛躍的な向上のもとに開発が進められている積
層高密度集積回路素子においては、上記従来方法
によつて作成したSiO2膜では問題がある。 As mentioned above, the SiO 2 film can be used as a surface protective film or as a
As long as the film is used as an interlayer insulating film for multilayer wiring having a laminated structure with relatively few layers, a film produced by the conventional sputtering method as described above can also be used. However, in the case of stacked high-density integrated circuit elements, which are being developed with dramatic improvements in the degree of integration, there are problems with the SiO 2 film produced by the above-mentioned conventional method.
即ち第1図は従来から提案されている積層高密
度集積回路素子の断面図で、実際には更に多層に
積層されるが、図が複雑になるのを避けるため集
積回路デバイス10,20を2層に積層した例を
示す。シリコン基板11に不純物拡散領域12,
12等を作成し、適宜配線13によつて電気的接
続を施こした第1層目のデバイス10上に、第2
デバイス20を積層するが、両デバイス10,2
0間にはデバイス間の電気的絶縁を図るために絶
縁膜30を介挿する。回路を作成した第1層目デ
バイス10上に絶縁膜30を被着した後、第2層
目デバイス20のためのポリシリコン膜21を形
成し、該ポリシリコン膜21内の一部の領域にレ
ーザー光を照射してレーザーアニールによつてポ
リシリコン膜を単結晶化する。単結晶化した領域
にP或いはN型の不純物を導入して回路素子を作
成し、第2層目デバイス20を作成する。同様に
第2層目デバイス20上にも絶縁膜を介して順次
集積回路デバイスを積層し、少なくとも5層以上
にデバイスを積層して非常に集積度の高い三次元
回路素子とする。 That is, FIG. 1 is a cross-sectional view of a laminated high-density integrated circuit device that has been proposed in the past.In reality, it is laminated in many more layers, but in order to avoid complicating the diagram, the integrated circuit devices 10 and 20 are separated by two. An example of stacked layers is shown. Impurity diffusion region 12 in silicon substrate 11,
12, etc., and the second
Although the devices 20 are stacked, both devices 10 and 2
An insulating film 30 is inserted between 0 and 0 in order to electrically insulate the devices. After depositing the insulating film 30 on the first layer device 10 on which the circuit has been created, a polysilicon film 21 for the second layer device 20 is formed, and some areas within the polysilicon film 21 are The polysilicon film is made into a single crystal by irradiation with laser light and laser annealing. A P or N type impurity is introduced into the single crystallized region to create a circuit element, and a second layer device 20 is created. Similarly, integrated circuit devices are sequentially stacked on the second layer device 20 via an insulating film, and the devices are stacked in at least five layers to form a three-dimensional circuit element with a very high degree of integration.
上記積層高密度集積回路素子において、デバイ
ス間に介挿する絶縁膜はSiO2膜や窒化シリコン
膜が用いられるが、デバイス間の電気的絶縁を確
実に行うものでなければならず、また順次デバイ
スを積層してゆく過程で熱工程や熱処理に晒され
ることがしばしばあり、このような作業環境に晒
しても変形したりデバイス表面から剥離してはな
らない。しかし上述のような従来方法によつて作
成したSiO2膜は膜密度が低く、そのために電気
的絶縁性が充分ではなく、また薄膜中の内部応力
が熱処理中に変化してそのためにシリコン基板が
変形する等の不都合があつた。このような不都合
は膜作成後高温で長時間の熱処理を施こせば幾分
改善される。しかし集積回路素子によつては高
温・長時間の熱処理を加えることができない場合
がしばしばあり、SiO2膜を絶縁層とし利用し得
ないという問題点があつた。 In the above-mentioned laminated high-density integrated circuit elements, SiO 2 film or silicon nitride film is used as the insulating film inserted between the devices, but it must ensure electrical insulation between the devices, and In the process of stacking layers, they are often exposed to thermal processes and heat treatments, and even when exposed to such working environments, they must not deform or peel off from the device surface. However, the SiO 2 film produced by the conventional method described above has a low film density and therefore does not have sufficient electrical insulation, and the internal stress in the thin film changes during heat treatment, causing the silicon substrate to deteriorate. There were some inconveniences such as deformation. These inconveniences can be somewhat alleviated by performing heat treatment at a high temperature for a long time after film formation. However, depending on the integrated circuit element, it is often impossible to apply heat treatment at high temperature and for a long time, and there is a problem that the SiO 2 film cannot be used as an insulating layer.
<発明の目的>
本発明は上記従来の製造方法によつて作成した
SiO2膜の問題点に鑑みてなされたもので、膜密
度の高い状態を維持しながら、たとえ熱処理を施
こしたとしても内部応力がほとんど変化しない熱
的に安定なSiO2膜をスパツタリング法で得るこ
とができる製造方法を提供することである。<Object of the Invention> The present invention is directed to the production of a product manufactured by the above conventional manufacturing method.
This was done in view of the problems with SiO 2 film, and it is possible to create a thermally stable SiO 2 film by sputtering, which maintains a high film density and whose internal stress hardly changes even after heat treatment. The object of the present invention is to provide a manufacturing method that can obtain the same.
<実施例>
マグネトロンスパツタリング装置の反応槽に設
けられた相対向する電極の一方に被スパツタ材料
をセツトし、他方の電極に、SiO2膜を被着すべ
き集積回路デバイス基板をセツトする。集積回路
デバイスをセツトした電極側は加熱手段を備え、
スパツタリング中の基板を所定温度に保持する。
各電極に材料をセツトした後反応槽内に所定の不
活性ガスを導入し、電極間に電源を供給する。ス
パツタリング装置の稼動によつて高周波電圧が電
極間に印加され、被スパツタ材料から飛び出した
SiO2膜作成のための分子或いは原子が基板表面
に堆積し、SiO2薄膜を作成する。スパツタリン
グによつて作成したSiO2膜は内部応力の安定化
を図るために熱処理する。<Example> A material to be sputtered is set on one of opposing electrodes provided in a reaction tank of a magnetron sputtering apparatus, and an integrated circuit device substrate to be coated with a SiO 2 film is set on the other electrode. . The electrode side on which the integrated circuit device is set is equipped with heating means,
The substrate during sputtering is maintained at a predetermined temperature.
After setting the materials on each electrode, a predetermined inert gas is introduced into the reaction tank, and power is supplied between the electrodes. When the sputtering equipment operates, a high frequency voltage is applied between the electrodes and the sputtering material is ejected from the sputtering material.
Molecules or atoms for creating a SiO 2 film are deposited on the substrate surface to create a SiO 2 thin film. The SiO 2 film created by sputtering is heat treated to stabilize internal stress.
第2図は上記マグネトロンスパツタリングによ
つて作成したSiO2膜の膜質と基板保持温度との
関係を示す図で、曲線Aはスパツタリング後熱処
理をしていないSiO2膜、曲線Bはスパツタリン
グ後800℃で1時間熱処理したSiO2膜についての
測定結果である。膜質の評価はエツチング速度
(×103Å/分)で行ない、エツチング液は緩衝フ
ツ酸である。同図の曲線A,Bから明らかなよう
に、基板加熱を行わないで室温でスパツタリング
したSiO2膜はエツチング速度が非常に大きく、
膜質を改善するべく800℃で1時間の熱処理を行
つても熱酸化で作成したSiO2膜が示すエツチン
グ速度(約1000Å/分)まで小さくはならない。
しかしスパツタリング中基板温度を350℃に保持
して作成したSiO2膜は、スパツタリング後熱処
理を行わなくてもエツチング速度が熱酸化SiO2
膜のエツチング速度とほぼ同程度である。これは
基板を加熱した状態でスパツタリングしたSiO2
膜は膜質が緻密になつていることを示す。また基
板温度を200℃に保つて作成したSiO2膜は800℃
で1時間の熱処理を行うとエツチング速度が熱酸
化SiO2膜のそれと同程度になる。即ち基板を加
熱保持した状態でスパツタリングすることより作
成したSiO2膜は、膜質が著しく緻密になつて電
気的には絶縁性がより高くなる。 Figure 2 is a diagram showing the relationship between the film quality of the SiO 2 film created by the above magnetron sputtering and the substrate holding temperature, where curve A is for the SiO 2 film without heat treatment after sputtering, and curve B is for the SiO 2 film after sputtering. These are measurement results for a SiO 2 film heat-treated at 800°C for 1 hour. Film quality was evaluated based on the etching rate (×10 3 Å/min), and the etching solution was buffered hydrofluoric acid. As is clear from curves A and B in the same figure, the SiO 2 film sputtered at room temperature without heating the substrate has a very high etching rate.
Even if heat treatment is performed at 800° C. for 1 hour to improve the film quality, the etching rate does not decrease to the level shown by the SiO 2 film created by thermal oxidation (approximately 1000 Å/min).
However, the etching rate of the SiO 2 film created by maintaining the substrate temperature at 350°C during sputtering was that of thermally oxidized SiO 2 even without heat treatment after sputtering.
The etching rate is approximately the same as the film etching rate. This is SiO 2 sputtered while the substrate is heated.
The film shows that the quality of the film is dense. In addition, the SiO 2 film created by keeping the substrate temperature at 200°C is 800°C.
When heat treatment is performed for 1 hour, the etching rate becomes comparable to that of a thermally oxidized SiO 2 film. That is, the SiO 2 film produced by sputtering while the substrate is heated and held has a significantly denser film quality and higher electrical insulation.
上記緻密な膜質をもつたSiO2膜は続いて行わ
れる熱処理で内部応力の安定化が図られる。 The internal stress of the dense SiO 2 film described above is stabilized by subsequent heat treatment.
第3図は各熱処理温度における経過時間と内部
応力との関係を示す図で、曲線aは600℃、曲線
bは800℃、曲線cは900℃に熱処理温度を選んで
いる。いずれの処理温度においても、熱処理初期
約10分間で大きく変化し、その後ほとんど変化し
なくなる。即ち内部応力の安定化が図られたこと
になる。 FIG. 3 is a diagram showing the relationship between elapsed time and internal stress at each heat treatment temperature, where the heat treatment temperatures were selected to be 600°C for curve a, 800°C for curve b, and 900°C for curve c. At any treatment temperature, there is a large change in the initial 10 minutes of heat treatment, and then there is almost no change. In other words, the internal stress has been stabilized.
上述の結果をもとにして、基板温度250℃で作
成したスパツタSiO2膜に800℃10分間の熱処理を
行つたところ、得られたSiO2膜はエツチング速
度が1000Å/分で、内部応力は2.6×109dyn/cm2
であつた。このSiO2膜を更に800℃で熱処理を続
けても、また800℃以下の温度で再度熱処理を行
つてもエツチング速度や内部応力の変化は見られ
ず、膜は緻密で且つ内部応力の安定した状態にあ
つた。 Based on the above results, a sputtered SiO 2 film prepared at a substrate temperature of 250°C was heat treated at 800°C for 10 minutes, and the resulting SiO 2 film had an etching rate of 1000 Å/min and an internal stress of 2.6× 109 dyn/ cm2
It was hot. Even if this SiO 2 film was further heat-treated at 800°C or again at a temperature below 800°C, no change in etching rate or internal stress was observed, and the film was dense and had stable internal stress. condition.
上記熱的に内部応力が安定した膜は、作業中の
熱処理によつて変形したり、基板に無理な力を及
ぼすことがないため、積層高密度集積回路素子の
デバイス間絶縁膜に適している。 The above-mentioned film with stable internal stress is suitable as an inter-device insulating film for laminated high-density integrated circuit elements because it does not deform due to heat treatment during work or exerts excessive force on the substrate. .
尚スパツタリングは、マグネトロンスパツタリ
ング法に限らず、RFスパツタリング法にも本発
明を適用することができる。 Note that the sputtering is not limited to the magnetron sputtering method, but the present invention can also be applied to the RF sputtering method.
<効果>
本発明の如く、200℃以上の基板加熱を行つて
形成したスパツタリング膜に比較的短時間の熱処
理を施すことにより、膜密度が高い状態を維持し
ながら熱的に安定した酸化シリコン膜を得ること
ができるため、積層高密度集積回路素子におい
て、既に下層に形成した素子に悪影響を及ぼすこ
となく層間絶縁膜を形成することが可能となり、
延いては信頼性の高い積層高密度集積回路素子を
提供することが可能になる。<Effects> As in the present invention, by applying a relatively short heat treatment to a sputtering film formed by heating the substrate to 200°C or higher, a thermally stable silicon oxide film can be created while maintaining a high film density. As a result, it is possible to form an interlayer insulating film in a laminated high-density integrated circuit element without adversely affecting the elements already formed in the lower layer.
As a result, it becomes possible to provide highly reliable laminated high-density integrated circuit elements.
第1図は積層高密度集積素子の概略断面図、第
2図は本発明を説明するためのエツチング速度と
スパツタリング時の基板温度との関係を示す図、
第3図は本発明を説明するための膜の内部応力と
熱処理時間との関係を示す図である。
FIG. 1 is a schematic cross-sectional view of a laminated high-density integrated device, and FIG. 2 is a diagram showing the relationship between etching rate and substrate temperature during sputtering to explain the present invention.
FIG. 3 is a diagram showing the relationship between internal stress of a film and heat treatment time for explaining the present invention.
Claims (1)
路素子のデバイス間に層間絶縁膜として酸化シリ
コン膜を製造する方法であつて、 基板保持温度を200℃以上に設定し、基板上に
スパツタリング法にて酸化シリコン膜を堆積する
工程と、 前記酸化シリコン膜に600〜900℃の温度で20分
以内の熱処理を行う工程と、 からなり、 以後の熱処理に対して内部応力がほとんど変化
しない安定な薄膜を作成することを特徴とする酸
化シリコン膜の製造方法。[Claims] 1. A method for manufacturing a silicon oxide film as an interlayer insulating film between devices of integrated circuit elements stacked on a substrate in multiple layers, the method comprising: setting the substrate holding temperature at 200°C or higher; , a step of depositing a silicon oxide film on a substrate by a sputtering method, and a step of heat-treating the silicon oxide film at a temperature of 600 to 900°C for within 20 minutes, to reduce internal stress for subsequent heat treatment. A method for producing a silicon oxide film, which is characterized by creating a stable thin film with little change in .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223053A JPS59114828A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57223053A JPS59114828A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59114828A JPS59114828A (en) | 1984-07-03 |
JPH0223030B2 true JPH0223030B2 (en) | 1990-05-22 |
Family
ID=16792093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57223053A Granted JPS59114828A (en) | 1982-12-21 | 1982-12-21 | Formation of silicon oxide film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59114828A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0763062B2 (en) * | 1985-04-12 | 1995-07-05 | 日本インタ−株式会社 | Method for manufacturing semiconductor device |
-
1982
- 1982-12-21 JP JP57223053A patent/JPS59114828A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59114828A (en) | 1984-07-03 |
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