JPH02224018A - Sorting circuit - Google Patents

Abstract

PURPOSE:To sort plural data fast by controlling the data writing and reading of a first buffer memory, a last buffer memory, and a chain buffer memory. CONSTITUTION:This circuit is a circuit which sorts and outputs reference axis data outputted from a data generating circuit 8 and is provided with a reference axis data memory 10, a data number pointer 12, the first buffer memory 20, a last buffer memory 30, a chain buffer memory 40, and sorting control circuits 80(80a - 80c) which controls the writing and reading of data to and from those memories. Then the two-time transfer operation consisting of the data transfer of the first buffer memory 20, the last buffer memory 30 and the chain buffer memory 40 of the inputted reference axis data, and data transfer from the first buffer memory 20 and last buffer memory 30 to the chain buffer memory 40 is carried out to sort the reference axis data. Consequently, the number of times of data transfer decreases and the sorting is performed fast.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sorting circuit, and particularly to a circuit for sorting a plurality of reference axis data.

[Background technology] The image synthesis circuit synthesizes and outputs various image signals for CRT display based on externally supplied image information.
Since dimensional images can also be synthesized and output, for example, video games for 3-dimensional images, flight control simulators for airplanes and various vehicles, Combicota graphics, C
It is widely used for AD device displays and other applications.

However, when synthesizing a three-dimensional image with depth using an image synthesis circuit in real time, the three-dimensional data of the famous object is processed for each famous frame based on the coordinate value in the image depth direction, that is, the Z-axis data. It is necessary to sort at high speed.

For this reason, it has been desired to develop a circuit that can quickly sort a plurality of three-dimensional data based on predetermined reference axis data, that is, Z-field data.

However, conventionally, such sorting has been performed on all data by successively comparing adjacent Z-axis data included in each data and rearranging them each time.

For this purpose, data transfer of all Z-axis data between memories must be repeated many times.

Therefore, there was a problem that data sorting work could not be performed at high speed.

Particularly, in this conventional technique, when the number of Z-axis data items to be compared increases, the sorting operation becomes time-consuming and labor-intensive. Therefore, in order to perform high-speed sorting, a relatively large computer must be used, resulting in a problem that the entire apparatus becomes complicated and expensive.

[Problems to be Solved by the Invention] An object of the present invention is to be able to sort multiple pieces of data at high speed with a simple configuration, and in particular to perform sorting even when there is a large number of reference axis data to be sorted. The object of the present invention is to provide a sorting circuit that can perform high-speed sorting.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a circuit for sorting a plurality of input reference axis data, the circuit sorting each input reference axis data↓corresponding data number. and a first data number storage area in which an address is specified based on the reference axis data, and when the reference axis data corresponding to each storage area T is input for the first time, the first data number is stored in this storage area. It has a first buffer memory that stores the data number generated by the data number generation means, and a last data number storage area whose address is specified based on the reference axis data, and the reference axis data corresponding to each storage area is input. a last buffer memory that updates and stores in this storage area the data number generated by the data number generation means for each data number; a chain buffer memory having a chain data number storage area in which an address is designated based on the data number; and the last buffer memory. a first control means for writing a new data number to be updated into a chain data number storage area designated by the data number before update, each time the data number is updated; After writing the data number into the buffer memory, the first data in a predetermined correspondence with the last data number storage area and the first rear are stored in the chain data number storage area specified by the data number stored in the last data number storage area. Number memory and rearrangement: 'A second control means for writing the data number so that the reference axis data is chained in ascending order or descending order in the chain data number storage area by writing the stored data number; A third control means reads out the data number written in the chain data number storage area according to 12 predetermined reading rules, and sorts and outputs each input reference axis data in the order of the read data number. shall be.

The present invention also provides a circuit for sorting a plurality of input data based on predetermined reference axis data, comprising: an information memory that stores a necessary portion of each of the data in correspondence with its data number; a sorting means into which reference axis data included in the data is input; the sorting means includes: a data number generation means which generates a data number corresponding to each input reference axis data; and a data number generation means based on the reference axis data. Ato! A data number storage area is provided, and when the reference axis data corresponding to each storage area is input for the first time, the data number generated by the data number generation means is stored in this storage area. It has a papa memory and a last data number storage area whose address is specified based on the reference axis data, and a data number is generated in this storage area every time the reference axis data corresponding to each storage lower-rear is input. A last buffer memory that updates and stores the data number generated by the means, a chain buffer memory that stores a chain data number storage area whose address is specified based on the data number, and a data number of the last buffer memory that is updated. a first control means for writing a new data number to be updated into a chain data number storage area r designated by the data number before update, and writing the data number to the first buffer memory and the last buffer memory. After completion, the chain data number storage area specified by the data number stored in the last data number storage area,
By writing the data number stored in the first data number storage area that has a predetermined correspondence with the last data number storage area, the reference axis data is chained in ascending or descending order in the chain data number storage area. a second control means for reading data numbers written in the chain data number storage area according to a predetermined reading rule, and reading data from the information memory in the order of the read data numbers. means, and is characterized in that it sorts and outputs a plurality of data based on reference axis data.

As described above, according to the present invention, the reference axis data to be sorted is input into the first buffer memory and the last buffer memory in the order of their data numbers.

Then, the first buffer memory stores, in the first data number storage area, the data number when the corresponding reference axis data is first input.

Similarly, the last buffer memory sequentially updates and stores the data number in its last data number storage area each time the corresponding reference axis data is read. Therefore,
Each last data number stores the data number when the corresponding reference axis data was last read.

Further, when the data number stored in the last data number storage area is updated and stored, the data number stored in the storage area and the newly stored data number are inputted to the chain buffer memory.

So, every time the data in the last data number storage area is updated, the chain buffer memory stores the data in the chain data number storage area specified by the data number before update.
Write the new updated data number. Therefore, if reference axis data with the same value but different data numbers is input repeatedly (~), the history of that reference axis data, that is, the order of the data numbers in which the reference axis data was input is displayed. It will be written to the chain data number storage area.

After writing data to a series of first buffer memory, last buffer memory, and chain buffer memory, the last data number and the last data number are stored in the chain data number storage area specified by the data number stored in the last data number storage area. The data numbers stored in the first data number storage areas having a predetermined correspondence with the storage areas are sequentially written. In this way, data numbers are written in each storage area of the chain data number storage area so that the reference axis data is chained in ascending or descending order.

In the sorting circuit of the present invention, the data numbers written in the chain data number storage area are read out according to a predetermined reading rule.

Then, the input reference axis data is read out and controlled so as to be output in the order of the data numbers read out in step 7.

By doing so, the input reference axis data is sorted and output in ascending order or descending order.

Further, in the sorting circuit according to claim (4), the reading 17 is controlled so that data is outputted from the information memory in the order of the data numbers read out in this manner. By doing so, a plurality of pieces of data are sorted and output from the information memory in ascending order or descending order based on the reference axis data.

As described above, according to the present invention, data transfer of input reference axis data to the first buffer memory, last buffer memory, and chain buffer memory, and data transfer of input reference axis data to the first buffer memory and last buffer memory, are generally performed. The reference axis data can be sorted by performing two transfer operations, ie, data transfer from the memory to the chain buffer memory. Therefore, compared to the conventional sorting technology that compares adjacent reference axis data and sequentially rearranges the reference axis data itself, the number of data transfers is greatly reduced and sorting can be performed at high speed. be able to.

Further, according to the present invention, in order to sort the reference axis data indirectly by using the data number of the reference axis data, instead of sorting using the base ffP axis data itself, the number of digits of the reference axis Even when there is a large amount of data, sorting can be performed easily and quickly.

C Example] Next, preferred embodiments of the present invention will be described based on the drawings.

First Embodiment FIG. 1 shows a preferred embodiment of the sorting circuit according to the present invention. The circuit of the embodiment is for sorting and outputting the reference axis data output from the data generation circuit 8, and includes a reference axis data memory 10, a data number pointer 12, a first buffer memory 20, and a last buffer memory 30. and chain buffer memory 40
and a sorting control circuit 80 that controls writing and reading of data to and from each of these memories.

(a) Writing to reference axis data mesowa 10/Mill
The reference axis data memory 10 has a data number VOI/RI1.
It has a total of N reference axis data storage areas 1-4 from 1 to N specified by 2. Here, if the reference axis data is composed of M-bit data,
Each reference axis data storage area 4 may be formed to have a storage capacity of M bits.

When a plurality of reference axis data to be sorted are input from the outside, data numbers 1 to N are assigned to the reference axis data in the order of input, and addresses 1 to N are assigned by the data number pointer 12. are sequentially written into the reference axis data storage area '14.

In this way, when the writing of the reference axis data to be sorted into the reference axis data memory]O is completed,
Next, the reference axis data is 1 from this reference M daemono seven 10.
The data numbers are sequentially read out in the order of data numbers from .

In the embodiment, reading 17 of the negative reference axis data is performed by using the data number pointer 12 or [reading address and 17 =
This is done by sequentially outputting the numbers 1 to .N. [Then, when Atonos is specified by the data number, the specified sub-axis data is transferred from 4 to 1 to the first buffer memory 20 and the last buffer memory 30 i. The reference axis data is read out and becomes 0. Otsu.

(b) Addition to Butts Memories 20 and 30,
The first buffer memory 20 and the last buffer memory 30 each include a first data number memory 24 that corresponds one-to-one to all possible values of the reference axis data.
, and has a data number storage area 34.

As in the example, when the reference axis data consists of M bits, the total of ζt, 0, 2...(2'-1) is 2.
It can take M values.

Therefore, the first buffer memory 20 contains at least 0. 2... 2M first data number storage area 24 specified by the first address of (2'A-1)
is provided. Similarly, the last buffer memory 30 is provided with at least 2M last data number storage areas 34 designated by addresses from 0° to 2 . . . (2'-1).

Further, data numbers of reference axis data output from the reference axis data memory 10 are written in the first data number storage area 24 and the last data number storage area 34. In this example, the data number is 1~・N
3, and the maximum value is N3. Therefore, each data number storage area 24.34 is represented by (I
It may be formed to have a capacity of o g 2 N l bits (where 7, () is a symbol meaning an integer that is rounded off after the decimal point).

When the reference axis data is input from the reference axis data memory 10 to the first buffer memory 20 and the last buffer memory 30, these first buffer memory 20 and last buffer memory 30 are designated by the corresponding address pointers 22 and 32. The data number of the reference axis data is written to the data number storage area 24.34.

In this embodiment, such data writing is performed using the first control circuit 80a of the sorting control circuit 80 as follows.

That is, when the reference axis data of the data number specified by the data number pointer 12 is output from the reference axis data memory 10, the reference axis data is set in the address pointers 22 and 32, and these address pointers 2
From 2.32 onwards, the set reference axis data is output as a write address. Then, in each data number storage area 24.34 specified by this write address,
The data number specified by the data number pointer 12 (data number corresponding to the reference axis data) will be written.

Here, once a data number is stored in the first data number storage area 24, even if new reference axis data of the same value is sequentially output from the reference axis data memory 10, the new data number will not be overwritten. It is formed like this. On the other hand, last data number storage area 3
4 indicates - Month, even if the data number is stored, the next time reference axis data of the same value is output from the reference axis data memory 10, the data number of that reference axis data will be newly updated and stored. is formed.

In this way, the first data number storage area 24 stores the data number when the value of this reference axis data appears for the first time (7).On the other hand, the last data number storage area 34 stores the data number for each yl (The data number when the Junsuke data value last appeared will be stored.

Therefore, at the same address of the first data number storage area 24 and the last data number storage area 34,
The reference axis data of the same value is 1 from the reference axis data memory 10.
If only - times are output, the same data number will be written, but if the same value is output to the reference axis data multiple times, an increasing data number will be stored in the end. become.

Therefore, if the value in the last data number storage area '34 of the last buffer memory 30 has been updated and stored multiple times, it is possible to sort the reference axis data in ascending or descending order if you know how this update was performed. The sequence of data numbers of each reference axis data at the time is known.

For this reason, a chain data number storage area 44 is provided in the chain buffer memory 40 in which addresses are specified in the order of O to N based on the data number output by the address pointer 42. Like the first data number storage area 24 and the last data number storage area 34, each of these chain data number storage areas 44 may be formed to have a storage capacity of at least (log+Nl bits).

Then, when the contents of the last data number storage area 34 are updated and recorded, the data number before the update is set in the address pointer 42, and the data number is stored in the chain data number storage area 44.
Addressing is performed.

Then, the specified chain data number storage area 4
A new updated data number is written in 4.

When the last data number storage area 34 is updated and stored in this manner, the update history is sequentially written into the in-buffer memory 40.

As explained above, according to this embodiment, when the reference axis data is output from the reference axis data memory 10 in the order of data numbers, the output reference axis data is used as the write address, and the data number is ]-]5-rod buffer memory 20. The data is written to the last buffer memory 3, and in conjunction with this, the data is transferred and written from the first and second buffer memories 30 to the chain baranoor memory 40.

When such data transfer writing is completed, next the first buffer memory 20 and the last buffer memory 3
Data transfer from 0 to chain buffer memory 40 is started.

(C) Transfer writing of data to buffer memory 40 When such data transfer is started, the second control circuit 80b of the sorting control circuit 80 performs the following transfer control.

First, the data number stored in the last data number storage area 34 is set in the address pointer 42. Next, the data number of the first data number storage area 24 having a predetermined correspondence with the designated address is written into the chain data number storage area 44 addressed by this address pointer 42.

Although there are some differences in writing such data numbers when sorting data in ascending order and when sorting data in descending order, the case where data is sorted in ascending order will be explained here as an example.

For example, when a data number is stored in the last data number storage area 34 designated by address O, the data number stored at address 0 is first set to the address pointer 42.

Then, the data number is read from the first data number storage area 24 specified by address 1, and this data number is written to the chain data number storage area 44 specified by address pointer 42.

At this time, if the data number is not stored in the first data number storage area 24 specified by address 1, the data number is read from the storage area 24 specified by address 2, and the data number is read out from the first data number storage area 24 specified by address 2.
Write in 4. Additionally, if the data number is not stored in the first data number storage area 24 specified by address 2, address k is incremented in the same manner as address 3, address 4, etc. until the data is found. .

Then, when the data number is read from the storage area 24 specified by the address, this data number is written into the chain data number storage area 44 specified by the address pointer 42.

When such reading/writing is completed, next, the data number is read from the last data number storage area 34 specified by the address, and is written to the chain data number storage area 44 using it as the write address in the same manner as the previous time. data is written.

The apparatus of the embodiment repeatedly writes data to the chain data number storage area 44 in this manner.

When such a series of write operations is completed, data numbers are stored in the chain data number storage area 44 of the chain buffer memory 40 so that the reference axis data are chained in ascending order.

Then, the third control circuit 8 of the sorting control circuit 80
0c reads out the data number written in the chain data number storage area 44 according to the predetermined readout rule 17. Then, in the order of the data numbers read out in this way,
Reading control is performed so that reference axis data is output from the reference axis data memory 10.

By doing this, the reference axis data is sorted and output from the reference axis data memory 10 in ascending order.

Specific Sorting Operation Next, a case will be explained using such a sorting circuit, taking as an example a case where seven pieces of reference axis data outputted from the data generation circuit 8 are sorted in ascending order and a case where they are sorted in descending order.

(1) When sorting in ascending order FIG. 2 shows an example of such a sorting circuit.

In this embodiment, since seven pieces of reference axis data are to be sorted, the reference axis data memory 10 stores items 1 to .
The reference axis data storage area 14 may be formed to have a total of seven reference axis data storage areas 14 designated by data numbers 7.

Further, it is assumed that the reference axis data is composed of 2-bit data so as to take any value from 0 to 3. In this way, the first buffer memory 20 and the last buffer memory 30 each have four data number storage areas 2 whose addresses are the reference axis data O to 3.
4.34.

(a) Writing/reading to the reference axis data memory 10 First, the reference axis data is transferred from the external data generation circuit 8 to the reference axis data memory 10 as follows: 2→1 →3・→3→0→2 → If input in the order of 3, the input reference axis data will be sequentially input. The data will be written to the storage area 14 whose address is the data number 2, 3, . . . .

One of the features of the present invention is that data memory]
When reference axis data is written in 0, the reference axis data is sorted using the data number rather than the reference axis data itself.

By doing this, even when the number of digits of the reference axis data to be sorted is large, it is possible to sort the reference axis data at high speed with a simple circuit.

In this embodiment, the reference axis data memory 1
When the reference axis data is written in 0, the reference axis data is sequentially read out from the reference axis data memory 10 in the order of the data number.

(1)) Writing to I'ff1 memory 20.30 When the reference axis data is read in this way, the corresponding data number is written to the first data number storage area using the read reference axis data as an address. 24 and last data number storage area 34 in sequence.

Therefore, from the data memory 10, data number "1" is first entered.
When the reference axis data "2" specified by is output, the data number "1" is written in each data number storage area 24.34 using this reference axis data "2" as an address.

Similarly, when the reference axis data "1" specified by the data number "2" is output from the reference axis data memory 10, the reference axis data "1" is used as an address, and the data numbers 24 and 34 are The data number "2" is written.

Next, when the reference axis data "3" specified by the data number "3" is similarly output from the reference axis data memory 10, this reference axis data "3" is used as an address and the data number storage area 24. 34 has its data number "3"
is written.

Next, the reference axis data “3” specified by the data number “4” is
” is output, data number “4” is input to the data number storage area 24.34 using this reference axis data “3” as an address.

At this time, in the first data number storage area 24,
Since the data number has already been written, no new data number is written. On the other hand, the last data number storage area 34 updates and stores the previous data number "3" to a new data number "4". Therefore, the data number “3” before update is stored in the data number storage area 44.
The updated data number "4" will be written using the address as the address.

Next, the reference axis data specified by the data number "5" from the reference axis data memory 10 [when 0, 1 is read, this reference axis data [0] is used as the address] 7, and each data number storage area is The data number "5" is written in 24.34.

Next, from the reference axis data memory 10, data number "6"
When the reference axis data "2" specified by is output, the data number "6" is input to the data number storage area 24.34 using this reference axis data "2" as an address. At this time, the data number “1” is already stored in the first data number storage area 24 specified by address r2J.
” is written. Therefore, the newly input data number "6" is not written. On the other hand, the last data number storage area 3 specified by address "2"
The contents of 4 are updated and stored in the newly input data number ``6''.

In this way, when the contents of the last data number storage area 34 are updated from "1" to "6", the updated data number is stored in the chain data number storage area 44 using the data number "1" before the update as an address. A new data number "6" is written.

Next, data number “7” is retrieved from the reference axis data memory 10.
When the last reference axis data "3" specified by is read out, data number "7" is input to data number 24.34 using this reference axis data "3" as an address. At this time, since the data number "3" has already been written in the first data number storage area 24, a newly input data number will not be written. In contrast,
The contents of the last data number storage area 34 are updated to the newly input data number "7".

In this way, when the contents of the last data number storage area 34 are updated to r4J = r7J, the new data after the update is stored in the chain data number storage area 44 using the data number "4" before the update as the address. The number "7" is stored.

Through this series of writing operations, the first data number storage area 24 whose address is the reference axis data has the following information:
The data number when each reference axis data first appears will be written.

Furthermore, the last data number storage area 34 whose address is the reference axis data stores the data number when the value of each reference axis data appears last.

Furthermore, in the chain data number storage area 44 whose address is the data number, the last data number storage area 3
Every time the data No. 4 is updated and stored, the updated data numbers are sequentially written using the pre-updated data numbers as addresses. Therefore, when the same reference axis data is output from the reference axis data memory 14 multiple times, this storage area 44 stores a history of the data number order in which the reference axis data was output. become.

(C) Transferring and writing data to buffer memory 940 When this series of write operations is completed, data is transferred from first buffer memory 20 and last buffer memory 30 to chain buffer memory 40 as shown in FIG.
Data transfer to starts.

When such data transfer is started, first, data number storage areas 24 in which data is stored are searched in order from the smallest address. Then, the data number stored in the storage area 24 is set to STAR!・Read the address and (2), chain data number storage area 4
Write to address 0 of 4.

If address 0 of the storage area 44 is to be used for other purposes, the start address may be set, for example, in the start address pointer 310, as shown by the dotted line in FIG. .

In this embodiment, when searching the data number storage area 24 in which data is stored in order from the smallest address, it is detected that a data number is written in the storage area 24 at address O. Then, this data number r5J is written into the chain data number storage area 44 designated by address 0 as shown in FIG.

Note that if the storage area 44 with address "0" is to be used for other purposes, it should be set in the start address pointer 310.

Next, the data number when the reference axis data "0" last appeared is the address, and the data number when the reference axis data larger than this [7] first appeared is the chain data number storage area 44. write to.

In order to do this, data number "5" in the last data number storage area 34 specified by address "0" must be selected.
Read as the write address.

Then, the data in the first data number storage area 24 designated by the address "1" may be written into the chain data number storage area 44 designated by the address "5".

Next, in the same way, the data number when the reference axis data "1" appears last is set as the write address.

The data number when the reference axis data “2” above this first appears is stored in the chain data number storage area 44.
write to.

To perform such writing, data number "2" in the last data number storage area 34 specified by address "1," is read out as a write address. and,
The data "1" in the first data number storage area 24 designated by the address "2" may be written into the chain data number storage area 44 designated by the address "2".

Similarly, the data number "6" when the reference axis data "2" appears last is written as the write address 17, and the data number "3" when the reference axis data "3" first appears as the chain data number. Write to storage area 44.

When such a series of data transfer operations is completed, data numbers are written in the chain data number storage area 44 so that the reference axis data are chained in ascending order.

(d) Sorting output of I single-axis data When the transfer and writing of such data is completed, the data number is sequentially read from the chain buffer memory 40 according to a predetermined read rule as the read address for the reference axis data memory]0. Output.

In this embodiment, the read start address is stored in the chain data number storage area 44 designated by address 0. For this reason, address "0" is first set in the address pointer 42. As a result, the data number "5" stored in the address "0" of the data number storage area 44 is read out as the read start address.

In this way, the data number is stored in the data number storage area 4.
4, the read delta number is then set in address pointer 42.

Therefore, the next data number "2" is read out from the data number storage area 44 designated by address "5", and the read data number is newly set in the pointer 42 at address "5".

When the data numbers are sequentially read out according to such read rules, the data numbers are sequentially output from the chain data number storage area 44 in the following order: 5→2 1→6→3→4 7.

Therefore, if the data number read in this way is used as the data read address for the reference axis data memory 0, the following data will be read from the reference axis data memory 10: 0-→1→2→2→3→3→3 Then, the reference axis data is sorted and output in ascending order.

(IN) Case of sorting in descending order Next, the case of sorting the reference axis data in descending order using the sorting circuit of the present invention is as shown in FIG. S2. This will be explained using an example of a case where

(a) ill data memo H (writing h/!II!
L This operation is the same as the case of sorting the reference axis data in ascending order, so its explanation will be omitted.

(b) Writing to Pufffu T Memo '120.30 This operation is similar to the case of sorting data in ascending order, so its explanation will be omitted here.

(e) Transferring and writing data to the buffer 1 memory 40 The process of transferring and writing data to the buffer 1 memory 40 differs slightly depending on whether the reference axis data is sorted in ascending order or in descending order. Become light.

FIG. 20 shows an example of data transfer from the first buffer memory 2° and the last buffer memory 3o to the chain buffer memory 40 when data is sorted in descending order.

When sorting is performed in descending order, at the start of data transfer, data number storage areas 24 in which data is stored are first searched for in descending order of address. Then, the data number stored in the storage area 24 is read out as a start address (7) and written to address 0 of the chain data number storage area 44.

If address 0 of the storage area 44 is to be used for other purposes, the start address may be set, for example, in the start address pointer 310, as shown by the dotted line in FIG.

In this embodiment, when searching the data number storage area 24 in which data is stored in order from the address (reference axis data) with the largest one, the data number is written in the memory J and rear 24 at address "3". is detected. This data number "3" is then written into the chain data number storage area 44 designated by address "0" as shown in FIG.

Note that when the storage area 44 at address rOJ is used for other purposes, it is set in the start address pointer 310.

Next, using the data number when the reference axis data "3" last appears as an address, write the data number when the smaller reference axis data "2" first appears to the chain data number storage area 44. It's crowded.

In order to do this, data number "7" in the last data number storage area 34 specified by address "3" must be selected.
is read as the write address. Then, the data "1" in the first data number ki tα1 area 24 designated by the address "2" may be written into the chain data number storage area 44 designated by the address r7J.

Next, in the same way, write the data number when the reference axis data "2" last appeared and take the address.

The data number when the reference axis data “1” below this first appears is stored in the chain data number storage area 44.
write to.

To perform such writing, data number "6" in the last data number storage area 34 specified by address "2" is read out as a write address. Then, data "2" in the first data number storage area 24 designated by the address "1" may be written into the chain data number storage area 44 designated by the address "6".

Similarly, at 17, write the data number ``2'' when the reference axis data ``shi'' appears last and set it as the address [1, and the data number ``5'' when the reference axis data ``0'' first appears.
” is written in the chain data number storage area 44.

When this series of data transfer operations is completed, data numbers are written in the chain data number storage area 44 so that the reference axis data are chained in descending order.

(d) Sorting output of reference axis data When the transfer and writing of such data is completed, the data number is then read from the chain buffer memory 40 as a read address for the reference axis data [10] according to a predetermined readout rule. Output sequentially.

In this embodiment, the read start address is stored in the chain data number storage area 44 designated by address "0". For this reason, first, atl female "0"
is set in the address pointer 421. As a result, the data number "3" stored in the address "0" of the data number storage area 44 is read out as the read start address.

When the data number is read from the data number 2tfl area 44 in this manner, the read data number is then set in the address pointer 42.

Therefore, the next data number ".1" is read out from the data number storage area 44 specified by the address "3", and the read data number is newly added to the no pointer 42.
is set to

When the data numbers are sequentially read out according to such read rules, the data numbers will be sequentially output from the chain data number storage area 44 in the order of 3 → 4 → 7 → 1-+6 to 4-2 → 5. .

Therefore, if the data read out in this way is used as the data 3 address for the reference axis data memory 10, then from the reference axis data 10, 3→3→3→2→ The reference axis data is sequentially sorted and output in descending order in the order of 2→1→0.

(m) Summary of sorting operations in ascending order and descending order As described above, according to the present invention, whether the reference axis data is sorted in ascending order or in descending order, the reference axis data itself is not used. By using the data number assigned corresponding to the reference axis data, even if the number of bits of the reference axis data is large, the sorting work can be done quickly and easily without being affected by this. It becomes possible.

In particular, according to the present invention, the sorting of reference axis data is performed by repeating the conventional work of rearranging one reference axis data while comparing it with all the remaining reference axis data for each reference axis data. The number of data transfers required is significantly smaller than that of the conventional method, and the amount of data to be transferred is also significantly smaller, making it possible to transfer reference axis data with a simple circuit and at extremely high speed. .

In addition, in the above embodiment, the case where all four reference axis data from 0 to 3 exist was explained as an example, but the present invention is not limited to this, and the present invention is not limited to this. Even if "1" does not exist, the sorting operation can be performed in the same way.

In this case, as shown in FIG. 4, even if the data transfer from the reference axis data memory 10 to the first buffer memory 20 and the last buffer memory 30 is completed, the address "1" of each of these buffer memories 20 and 30 is No data number is written in the data number storage area 24.34 designated by .

Therefore, when sorting data in ascending order, for example, when transferring data from each buffer memory 20.30 to the chain buffer memory 40, the data number "0" when the reference axis data "0" was last output is used.
5'' as the at I node, then any more reference axis data, that is, the data number 1 when the reference axis data 2 first appears, may be written into the chain data number storage area 44. Note that the subsequent data writing is performed in the same manner as in the embodiment shown in FIG. 3 above.

(The following is a blank space) Second Embodiment FIG. 21 shows a second preferred embodiment of the present invention.

In the first embodiment, the case where the data number pointer 12 of the reference axis data memory 10 functions as data number generation means has been described as an example. The present embodiment is characterized in that a data number generation counter 3 is used instead, and this counter 13 is made to function as data number generation means.

That is, when reference axis data to be sorted is sequentially output from the external data generation circuit 8, this reference axis data is sequentially written and stored in the reference axis data memory 10 in the same manner as in the first embodiment. In addition, a data number counter 13, a first buffer memory 20. It is input to the last buffer memory 30.

At this time, the data number counters 1 and 3 generate a corresponding data number each time the reference axis data is input. In the embodiment, the output is synchronized with the input of the reference axis data.
...Outputs data numbers in the order of (2M-1,).

Then, the first buffer memory 20. In each storage area 24, 34 of the last buffer memory 30, the reference axis data output from the data generation circuit 8 is used as a write address, and the data number output from the data number counter 13 is written in the same manner as in the first embodiment. written. At this time, data is also written to the chain buffer memory 40 in the same manner as in the first embodiment.

At the time when such data transfer and writing to each buffer memory 20, 30, and 40 is completed, writing of the reference axis data to the reference axis data memory 10 is also completed. After such data transfer and writing is completed, data is transferred from the first buffer memory 20 and the last buffer memory 30 to the chain buffer memory 40 in the same manner as in the first embodiment.

Then, when the data transfer and writing to the chain buffer memory 40 is completed, this chain buffer memory 40
Data numbers are stored so that the reference axis data are chained in ascending or descending order.

Therefore, the third control circuit 80c reads out the data number written in the chain data number storage area 44 according to a predetermined reading rule. Then, reading is controlled so that the reference axis data is output from the reference axis data memory 10 in the order of the read data numbers. Thereby, the reference axis data is sorted and outputted from the reference axis data memory 10 in ascending order or descending order.

In this way, according to this embodiment, the reference axis data memory 1
Since the writing of reference axis data to 0 and the sorting of this reference axis data can be performed simultaneously and in parallel, the sorting of the reference axis data can be performed faster than in the first embodiment.

As a result, the reference axis data can be sorted and output in ascending order or descending order, similarly to the first embodiment.

Third Embodiment In the first and second embodiments, the case where the input reference axis data is sorted is explained as an example, but the present invention is not limited to this, and the reference axis data and their combination information ( Similar sorting can be performed on sorting data consisting of information that is paired with reference axis data.

FIG. 19 shows a preferred embodiment in which sorting data including such combination information is sorted based on its reference axis data. Although the circuit of this example can be formed using any of the circuits of the first example V and the second example, here, the circuit of the first example is formed using the circuit of the first example. This will be explained using a case as an example.

The sorting circuit of the embodiment uses the reference axis data memory〕0
and an information memory 58. And :': +7)
The circuit stores the reference axis data included in the sorting data output from the data generation circuit 8 as reference axis) 1 - memory 1.
0 is stored [2, each reference axis data and +4t one combination information is stored in the information memory 58.

Here, the reference axis data memory 10 has a total of N reference axis data storage areas 14 from at least 1 to N designated by the data number pointer 12.

Further, the information memory 58 also stores the data number pointer 12.
A total of N combination information storage areas 58a, specified by at least 1=N, are ζf.

When a plurality of reference axis data to be sorted are input from the external data generation circuit 8, data numbers 1-H are assigned to the reference axis data in the order of input. The reference axis data and its stitching information included in the sorting data are stored at data number pointer 1.
Reference axis data storage areas 1 to N specified by 2 are sequentially written to the t-parallel and combination information storage area 58a.

In this way, sorting data is input from the outside at the sorting time of this embodiment, and 41
1, 'The reference axis data and their combination information included in the sorting data are sequentially written in each storage area 14.58a designated by the data number pointer 12 in a predetermined correspondence relationship.

Therefore, if the reference axis data stored in the reference axis data memory 10 is sorted in the same manner as in the first embodiment, this reference axis data will be stored in the chain data storage area 44 of the chain buffer memory 40. Data numbers are stored in a chain in ascending or descending order.

Therefore, the chain data number storage area 44
The data numbers stored in the information memory 58 are read out in the same manner as in the first embodiment, and are stored in the information memory 58 in the order of the read data numbers.
When the combination information is read from the information memory 58, a series of combination information is sorted and output in ascending order or descending order based on the reference axis data.

As explained above, according to this embodiment, even when the amount of information of the sorting data itself is large, the sorting process using the reference axis data memory 10 and each buffer memory 20.degree. 30.40 can be completed in a short time. Therefore, even when the amount of information per unit of sorting data is large, this sorting process can be performed efficiently in a short time.

Fourth Embodiment FIG. 22 shows a fourth preferred embodiment of the present invention. In the third embodiment, explanation I7 is given by taking as an example a case in which a circuit for sorting sorting data including combination information based on reference axis data is formed using the circuit of the first embodiment. This embodiment is characterized in that such a sorting circuit is formed using the circuit of the second embodiment. Incidentally, members corresponding to those in each of the above-mentioned embodiments are given the same symbols and their explanations will be omitted.

The sorting circuit of this embodiment is composed of an information memory 58 and the circuit shown in the second embodiment. In addition,
A reference axis data memory 10 is not provided.

Then, the reference axis data included in the sorting data output from the external data generation circuit 8 is transferred to the data number counter 13. Input to each buffer memory 20°30,
The combination information paired with each reference axis data is sequentially stored in the information memory 58 in the same manner as in the third embodiment.Of course, the combination information sequentially stored in the information memory 58 includes: Reference axis data may also be included.

Then, when the reference axis data is input, each buffer memory 20, 30, 40 . Data number click! -13 and the sorting control circuit 80 operate in the same manner as in the second embodiment. Therefore, data numbers are stored in the chain data storage area 4/; of the chain buffer memory 40 so that the reference axis data are chained in ascending or descending order.

Then, the third control circuit 80e transfers the data number stored in the chain data number storage area 44 to the first
The combination information is read out in the same manner as in the embodiment, and the combination information is read out from the information memory 58 in the order of the read data numbers.

As a result, a series of combination information is sorted and outputted from the information memory 58 in ascending order or descending order based on the reference axis data.

Fifth Embodiment FIG. 23 shows a modification of the first embodiment as a fifth embodiment.

The feature of this embodiment is that even when the number of digits of the reference axis data stored in the reference axis data memory 10 is large, the reference axis data can be sorted at high speed without increasing the memory capacity of each buffer memory 20, 30, 40. It is to do so.

In this embodiment, the reference axis data memory IO has a reference axis data storage area 14 whose address is designated by a data number.

Further, two sets of chain buffer memories 40 are provided, and are configured such that when data is being written to one memory 40, data is being read from the other memory 40.

Then, the reference axis data outputted from the data generation circuit 8 is sequentially written and stored in the corresponding storage area 14 in the order of the data number. In the embodiment, the reference axis data consisting of 3M bits is written into the corresponding storage area 14.

When writing of the reference axis data into the reference axis data memory 10 is completed in this manner, reading of the reference axis data from the reference axis data memory 10 is then started.

The feature of this embodiment is that the 3M bit data constituting the reference axis data is divided into a plurality of search digits for each predetermined bit, and the reference axis data memory 10 is read out from the reference axis data memory 10 in units of search digits. It is in.

In this embodiment, when the writing of the reference axis data into the reference axis data memory 10 is completed, the lower M bit data is sequentially read out from the reference axis data memory 10 in the order of data numbers 1 to N, and is stored in the first buffer. memory 20
and is output to the last buffer memory 30.

The lower M bit data of each reference axis data read out in this way is subjected to sorting processing in the same manner as in the first embodiment. At this time, data is written into one of the two chain buffer memories 40 provided.

Therefore, data numbers are written in the chain data number storage area 44 of the one chain buffer memory 40 so that the lower M bits of the reference axis data are chained in ascending or descending order.

In this embodiment, the fourth control circuit 80d reads out the data number written in the chain data number storage area 44 of one chain buffer memory 40 according to a predetermined rule, as in the first embodiment. Therefore read out.

Then, the middle M-bit data of the reference axis data is controlled to be read out from the reference axis data memory 10 to each buffer memory 20, 30 in the order of the read data number.

The middle M-bit data of the reference axis data read in this manner is similarly sorted. At this time, data is written into the other of the two chain buffer memories 40 provided. As a result, data numbers are written in the chain data number storage area '44 of the other chain buffer memory 40 so that the middle M-bit data of the reference axis data are chained in ascending or descending order.

The fourth control circuit 80d of the embodiment reads out the data number written in the other chain data number storage area 44 in accordance with a predetermined reading rule. Then, in the order of the read data numbers, the upper M bits of the reference axis data are sequentially read out from the reference axis data memory 10 and output to each buffer memory 20.30.

17 Then, the upper M bits of the reference axis data thus outputted to the buffer memories 20 and 30 are similarly sorted. At this time, data is written into one of the two chain buffer memories 40 provided. Therefore, data numbers are written in the chain data number storage area 44 of the one chain buffer memory 40 so that the upper M bits of the reference axis data are chained in ascending or descending order.

In this way, a predetermined digit of the reference axis data is set as a search digit (a digit consisting of M-bit data in the embodiment), and the sorting process of the reference axis data based on each search digit is performed as follows:
The search is repeated while shifting the search digit from the lowest search digit to the second highest search digit of the reference axis data. As a result, when the sorting process of the reference axis data based on the highest search digit is completed, data numbers are written in the chain data number memory J and rear 44 so that the reference axis data are chained in ascending or descending order. Become.

Follow. The third control circuit 80c of the embodiment, after completing the sorting process of the reference axis data based on the most significant search digit, reads the data number written in the chain data number storage area r''44 according to a predetermined reading rule. Then, reading is controlled so that the reference axis data is output from the reference axis data memory 1 [] in the order of the read data numbers.

Thereby, even if the reference axis data memory 10 is composed of a large number of digits, it is possible to perform high-speed sorting with a simple configuration without increasing the memory capacity of each buffer memory 2030.40.

Next, a specific operation for sorting the reference axis data in ascending order will be explained based on FIG. 24.

In order to simplify the explanation, an example will be described in which reference axis data composed of ternary numbers is sorted one digit at a time starting from the lowest digit.

First, assume that reference axis data is stored in the reference axis data memory 1-0 as shown in FIG. 24(A).

When the first sorting operation is started for the reference axis data stored in this manner, a variable m representing a search digit is set to 0. Then, the values of the search digit m-0 are read out from the reference axis data memory 10 in the order of their data numbers, and the read reference axis data of the search digit m-0 is sorted as described above. As a result, the data numbers are stored in the chain data number storage area 44 so that the values of the search digits m-0 of the reference axis data are chained in ascending order.

Next, the data number written in this chain data number storage area 44 is read out in a predetermined manner.

The m-1 search digit of the reference axis data is read out from the reference axis data memory 10 in the order of read data numbers according to the rules. At this time, the reading order of the reference axis data read from the reference axis data memory 10 is the 24th
The result is as shown in Figure (B). As is clear from the figure,
It will be understood that the m-ml digit values of the reference axis data are sorted and read out in ascending order according to the m-0 search digit value.

Then, when the read m=1 search digit values are sorted in the same manner, the chain data number storage area 44 stores the m-1 search digit values of the reference axis data in ascending order. That data number will be stored. Therefore, by reading the m-2 search digit of the reference axis data from the reference axis data memory 10 based on the data number written in the chain data number storage area 44, the 24th The value of the m-2 search digit of the reference axis data is read out in the order shown in Figure (C).

In this way, by repeating the sorting process while shifting the search digit one by one from the lowest digit to the highest digit of the reference axis data, the highest search digit m-
When the second sorting process is finished, the 24th reference axis data is stored in the chain data number storage area 44.
Data numbers are written in a chain in ascending order as shown in Figure (D).

Therefore, the third control circuit 80c controls the most significant search digit m
After completing the sorting process of -2, the data numbers written in the chain data number storage area 44 are read in a predetermined reading order, and the reference axis data is read from the reference axis data memory 10. As a result, the reference axis data memory 10
From then on, the reference axis data is sorted and output in ascending order as shown in FIG. 24(D).

Note that although the case where the reference axis data is sorted in ascending order is explained here as an example, by repeating the operation of sorting the values of each search digit in descending order, the reference axis data can be sorted and output in descending order. You can also do it.

Further, in this embodiment, the case where two sets of chamber buffer memories 40 are provided has been described as an example. However, the present invention is not limited to this, and for example, after once transferring the data number written to the chain buffer memory 40 to another memory, reading the data number from the memory according to a predetermined reading rule,
Reference axis data memory 10 in the order of read data numbers.
J:
stomach. By doing so, the data sorting speed is reduced, but only one set of the check buffer memory 40 is required.

Sixth Embodiment FIG. 25 shows a sixth preferred embodiment of the present invention. The third embodiment has been described by taking as an example a case where a circuit for sorting sorting data including combination information based on reference axis data is formed using the circuit of the first embodiment. This embodiment is characterized in that such a sorting circuit is formed using the circuit of the fifth embodiment.

The sorting circuit of this embodiment is composed of an information memory 58 and the circuit shown in the second embodiment.

The reference axis data included in the sorting data output from the external data generating circuit 8 is input to the reference axis data memory 10 and subjected to sorting processing in the same manner as in the fifth embodiment. Therefore, data numbers are stored in the chain data storage area 44 of the chain buffer memory 40 so that the reference axis data are chained in ascending or descending order.

Then, the third control circuit 80e transfers the data number stored in the chain data number storage area 44 to the fifth control circuit 80e.
As in the embodiment, combination information is read out and controlled from the information memory 58 in the order of data numbers read out 7 and read out j7. As a result, a series of combination information is sorted and output from the information memory 58 in ascending or descending order based on the reference axis data.

It turns out.

Comparison with the present sorting circuit The present applicant has filed an application on August 31, 1985 for a new sorting circuit separate from the present sorting circuit (Japanese Patent Application No. 1982-217044).

A simple comparison of the sorting times between the sorting circuit according to the prior application and the sorting circuit according to the first embodiment of the present application is as follows.

First, if the number of reference axis data to be sorted is N, and the number of bits of each reference axis data is , then the sorting processing time (RAM access) is simply compared as follows.

First, in the sorting circuit according to the prior application, the noting processing time is expressed as (4N+2)XM+N+4 cycles...O). Note that the details of this formula have already been described in detail in the specification of the earlier application, so the explanation thereof will be omitted here.

Here, N-1023 pieces, M-15 bits, RA
Assuming a cycle steal of 6.144 MIIz for M access, the total processing time is 82437 cycles/[t, 44 MHz −1
0.2m sec, which is one field time (approximately 18.0msec).
There is plenty of time within 5mm (5ec).

However, the number of data increased, N-2047 pieces, M-15 pieces.
As in Bit, this processing time is 124901 cycles / 6.144 M fiz -
The time required is 20.3 m sec, which means that one field time is not enough.

As described above, in the sorting circuit according to the prior application, if the number of data items to be sorted is larger than the number of bits of the data, the sorting process cannot be performed in the time equivalent to one field, which causes a problem.

In particular, in the three-dimensional image synthesis apparatus described below, the number of data to be sorted (9 in system terms, the number of display polygons) tends to increase, so a faster sorting circuit is required.

The sorting circuit of the present invention was developed based on this request, and when simply calculated under the same conditions, the sorting processing time is as follows.

First, the reference axis data memories 1 and 0 read out the reference axis data at the same time, so N cycles are required.

The first buffer memory 20 requires N cycles to write data to the chain buffer memory.

2M cycles are required for reading when data is transferred to the bus 50.

The last buffer memory 30 requires N cycles to read for checking data, N cycles to write data, and 2M cycles to transfer data to the chain buffer memory 40.

Furthermore, chain buffer memory 40 requires N cycles to write data.

In addition, in order to clear the contents of the first buffer memory 20 and the last buffer memory 30 to zero before writing data to each buffer memory, the first buffer memory 20 is cleared to zero, and the last buffer memory 30 is cleared to zero. Requires N cycles to clear.

Therefore, to summarize the above, the entire sorting process requires a processing time of 7XN+2X2M+l cycles (2). Therefore, if we assume that the number of bits of the reference axis data to be sorted is M-15, change the number N of reference axis data, and calculate the sorting processing time based on the first and second equations, , the sorting processing time according to the prior application and the processing time of the sorting circuit according to the present invention are shown in the following table.

Table 1: Number of cycles for M-15 bits As is clear from Table 1, when the number of reference axis data to be sorted is small, the processing time of the sorting circuit of the earlier application is shorter. It will be understood that as the number of reference axis data to be sorted increases, the processing time of the sorting circuit of the present invention becomes significantly shorter.

Therefore, according to the present invention, as the number of reference axis data increases, it is possible to perform high-speed sorting that significantly reduces the sorting time.

Applications As explained above, the sorting circuit according to the present invention can sort a large amount of reference axis data at high speed. For this reason, reference axis data is combined with various information,
Even when the amount of data is large, it is possible to sort the various types of sorting data with a large amount of data at high speed based on the reference axis data.
It can be widely used for sorting based on first class reference axis data and for other purposes.

Specific Example FIG. 5 shows a preferred specific example of a three-dimensional image synthesis device to which the present invention is applied. Polygon information transfer circuit 52. It includes a sorting circuit S and a polygon display circuit 60, and is formed to synthesize and display a three-dimensional two-dimensional image, that is, a pseudo three-dimensional image, on the CRT of the polygon display circuit 60.

In this embodiment, the polygon information generation circuit 50 includes:
It handles three-dimensional three-dimensional information, including rotation, translation, perspective,
Various transformations such as projection are applied to convert the three-dimensional information to be displayed into two-dimensional polygon combination information, and the (
X, Y) coordinates are calculated as polygon information.

Note that the polygon information generation circuit 50 also calculates the display point in the depth direction of each polygon, that is, the Z coordinate of the center of each polygon, as polygon information, and further calculates color information, brightness information, etc. of the polygon as necessary. Calculate as accompanying information.

In addition, in this example, to simplify the explanation,
The following explanation will be given assuming that color information is calculated as the accompanying information.

FIG. 6 shows an example of polygon information of a polygon calculated in this manner.

In this way, the polygon information generation circuit 50 generates polygon information for each of the four polygons (XY coordinates at the vertex positions of the polygons,
After calculating the Z coordinate and color information at the center point, the polygon information transfer circuit 52 separates the polygon information of each polygon into 5Z coordinate data and other data, as shown in FIG. Coordinate data as reference axis data memory 1
-0, and write other data (combination information) to XY
Write to RAM58.

In this manner [7], each time polygon information of each polygon is calculated and output from the polygon information generation circuit 50, the Z coordinate of this polygon information is sequentially input into the reference axis data memory 10, and other than the Z coordinate The polygon information is X Y R
The data are sequentially input to A M 58.

At this time, the data number 17 register 54 counts the number of polygons calculated and output from the polygon information generation circuit 50, and detects the number of displayed polygons for each rask scan.

FIG. 8 shows a sorting circuit S used in the three-dimensional image synthesis device of the embodiment. , are sorted in ascending order from the smallest Z coordinate value and output to the polygon display circuit 60.

Therefore, as shown in Fig. 9, the reference point is the CRT screen, and the X
When the YZ three-dimensional coordinates are set, the sorting circuit S will sort and output the polygon information of the polygon displayed in the front of the screen, that is, the polygon with the highest priority.

Then, the polygon display circuit 60 synthesizes the polygon information of each polygon output in this way into an image based on its priority. For example, when multiple polygons are displayed in an overlapping manner, Three-dimensional images are synthesized so that polygons with high priority are displayed preferentially.

Polygon information generation circuit Figure 10 shows the airplane control system, Mi! A specific configuration of a polygon information generation circuit 50 applied to a notator device is shown, and the polygon information generation circuit 50 of the embodiment calculates and outputs simulation images of various flight conditions during flight.

First, the three-dimensional calculation circuit 50-4 assumes a moving coordinate system with the airplane as its origin.

When the main CPU circuit 50-2 outputs movement coordinates representing the current position of the airplane, the three-dimensional calculation circuit 50-4 reads predetermined polyhedral data from the three-dimensional information memory 50-3.

In the embodiment, since the information written in the three-dimensional information memory 50-3 is expressed using a fixed coordinate system, the three-dimensional calculation circuit 50-4 reads out the information from the three-dimensional information memory 50-3 ( It is necessary to convert the obtained information into coordinate data of the moving coordinate system.

This conversion can be achieved by a combination of two calculation elements: coordinate rotation and translation, and in the process of this calculation, information that is found to be out of the pilot's field of vision (Zku0) is removed. The situation data obtained by the conversion is output to the main CPU circuit 50-2. Then, each piece of coordinate-converted polyhedral information is then subjected to perspective projection transformation toward the Z-0 viewpoint, assuming that the display screen is on the Z-0 plane.

Through such perspective projection transformation, each polyhedron data is represented as a collection of point information obtained by converting the coordinates of each vertex of the polyhedron into two dimensions of X and Y.

Furthermore, in performing such perspective projection transformation, the distance between the viewpoint and the coordinates of each vertex of the polyhedron is determined in advance.

Then, the two-dimensional point coordinates (vertex coordinates of the polyhedron) obtained by the perspective projection transformation are classified for each polygon representing the surface of the polyhedron, and whether the classified polygon falls within the field of view of the pilot, that is, the field of view of the screen. Polygons that do not fit into the field of view are removed.

After that, this three-dimensional calculation circuit 5 (14) calculates the 2D value at the center point of the polygon for the polygon that falls within the accepted coordinate range.
Determine the coordinate value as a representative value.

At the same time, the three-dimensional calculation circuit 50-4 calculates accompanying data of each polygon within the coordinate range, and in the embodiment, color information.

Then, the three-dimensional calculation circuit 50-4 outputs the XY coordinates of the vertices of each polygon, the Z coordinate of the center position, and color information obtained in this way for each polygon as polygon information.

The polygon information of each polygon output from the polygon information generation circuit 50 of the embodiment is composed of 17 words, of which 1-word is the Z coordinate of the center point, and the remaining 16 words are the XY coordinates of the apex of the polygon. , is used to represent color information, etc.

Furthermore, one word is composed of 16 bits.

In this way, the polygon information generation circuit 50 of the embodiment converts the situation in the field of view of the pilot into combination information of a plurality of polygons, and sequentially outputs the polygon information of each polygon to the sorting circuit S. Become.

Here, each polygon is displayed closer to the screen as the Z coordinate value included in the polygon information is smaller, so the smaller the Z coordinate value included in the polygon information, the higher the priority of the polygon is. become. Therefore, by sorting the polygon information of each polygon that is randomly output in this way in order of decreasing Z coordinate value, it becomes possible to easily and quickly synthesize a three-dimensional image by the polygon display circuit 22.

Sorting Circuit The sorting circuit of the present invention is characterized in that it sorts a plurality of data including predetermined reference axis data based on the reference axis data.

FIG. 8 shows a specific configuration of the sorting circuit S according to this embodiment.

This sorting circuit S includes a reference axis data memory 10 and an XYRAM 58 used as an information memory. Z-axis information is written to the reference axis data memory 10,
The remaining information is written to XYRAM58.

Here, the reference axis data memory 10 includes a first buffer memory 20. Last 1~Buffer Memory 30
and chain buffer memory 40 are formed as a group of sorting RAMs 70.

The sorting control circuit 80 controls writing and reading of data in the sorting RAM 70, and writes the data number to the chain buffer 40 so that the reference axis data is chained in ascending order.

Then, the data number written in this chain buffer 40 is read out according to the predetermined reading rule described above. Thereafter, one screen's worth of polygon information is read out from the XYRAM 58 in the order of the read data numbers.

In this way, the apparatus of this embodiment can sort one screen's worth of polygon information output from the polygon information generation circuit 50 in ascending order based on its Z coordinate and output it to the polygon display circuit 60. .

Hereinafter, the specific circuit configuration will be explained in detail by taking the sorting circuit of the third embodiment (the sorting circuit shown in FIG. 19) as an example.

(a) First control circuit 80a FIG. 11 shows a specific circuit configuration of the first control circuit 80a shown in FIG. 19, and FIG. 12 shows a flowchart showing its operation. has been done.

This first control circuit 80a has a reference axis data memory]0
The Z-axis data written in is read out sequentially in the order of the data number. Then, using the read Z-axis data as an address, the corresponding data number is stored in the first buffer memory 20.
．． Write to the last buffer memory 30. At the same time, when the data number in the last buffer memory 30 is updated and stored, the updated data number is written into the chain buffer memory 4o using the pre-updated data number as an address.

In this embodiment, the first control circuit 80a includes a data number pointer 12, a data number register 54, a comparison/determination circuit 110, and a step 1 control circuit 112.

Here, the data number pointer 12 is formed so as to output data numbers 1 to N as write/read addresses of the reference axis data memory 1o, as described above.

Therefore, when outputting Z-axis data from the reference axis data memory 1o to each buffer memory 20, 30 and 40, this data number pointer 12 will change the data number by 1, 2, 3, etc. as shown in FIG. , . . . are output sequentially in increments.

As a result, the Z-axis data is sequentially outputted from the reference axis data memory 10 in the order of the data number to the at l female input terminal of each buffer memory 20.30, and is also outputted to the step 1 control circuit 112. Become.

At this time, the data number output from the data number pointer 12 is output to the data input terminals I of the first buffer memory 20, last buffer memory 30, and chain buffer memory 40, and is also output to the comparison/judgment circuit 110. It is being output.

Therefore, each data number storage area 24.3 in the first buffer memory 20 and the last buffer memory 30
4, as shown in the flow 1000 of FIG. 12, for example, the reference axis data input to the address input terminal A is used as a write address, and the data capital number input to the data input terminal I is written and stored. Become.

At this time, when the data number in the last data number storage area 34 is updated and stored, the data before the update is output from the output terminal O to the address input terminal A of the chain buffer memory 40.

Therefore, as shown in flow 1100 in FIG. 12, the data number storage area 44 of the chain buffer memory 40 is output from the data number pointer 12 with the pre-update data number output from the last buffer memory 30 as an address. The new data number will be written and stored.

Such data transfer/writing work is repeated every time a new data number is incremented and output from the data number pointer 12.

The comparison/judgment circuit 110 then selects the data number pointer 1
When the data number incremented from 2 matches the number of polygon information for the CRT screen output from the data number register 54, the step 1 control circuit 112
Outputs a transfer control end signal to Thereby, step 1 control circuit 112 completes a series of data writing operations to buffer memories 20, 30 and 40.

Next, the sorting circuit switches to operation in step 2. Then, using the data number stored in each data number storage area 34 of the last buffer memory 30 as a write address, the first buffer 2 in a predetermined correspondence relationship is written.
The data number in the data number storage area 24 within 0 is stored in the data number storage area 4 in the chain buffer memory 40.
4 starts a series of operations.

(b) Second control circuit 80b FIG. 13 shows a specific circuit configuration of the second control circuit 80b that performs such transfer control in step 2, and FIG. 14 shows its operation. A flowchart is shown.

This second control circuit 80b is the step 2 control circuit 21
0, start address selector 212, start address pointer 214, and address pointers 22 and 32.

Then, when the step 2 operation is started, the step 2 control circuit 210 resets each address pointer 22.32 to "0" according to the flow 2000 shown in FIG. 14. Then, in the first data storage area 24 specified by the rOJ address output by the address pointer 22,
Determine whether a data number has been written. At this time, if the data number is not stored at address 0, the address pointer 22 is incremented, and the data number is stored in the first data number storage area 24 specified by the new incremented address. Determine whether or not there is. Such a determination operation is repeated according to the flow 2100 shown in FIG. 14 until the first data number storage area 24 in which the data number is stored is detected.

When the first data number storage area 24 in which the data number is stored is detected, the data number at that time is used as the start address and the start address pointer 3
Set to 10. Therefore, taking the case shown in FIG. 3 as an example, the first data number storage area 24 (in this case, address 0
Data number "5" corresponding to the reference axis data is read from the storage area 24) designated by and set in the start address pointer 310 as the start address.

In this way, the start address is set.
Next, according to the flow 2200 in FIG. 14, the data number stored in the last data number storage area 34 is set as a write address, and the data number stored in the first data number storage area 24 in a predetermined correspondence with this is set as a write address. A series of operations of writing to the data number storage area 44 are repeated. As a result, as shown in FIG. 3, for example, the chain data number storage unit 7'44 has
Data numbers are written so that the reference axis data (in this case, Z-axis data) are chained in ascending order.

At this time, for example, as shown in FIG. 4, if there is a storage area in which no data number is written in the data number storage areas 24 to 34, 1. Data number memory, 'T
-While determining whether or not a data number is written in the rear 24, it is the farthest where the data number is written! - Increment address pointer 24 until 24 is detected in the data number storage area.

Then, at the same time as the first data number storage area 24 in which the data number is stored is detected, the C chain data number storage area 44 is detected according to flow 2200.
Similarly, data number writing is performed in L2.

(e) Flag memory 21-4 By the way, when sorting the reference axis data in hundreds or tens of units, the first data number storage area 24 in which the reference axis data is written is detected. This requires a certain amount of time. However, considering that in a three-dimensional imaging device, a series of sorting operations must be completed within one field time (1,760 seconds), the detection time becomes a value that cannot be ignored.

Therefore, in this embodiment, a flag memory 214 is provided in order to significantly shorten such detection time and enable faster sorting.

FIG. 16 shows the configuration of this flag memory 214 in association with the first data number storage area 24.

This flag memory 214 has a plurality of 1-bit flag storage areas 214a that correspond 1:1 to each first data number storage area 24, and when data is stored in the first data number storage area 24, the corresponding j
A flag is set in the bit flag area 214a.

In the embodiment, the flag memory 214 has eight 1
The pit flag area is designated as a group by the flag address, and the flag information from the group of flag areas designated by the flag address is
It is configured to output 8-bit data).

Therefore, for example, if you specify flag address 000H,
From the 8-bit flag information output from the flag memory 214, the first data storage area 2 for 8 addresses specified by address 0000I (~0007H)
It is possible to determine at once whether or not there is a storage area in which a data number is written in 4.

When a flag indicating writing of a data number is detected while detecting the data number storage area 24 in which a data number is written using such flag memory 214, at this time, the data number specified by the flag address is detected. 8 bits worth of flag information is written to the shift register 210a as shown in FIG.

Then, the step 2 control circuit 2-0 shifts the contents of the shift 1 nozzle 210a to the right one bit at a time, and detects the first data number storage area 24 in which the data number is written. .

In this way, the embodiment 210 sequentially increments the flag address of the flag memory 214 from 0OOH and sequentially reads out the contents of the flag memory 214 8 bits at a time. is being detected at high speed.

Note that writing the flag to the flag memory 214 is as follows:
This is performed by the step 1 control circuit 112 shown in FIG. That is, this step 1 control circuit 112 writes the data number to the first data number storage area of the first buffer memory 20, and at the same time writes the data number to the first data number storage area of the first buffer memory 20.
The 14 corresponding flags are set in sequence.

By doing this, step 2 shown in FIG.
The operation of writing data from each buffer memory 20 and 30 to chain buffer memory 40 can be performed at higher speed.

Further, if such a flag memory 214 is used, by clearing the flag memory 214 to zero, there is no need to clear the buffer memories 20 and 30 to zero.

Furthermore, in this embodiment, the reason why each group of flag memories 2 to 4 specified by the flag address is set to 8 bits is considered to be optimal from the physical data number order of the memories and from a probabilistic viewpoint. Because I thought about it.

For example, consider the problem of how many bits should be read in order to minimize the read time when 2'' pieces of data are randomly written to 2'' addresses.In this case,
The bit unit specified by each flag address is 1
When calculating as 6 bits, 8 bits, 4 bits, and 2 bits, the minimum unit is 4 bits. However, since data may overlap at the same address, the minimum value would be obtained by combining the bit units specified by the flag address with 4 bits and 8 bits, but depending on the physical memory configuration, 8 bits would be the minimum value. I chose bit units.

(d) Third control circuit 80e Also, as explained above (again, data numbers are written in each data number storage area 44 in the chain buffer memory 40 so that the reference axis data is chained in ascending order). ,
Next, the written data numbers are read out according to a predetermined reading rule, and read out from the XVRAM 58 in the order of data numbers.
The operation in step 3 of sorting and outputting polygon information starts from.

FIG. 17 shows a third step that performs the operation of step 3.
The specific circuit configuration of the control circuit 80e is explained, and FIG. 18 shows a flowchart 1. showing its operation.

In this embodiment, the third control circuit 80e includes the step 3 control circuit 312. Data number counter 314. Comparison/judgment circuit 316. Address pointer 42. Start address pointer 310. Selector 318. Includes latch 320.

Then, when the step 3 operation is started, the step 3 control circuit 3-2 first resets the address pointer 42 and the data number counter 31-4. Next, the selector 318 is switched to the start address pointer 3/0 side, and the data number set in the start address pointer 310 is set as the start address and output to the XVRAM 58 via the selector 3/8° latch 320. do.

As a result, for example, as shown in FIG. 3, if data number "5" is set as the star address, the polygon information specified by this data number "5" is output from the XVRAM 58. That will happen.

In addition, in synchronization with such a read operation, the value of the pig number counter 314 is incremented by one, and at the same time, the data number output from the latch 320 is set in the AT female pointer 42 as the next read address. .

In this way, when the first polygon information is read,
Next, the step 3 control circuit 312 switches the selector 318 from the starter address pointer 310 side to the chain buffer memory 40 side.

Then, the step 3 control circuit 312 sorts and outputs the polygon information from the XYRAM 58 based on the Z-axis data according to the flow 3000 shown in FIG.

That is, when a data number is output from the address pointer 42 as a read address, the chain data storage area 44 specified by this read address
From selector 318. The data number is read out via the latch 320. Then, polygon information is output from the XYRAM 58 using the read data number as a read address, and the data number is set in the address pointer 42 as a new read address.

The sorting circuit of the embodiment repeatedly performs such a polygon information reading operation.

At this time, the data number counter 314
Count the number of accesses, that is, the number of polygon information sorted and output from the XYRAM58 [7,
The count value is outputted to the comparison/judgment circuit 316.

Then, when the value of the data number counter 314 matches the number of polygon information counted in advance by the data number register 54, the comparison/judgment circuit 316 outputs an end signal to the step 3 control circuit 312.

In this way, the sorting circuit of this embodiment completes a series of sorting operations.

It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made within the scope of the gist of the present invention.

[Effects of the Invention] As described above, according to the present invention, it is possible to sort and output a large number of reference axis data with a simple circuit and at high speed.

In particular, according to the present invention, when the number of reference axis data is large compared to the number of bits of the reference axis data, the sorting operation can be performed at high speed, which is extremely effective when a large number of data are to be sorted. Become something.

Furthermore, according to the fourth aspect of the present invention, even when the reference axis data is combined with various types of information and the amount of data becomes large sorting data, such sorting data with a large amount of data can be processed based on the reference axis data. Since it can perform high-speed sorting, it can be used in a wide variety of applications.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the basic configuration of the sorting circuit according to the present invention, FIG. 2 is an explanatory diagram showing the data transfer operation from the reference axis data memory to each buffer memory, and FIGS. 3 and 4 are An explanatory diagram showing the data transfer operation from the first buffer memory and the last buffer memory to the chain buffer memory, FIG. 5 is a block circuit diagram showing an example of a three-dimensional image synthesis device to which the sorting circuit of the present invention is applied, and FIG. 7 is an explanatory diagram of polygon information calculated and output from the polygon information generation circuit shown in FIG. 5, and FIG. 8 is a block diagram of the sorting circuit of the present invention used in the three-dimensional image synthesis device shown in FIG. 5. 9 is a three-dimensional conceptual diagram of an image displayed using the circuit shown in FIG. 5; FIG. 10 is a block circuit diagram showing a specific configuration of the polygon information generation circuit shown in FIG. 5; FIG. 11 is a block circuit diagram showing an example of the circuit configuration of the sorting circuit of the present invention, FIG. 12 is a flowchart showing the operation of the circuit shown in FIG. 11, and FIG. 13 is a specific example of the sorting circuit of the present invention. A block circuit diagram showing an example of the circuit configuration, FIG. 14 is a flowchart showing the operation of the circuit shown in FIG. 13, FIG. 15 is an explanatory diagram of flags registered in the shift register of the circuit shown in FIG. 13, FIG. 16 is an explanatory diagram showing the configuration of the flag memory used in the circuit shown in FIG. 13 in association with the first data number storage area. FIG. 17 is an example of a specific circuit configuration of the sorting circuit of the present invention. 18 is a flowchart showing the operation of the circuit shown in FIG. 17, FIG. 19 is an explanatory diagram of the third preferred embodiment of the present invention, and FIG. When sorting,
FIG. 21 is an explanatory diagram showing the operation of transferring data from the first buffer memory and the last buffer memory to the chain buffer memory. FIG. 22 is an explanatory diagram of the second preferred embodiment of the present invention. FIG. 23 is an explanatory diagram of a fifth preferred embodiment of the present invention. 10... Reference axis data memory, 12... Data number pointer, 13... Data number counter, 20... First buffer memory, 24... First data number storage area, 30... Last buffer memory , 34...Last data number storage area, 40...Chain buffer memory, 44...Chain data number storage area, 58...
Information memory 80... sorting control circuit, 80a... first control circuit, 80b... second control circuit, 80e... third control circuit, 80d... fourth control circuit. FIG. 25 is an explanatory diagram showing an example of sorting operation of the sorting circuit; FIG.
Patent Attorney Yukio Fuse (and 2 others) Figure 22

Claims (10)

[Claims] (1) A circuit for sorting a plurality of input reference axis data, comprising data number generation means for generating a data number corresponding to each input reference axis data, and an address designated based on the reference axis data. a first buffer memory having a first data number storage area, and storing a data number generated by the data number generation means in this storage area when reference axis data corresponding to each storage area is input for the first time; It has a last data number storage area whose address is specified based on the axis data, and each time the reference axis data corresponding to each storage area is input, the data number generated by the data number generation means is updated and stored in this storage area. a chain buffer memory having a chain data number storage area whose address is specified based on the last buffer memory data number to be updated, and a chain data number storage area whose address is specified based on the last buffer memory data number; a first control means for writing a new data number to be updated in a number storage area; By writing the data number stored in the first data number storage area that has a predetermined correspondence with the last data number storage area into the specified chain data number storage area, the reference axis is stored in the chain data number storage area. a second control means for writing data numbers so that the data are chained in ascending or descending order; and a second control means for reading the data numbers written in the chain data number storage area according to a predetermined reading rule, and reading each input reference axis data. A sorting circuit comprising: third control means for sorting and outputting read data in order of numbers. (2) Claim (1), further comprising a reference axis data memory that stores each input reference axis data in the order of its data number, and the data number generating means directs the data number to the reference axis data memory as a read address. The first buffer memory is formed by using a data number pointer to output and read out each reference axis data from the reference axis data memory in order of data number, and the first buffer memory stores the corresponding reference axis data from the reference axis data memory to each storage area first. The last buffer memory is configured to store a data number output from the address pointer when input, and the last buffer memory stores the data number in each storage area from the reference axis data memory every time the corresponding reference axis data is read out from the reference axis data memory. The third control means updates the data number stored in the chain data number storage area with the data number output from the address pointer, and the third control means updates the data number written in the chain data number storage area according to a predetermined reading rule. 1. A sorting circuit characterized in that the sorting circuit is configured to sort and output reference axis data from a reference axis data memory in the order of read data numbers. (3) Claim (1), further comprising a reference axis data memory that stores each input reference axis data in the order of its data number, and the data number generating means corresponds to each reference axis data each time it is input. The first buffer memory is formed using a counter that outputs a data number to each of the buffer memories, and the first buffer memory is configured to output data from the counter when each storage area is first addressed by input reference axis data. The last buffer memory is configured to store the data number written in the storage area from the counter each time each storage area is addressed by input reference axis data. The third control means reads out the data numbers written in the chain data number storage area according to a predetermined reading rule, and reads the data numbers from the reference axis data memory in the order of the read data numbers. A sorting circuit characterized in that it is formed to sort and output reference axis data from. (4) A circuit for sorting a plurality of input data based on predetermined reference axis data, and an information memory that stores necessary parts of each of the data in correspondence with the data numbers; a sorting means into which the reference axis data to be input is input; the sorting means includes: data number generation means to generate a data number corresponding to each input reference axis data; and an address is specified based on the reference axis data. a first buffer memory having a first data number storage area in which the first data number is stored, and storing a data number generated by the data number generation means in this storage area when the reference axis data corresponding to each storage area is input for the first time; It has a last data number storage area whose address is specified based on the reference axis data, and updates the data number generated by the data number generation means in this storage area every time the reference axis data corresponding to each storage area is input. a chain buffer memory having a chain data number storage area whose address is specified based on the data number; and a chain buffer memory having a chain data number storage area whose address is specified based on the data number; a first control means for writing a new data number to be updated into a chain data number storage area; and a first control means for writing a new data number to be updated into a chain data number storage area; By writing the data number stored in the first data number storage area that has a predetermined correspondence with the last data number storage area into the chain data number storage area specified by the data number, the chain data number storage area a second control means for writing data numbers so that the reference axis data are chained in ascending or descending order; and a second control means for reading out the data numbers written in the chain data number storage area according to a predetermined reading rule, and reading out the data numbers in the order of the read data numbers. A sorting circuit comprising: third control means for reading data from the information memory, and sorting and outputting a plurality of data based on reference axis data. (5) Claim (4) includes a reference axis data memory that stores each input reference axis data in the order of its data number, and the data number generation means directs the data number to the reference axis data memory as a read address. The first buffer memory is formed by using a data number pointer to output and read out each reference axis data from the reference axis data memory in order of data number, and the first buffer memory stores the corresponding reference axis data from the reference axis data memory to each storage area first. The last buffer memory is configured to store a data number output from the address pointer when input, and the last buffer memory stores the data number in each storage area from the reference axis data memory every time the corresponding reference axis data is read out from the reference axis data memory. The third control means updates the data number stored in the chain data number storage area with the data number output from the address pointer, and the third control means updates the data number written in the chain data number storage area according to a predetermined reading rule. What is claimed is: 1. A sorting circuit characterized in that the sorting circuit is configured to read out data from an information memory in the order of read data numbers and to sort and output data according to the read data numbers. (6) In claim (4), the data number generating means is formed using a counter that outputs a corresponding data number to each of the buffer memories each time each reference axis data is input, and the first buffer The memory is configured to store in each storage area a data number output from the counter when each storage area is first addressed by input reference axis data, and the last buffer memory is configured to store a data number output from the counter in each storage area The third control means is configured to update the data number written in the storage area to the data number output from the counter each time the address is specified by input reference axis data, and the third control means is configured to update the data number written in the storage area to the data number output from the counter. A sorting circuit characterized in that it is configured to read data numbers written in a data number storage area according to a predetermined reading rule, and to sort and output data from the information memory in the order of the read data numbers. (7) A circuit that sorts a plurality of reference axis data consisting of multiple digits based on a data number given corresponding to each of the reference axis data, the circuit sorting each of the reference axis data,
A reference axis data memory is stored corresponding to the data number, and the data number is output as a read address to the reference axis data memory, and the value of the lowest search digit of each reference axis data is read from the reference axis data memory as the data number. It has a data number pointer that is sequentially read out, and a first data number storage area whose address is specified based on the reference axis data of a predetermined search digit output from the reference axis data memory, and a corresponding one from the reference axis data memory to each storage area. a first buffer memory that stores a data number output from the address pointer when the reference axis data to be searched is first input; and an address is specified based on the reference axis data of a predetermined search digit output from the reference axis data memory. Each time the corresponding reference axis data is read out from the reference axis data memory to each storage area,
a last buffer memory that updates a data number stored in the storage area to a data number output from the address pointer; a chain buffer memory having a chain data number storage area in which an address is specified based on the data number; a first control means for writing a new data number to be updated into a chain data number storage area specified by the data number before update, each time the data number of the buffer memory is updated; After writing the data number to the last buffer memory, the first data number that has a predetermined correspondence with the last data number storage area is stored in the chain data number storage area specified by the data number stored in the last data number storage area. a second control means for writing a data number such that the reference axis data is chained in ascending order or descending order in the chain data number storage area by writing the data number stored in the storage area; The upper digit of is set as the search digit, and the data number written in the chain data number storage area is read out according to the predetermined reading rule, and the reference axis data is read from the reference axis data memory in the order of the read data number. The sorting process for each search digit, in which the set search digit is output to each of the first buffer memory and last buffer memory, is performed by shifting the search digit one digit at a time from the lowest digit to the highest digit of the reference axis data. After the fourth control means repeatedly performs the sorting process for the most significant search digit, the data numbers written in the chain data number storage area are read out according to a predetermined reading rule, and the data numbers are read out in the order of read data numbers. A sorting circuit comprising: third control means for sorting and outputting each reference axis data from the reference axis data memory. (8) A circuit for sorting a plurality of input data based on predetermined reference axis data, comprising: an information memory that stores necessary parts of each of the data in correspondence with the data numbers; a sorting means into which reference axis data is input; the sorting means includes: a reference axis data memory that stores each of the reference axis data in correspondence with its data number; and a data number directed to the reference axis data memory. a data number pointer that outputs as a read address and reads out the value of the lowest search digit of each reference axis data from the reference axis data memory in order of data number; and the reference axis data of a predetermined search digit output from the reference axis data memory. It has a first data number storage area in which an address is specified based on the reference axis data memory, and stores in each storage area from the reference axis data memory the data number output from the address pointer when the corresponding reference axis data is input for the first time. It has a first buffer memory and a last data number storage area in which an address is specified based on the reference axis data of a predetermined search digit output from the reference axis data memory, and the corresponding reference is stored in each storage area from the reference axis data memory. Every time axis data is read,
a last buffer memory that updates a data number stored in the storage area to a data number output from the address pointer; a chain buffer memory having a chain data number storage area in which an address is specified based on the data number; a first control means for writing a new data number to be updated into a chain data number storage area specified by the data number before update, each time the data number of the buffer memory is updated; After writing the data number to the last buffer memory, the first data number that has a predetermined correspondence with the last data number storage area is stored in the chain data number storage area specified by the data number stored in the last data number storage area. a second control means for writing a data number such that the reference axis data is chained in ascending order or descending order in the chain data number storage area by writing the data number stored in the storage area; The upper digit of is set as the search digit, and the data number written in the chain data number storage area is read out according to a predetermined reading rule, and the reference axis data is read from the reference axis data memory in the order of the read data number. The sorting process for each search digit, in which the set search digit is output to each of the first buffer memory and last buffer memory, is performed by shifting the search digit one digit at a time from the lowest digit to the highest digit of the reference axis data. After completing the sorting process for the most significant search digit, the fourth control means reads out the data numbers written in the chain data number storage area according to a predetermined reading rule, and reads them in the order of the read data numbers. A sorting circuit comprising: third control means for sorting and outputting data from the information memory, and sorting and outputting a plurality of data based on reference axis data. (9) In any one of claims (4) to (6) and (8), the information memory stores at least the three-dimensional information (X, Y, Z). ) are stored in order of data numbers, the Z-axis data included in the three-dimensional information is input to the sorting means as reference axis data, and the three-dimensional information included in the information memory is stored in the Z-axis data. A sorting circuit characterized by outputting sorting in ascending order or descending order based on. (10) In any one of claims (1) to (9), the second control means includes a plurality of 1-bit flag areas in one-to-one correspondence with the first data number storage area, and A flag memory is provided in which a flag is set in a corresponding flag area when a data number is stored in a storage area, and a predetermined number of flag addresses are assigned to the flag area in units of one group, and each flag address specifies a flag. By reading flag information in groups from a group of flag areas, it is possible to determine whether or not a data number is written in each data number storage area without reading the data number from the data number storage area. A sorting circuit characterized by: