JP3210053B2 - Sorting equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sorting apparatus, and more particularly to an apparatus for sorting data based on a plurality of reference value data.

An image processing apparatus synthesizes and outputs various image signals for CRT display based on image information supplied from the outside, and outputs not only a two-dimensional planar image but also a three-dimensional synthesized image. For example, they are widely used in video games for three-dimensional images, computer graphics, displays of CAD devices, and other uses.

When a three-dimensional image having depth is synthesized in real time using an image processing apparatus,
It is necessary to sort the three-dimensional data of each target object at a high speed in 1/60 seconds based on the coordinate values in the image depth direction, that is, the Z-axis data.

For this reason, a plurality of three-dimensional data are
It has been desired to develop a device capable of high-speed sorting based on axis data.

However, conventionally, such sorting is
The operation of successively comparing adjacent data of the Z-axis data included in each data and rearranging the data each time is performed on all data.

In order to perform this processing, the data transfer of all the Z-axis data between the memories must be repeated many times. Therefore, there is a problem that data sorting cannot be performed at high speed.

[0007] In particular, in this conventional technique, if the number of Z-axis data to be compared increases, the sorting operation takes too much time and effort. Therefore, in order to perform high-speed sorting, a relatively large computer must be used, and there is a problem that the entire apparatus becomes complicated and expensive.

Therefore, there is a sorting apparatus which can sort a plurality of data at a high speed with a simple configuration, and can perform the sorting at a high speed even when the number of reference axis data to be sorted is large. JP-A-2-222018 (International Patent Classification G0
6F 7/24).

This sorting apparatus inputs reference axis data to be sorted to a first buffer memory and a last buffer memory in the order of their data numbers.

The first buffer memory stores, in the first data number storage area, the data number when the corresponding reference axis data is first input.

Similarly, each time the corresponding reference axis data is read out, the last buffer memory sequentially updates and stores the data number in the last data number storage area. Therefore, each last data number stores the data number when the corresponding reference axis data was last read.

When the data number stored in the last data number storage area is updated and stored, the data number stored in the storage area and the newly stored data number are input to the chain buffer memory. You.

Each time the data in the last data number storage area is updated, the chain buffer memory writes a new data number after the update to the chain data number storage area designated by the data number before the update. . Therefore, if reference axis data having the same value but different data numbers is repeatedly input, the history of the reference axis data, that is, the data number order of the reference axis data indicates the chain data number. It will be written to the storage area.

After the series of data is written to the first buffer memory, the last buffer memory, and the chain buffer memory, the last data is stored in the chain data number storage area designated by the data number stored in the last data number storage area. The data numbers stored in the first data number area having a predetermined correspondence relationship with the data numbers are sequentially written. In this way, data numbers are written in the respective storage areas of the chain data number storage area so that the reference axis data is chained in ascending or descending order.

The sorting circuit reads the data numbers written in the chain data number storage area in accordance with a predetermined read rule, and outputs the input reference axis data in the order of the data numbers.

In this manner, the input reference axis data is sorted and output in ascending or descending order.

By the way, as shown in FIG. 46, the image processing apparatus performs 3D clipping for eliminating polygons having smaller Z-axis data than the screen and polygons having larger Z-axis data than the boundary limit. Z
3D clipping that excludes polygons in the data area, and 3D picking that leaves only polygons in any arbitrary Z data area, as shown in FIG. 48, are performed.

[0018]

However, according to the above-described method, a so-called 3D clipping process for excluding a polygon having a smaller Z value than the screen surface and a polygon having a larger Z value than the field of view, or a polygon in an arbitrary Z region is used. In order to perform the remaining 3D picking processing or the like, after performing the entire sort, a certain limit Z value is required, and since a plurality of data are sorted based on a predetermined reference axis, extra data transfer is performed. there were.

The present invention provides 3D clipping processing and 3D
It is an object of the present invention to provide a sorting apparatus that can perform high-speed processing with a simple configuration even when performing a picking processing or the like.

[0020]

SUMMARY OF THE INVENTION A sorting apparatus according to the present invention is a sorting apparatus for sorting a plurality of input reference value data, wherein a data number for generating a data number corresponding to each input reference value data. Generating means for dividing input reference value data into upper and lower data, and holding the first address of a chain list of a data group having a value equal to that data at an address corresponding to each data value; Storage means for storing the address of the end point data of the chain list of the data group having a value equal to the data value at the address corresponding to the value of each divided data; and Third storage means for storing a pointer of a chain list indicating a data group having the same value as the reference value data accompanying the data; And means for controlling to process the low-order data divided only equivalent data to sort from the host data. Further, the sorting apparatus of the present invention is a sorting apparatus for sorting input reference value data consisting of a plurality of digits, and a data number generating means for generating a data number corresponding to each input reference value data. , Input reference value data to 2
A multi-digit reference value data storage area that is divided into one or more data groups and stored at addresses corresponding to respective data numbers, and a data group whose address is specified based on the reference value data of each divided data group. Has a corresponding storage area,
When the reference value data corresponding to each area is input for the first time, a count start area for storing a data number generated by a data number generation means in this storage area, and an address designated based on the reference value data A count end area for updating and storing the data number generated by the data number generating means in this storage area each time the reference value data corresponding to each area is input; A new data area to be updated is stored in a pointer area for specifying the next address to which the address is specified and a pointer area specified by the data number before the update each time the data number in the count end area is updated. First control means for writing a number, and a sort method having a sort address area corresponding to the divided data group for storing the sort result. After the data number has been written to the upper count start area and the upper count end area according to the upper reference value data of the divided data group, the data written to the upper count start area Second control means for linking the number, the data number written in the upper pointer area and the data number written in the upper count end area and writing them in the sort memory, and sorting the upper reference value data After completion of the above, the reference value data from the lower reference value data storage area corresponding to the upper reference value data of the same value data of the upper reference value data is transferred to the lower count start area and the lower count. After writing to the end area, the data number written to the lower count start area and the lower pointer area And third control means for writing the sort memory data number written in the data number and the lower count end regions incorporated come in association chain consisting comprise.

Further, the present invention includes a first flag area corresponding to the count start area, and a second flag area corresponding to the count end area, respectively.
The first flag area may be set when data is stored in the count start area, and the second flag area may be set when data in the count end area is updated.

Further, the present invention has a flag group corresponding to an address based on the upper-level reference value data, and includes means for setting a flag of the flag group of an address corresponding to an area where clipping or picking processing is performed. After the sorting of the upper reference value data, the third control means is configured to omit the sorting of the lower reference value data for the upper reference value data of the address corresponding to the clipping. good.

The sorting apparatus according to the present invention is a sorting apparatus for sorting a plurality of input reference value data having a plurality of digits, and a data number generating means for generating a data number corresponding to each input reference value data. And an upper digit and lower digit reference value data storage area for dividing the input reference value data into upper digit and lower digit data and storing them at addresses corresponding to the respective data numbers, and an upper digit reference value data A first storage area in which an address is specified based on the data number, and when the upper-order reference value data corresponding to each area is first inputted, the data number generated by the data number generation means is stored in this storage area. And a second storage area in which an address is specified based on the reference value data. The upper-order reference value data corresponding to each area is provided. Each time a data is input, an upper digit count end area for updating and storing the data number generated by the data number generating means in this storage area, and an upper digit count end area for specifying the next address whose address is specified based on the data number. A digit pointer area, and a third storage area to which an address is specified based on lower-order reference value data, and when lower-order reference value data corresponding to each area is first input,
This storage area has a lower digit count start area for storing a data number generated by the data number generating means, and a fourth storage area in which an address is specified based on the reference value data. Each time reference value data is input, a lower digit count end area for updating and storing the data number generated by the data number generating means in this storage area and a next address to which an address is specified based on the data number are specified. Whenever the data number of the lower digit pointer area and the upper row digit or the lower digit count end area is updated, the new upper digit or lower digit pointer area specified by the data number before the update is updated. First control means for writing a data number, a sort memory having a sort address area corresponding to upper and lower digits for storing a sort result, After the data number has been written to the upper digit count start area and upper digit count end area according to the upper digit reference value data, the data number written to the upper digit count start area and the data number written to the upper digit pointer area Second control means for linking the data number written in the upper digit count end area to the sort memory and writing the data number into the sort memory; and after the sorting of the upper digit reference value data, data having the same value as the upper digit reference value data. After the reference value data from the lower digit reference value data storage area corresponding to the upper digit reference value data is written to the lower digit count start area and the lower digit count end area, the data written to the lower digit count start area Number, data number written in lower digit pointer area and lower digit count end And third control means for writing the sort memory data number written in frequency in association chain consisting comprise.

[0024]

According to the present invention, the reference value data is divided into two or more data groups and the sorting process is performed. That is, distribution count sorting is performed on the reference value data on the upper side. By performing a distribution sort of only the lower-order reference value data with respect to the data group of the same reference value data from the smaller reference value data address, and sequentially writing the sorted data to the sort memory address, Sorting can be performed at high speed even for data having a large bit length.

Further, according to the present invention, after the sorting of the upper-order reference value data is completed, the sorting of the lower-order reference value data is omitted for the upper-order reference value data of the address corresponding to clipping. Can be configured,
3D clipping and 3D picking that exclude polygons of arbitrary reference value data can be performed without performing extra data transfer, and 3D clipping, 3D picking, and the like can be performed at high speed.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a pseudo three-dimensional image processing apparatus using the present invention. This apparatus is suitable for use in game machines such as racing games and airplane control simulations. One example is shown. The overall configuration of the present invention will be described with reference to FIG.

In this embodiment, the image information supply device 5
Calculates a simulation image of various conditions during driving, outputs the simulation image as information of a plurality of polygons to the polygon coordinate memory 20, determines a representative value of the distance from the viewpoint, and The Z value is determined as a polygon having a high priority, and the Z value is determined.
The value is transferred to the sort processing device 100.

The configuration of the image information supply device 5 will be described. This device includes a world memory 1, a geometric conversion circuit 2, an operation unit 3, and a main CPU circuit 4.

The world memory 1 represents all objects as a set of a plurality of polygons, and stores end point information indicating each end point of the polygon.

The operation section 3 is composed of a steering wheel, an accelerator, a brake and the like, and the operation content is converted into an electric signal and output to the main CPU circuit 4.

The main CPU circuit 4 outputs various status signals output from the operation unit 3, for example, "the vehicle has accelerated."
It receives information such as “the car has hit the guardrail”, “the car has turned along the road”, etc., calculates the situation data according to the information, and outputs it to the geometric transformation circuit 2.

The geometric conversion circuit 2 calculates a scene that the driver can see according to the current position of the vehicle calculated by the main CPU 4 while referring to various polygon data stored in the world memory 1, and according to the scene. The end point information of the geometrically deformed polygon is output to the polygon coordinate memory 20. That is, the vertex coordinates of each polygon are geometrically transformed by the perspective projection transformation, and the two-dimensional X and Y coordinates are output to the polygon coordinate memory 20.

In performing such perspective projection conversion, the distance between the viewpoint and each polygon is determined in advance. And
It is checked whether or not each polygon obtained by the perspective projection conversion falls within the driver's visual field, that is, the visual field of the screen. For the polygons in the field of view, determine the representative value of the distance from the viewpoint,
The Z value is determined as a polygon having a small representative value, that is, a polygon having a high priority, and is output to the polygon coordinate memory 20 and the sort processing device 100 as polygons having a high priority in order from a polygon having a small Z value.

A sorting apparatus 10 according to the present invention.
To 0, the Z value for each polygon calculated by the image information supply device 5 is transferred. After receiving the Z values of all the polygons, the sort processing device 100 performs a sort process closer to the screen, that is, in ascending order of the Z value, as shown in FIG. Then, the polygon addresses arranged in ascending order of the Z value are written in the sort address area.

In the polygon coordinate calculation of the sort processing device 100, information of each polygon is written into an internal memory, and the sorted data is sent to the polygon image processing circuit 30. The polygon image processing circuit 30 is
The address of the polygon having the smallest Z value is received from the sort address area of 0, and image processing is performed using the information of the XY address of the polygon coordinate memory 20 indicated by the address to display the polygon on the CRT 40.

Next, a sorting apparatus according to a first embodiment of the present invention will be described. FIG. 2 is a block diagram showing the overall configuration of the sorting device. This sorting device includes a data memory 10, a sort circuit 100, a distribution count memory 11, and a sort memory 12.

The data memory 10 includes the address generation circuit 1
3 has a storage area for storing Z value data of 1 to N specified by 3. As shown in FIG. 5, the storage area is largely divided into an H area and an L area.
Each of these areas is divided into a Z value area for storing Z value data and a NEXT pointer area for storing an associated NEXT address. Higher data of the reference value data is stored in the H area, and a reference value is stored in the L area. Lower data of the data is stored. Here, as shown in FIG.
Assuming that the data is composed of 6-bit data, the upper 8 bits of the reference value data are stored in the H area, and the lower 8 bits of data are stored in the L area. The data number generated by the data number generating means corresponding to the Z value data input to the data memory 10 is stored.

The sort memory 12, as shown in FIG.
The sort memory 12 has a sort address area for storing the sort result.
The region is divided into regions. This sort memory 12
Are stored in the sorted order.

The NEXT pointer area of the data memory 10 stores a pointer value indicating the address of the data having the same value. The sort address area of the sort memory 12 stores the address value of the data having the smallest Z value in the order of the address. Is stored.

The sorting circuit 100 uses the distribution count memory 11 as a working for the Z value input from the data memory 10 via the multiplexer 14,
The addresses sorted into the H value area and the L value area of the Z value are written to the sort memory 12 via the multiplexer 14 in the sort address areas of the H area and the L area.

As shown in FIG. 6, the distribution count memory 11 is divided into an H area and an L area as in the data memory 10, and this area is divided into a distribution count start area and a distribution count end area. I have. In this embodiment, the distribution count memory 11 is the data memory 1
It has addresses from 0 to 255 corresponding to the 8-bit data stored in the respective Z value areas of 0, and has the head address of the data of the address value in the distribution count start area. The distribution count end area has the end point address of the address value.

The clip control circuit 16 specifies a Z value area to be deleted in advance to perform the above-described 3D clipping or picking processing, and sends the specified area to the H sort processing circuit 15.

The H sort processing circuit 15 includes a data memory 10
As the sort processing of the H area stored in the storage area, NEXT of the H area of the distribution count memory 11 and the H area of the data memory
Write data to each of the pointer areas. Further, the H sort processing circuit 15 determines whether or not the sorted area is a target of clipping processing, and controls the L sort processing circuit 18 not to perform the sort processing on the target area. Controlled. In addition, between the L-side sort processing circuits, data is written to the H area of the distribution count memory 11 and the NEXT pointer area of the L area of the data memory as the sort processing of the L area stored in the data memory 10, respectively.

Next, the sorting operation of the present invention will be described. FIG. 3 is a flowchart showing this sort operation. When a plurality of reference axis data (Z value data) to be sorted is input from the image information supply device 5, data numbers 1 to N corresponding to the reference value data are assigned in the input order, and the data numbers are assigned to the address generation circuit. The upper 8 bits of the reference value data are sequentially stored in the 1 to N H areas addressed by the data number pointer, and the lower 8 bits of the reference value data are sequentially stored in the 1 to N L areas. (Step S1).

When the storage of the plurality of Z-value data to be sorted in the data memory 10 is completed in this way, the H sort processing circuit 15 sorts the H area (step S2). This H area sorting process
The Z value data stored in the H area is sequentially read from the data memory 10 in the order of data numbers 1 to N, and output to the distribution count start area and the end area of the distribution count memory 11.

In this embodiment, the reading of the Z value data is performed by sequentially outputting the data numbers in the order of 1 to N as the data number pointer read address. Then, when an address is specified by the data number, the Z value data is read from the H area of the specified Z value data to the distribution count start area and the end area of the distribution count memory 11.

The distribution count start area and the end area of the distribution count memory 11 have areas corresponding one-to-one to all possible values of the Z value data.

When the H bits of the Z value data are composed of 8 bits as in the embodiment, 0, 1, 2,.
5 for a total of 256 values. Therefore, the distribution count start area and the end area of the distribution count memory 11 are designated by the addresses 0, 1, 2,.
Storage areas are provided.

The data number of the Z value data output from the data memory 10 is written in the distribution count start area and the end area of the distribution count memory 11. In this embodiment, the data numbers are represented by 1 to N, and the maximum value is N.

When the Z value is input from the data memory 10 to the distribution count start area and the end area of the distribution count memory 11, the distribution count start area and the end area are designated by the address pointer of the corresponding address generation circuit 17. The data number of the Z value is written in the storage area to be written.

In this embodiment, data writing is performed as follows. That is, when the Z value data of the data number designated by the data number pointer of the address generation circuit 13 is output from the data memory 10,
The value data is set in an address pointer of the address generation circuit 17, and the set Z value data is output from the address pointer as a write address. Then, the data number (data number corresponding to the Z value) specified by the data number pointer is written in the distribution count start area and the end area of the distribution count memory 11 specified by the write address.

Here, once the data number is stored in the distribution count start area of the distribution count memory 11, even if new Z-value data of the same value is sequentially output from the data memory 10, the new data number overlaps. It is configured not to be written. On the other hand, even if a data number is once stored in the distribution count end area, when the same Z value is output from the data memory 10 next time, the data number of the Z value is newly updated and stored. It is configured as follows.

In the distribution count start area, a data number when the Z value first appears is stored. On the other hand, in the distribution count end area, the data number at the time when each Z value appears last is stored.

When the contents of the distribution count end area are updated and recorded, the data number before the update recording is set in the address pointer, and the address of the NEXT pointer area of the data memory 10 is specified. And the specified N
A new data number after the update is written in the EXT pointer area.

For this reason, a NEXT pointer area is provided in the data memory 10 as an area holding an address to be accessed next.

The Z value is read from the data memory 10,
Distribution count start area or distribution count end area of distribution count memory or data memory 100NE
A data number is set in each of the XT pointer areas. That is, the NEXT pointer area reads out the Z value data, writes the data number, and sets the distribution count end value to the address value indicated by the value of the distribution count end area when the distribution count start value of the distribution count memory 11 has already been set. The setting of the NEXT pointer area is performed when the distribution count start area and the end area are set.

In the sorting process, the data value of the distribution count start area is read from the minimum address of the distribution count memory 11, and if the NEXT pointer is set, the NEXT pointer values are chained and read.

Further, in this embodiment, the respective relationships between the H-side and L-side areas of the data memory 10 and the distribution count memory 11 are as follows: the distribution count start area, the end area, and the NEXT pointer area of the H side area. After storing the respective data, the H-side area is processed by the above-described sort processing, and the sorted data is set in the distribution count start area, the end area, and the NEXT pointer area of the L-side area as described above.

Therefore, when the same value Z is output from the data memory 10 only once at the same address in the distribution count start area and the end area, the same data number is written. When the Z value is output a plurality of times, different data numbers will be finally stored.

Therefore, when the value of the distribution count end area of the distribution count memory 11 is updated and recorded a plurality of times, if it is known how this update is performed, the reference value data is sorted in ascending or descending order. The sequence of the data numbers of each reference value data at the time is determined.

When the distribution count end area is updated and recorded in this way, the update history is sequentially written to the NEXT pointer area in the data memory 10.

As described above, according to this embodiment,
When the Z-value data is output from the data memory 10 in the order of the data numbers, the output Z-value data is used as a write address, and the data numbers are written into the distribution count start area and the distribution count end area. NE of data memory 10 from distribution count end area
Data transfer writing to the XT pointer area is performed.

When such data transfer is started, H
The sort circuit 15 performs the following transfer control.

The data number stored in the distribution count end area is set in the address generation circuit 13. NEXT addressed by this address generation circuit 13
The data number of the distribution count start area having a predetermined correspondence with the designated address is written in the pointer area.

The writing of the data numbers is slightly different between the case where the data is sorted in ascending order and the case where the data is sorted in descending order. Here, the case where the data is sorted in ascending order will be described as an example.

For example, when a data number is stored in the distribution count end area specified by the address 0,
First, the data number stored at address 0 is set in the address pointer.

Then, the data number is read from the distribution count start area specified by the address 1, and this data number is written to the NEXT pointer area of the data memory 10 specified by the address pointer.

At this time, if the data number is not stored in the distribution count start area specified by the address 1, the data number is read from the storage area specified by the address 2 and is stored in the NEXT pointer area of the data memory. Write. If no data number is stored in the distribution count start area designated by address 2, the address is sequentially incremented in the same manner as address 3, address 4,... Until data is found.

When the data number is read from the storage area specified by the address K, the data number is stored in the NEX of the data memory 10 specified by the address pointer.
It is written to the T pointer area.

When such reading and writing are completed, the data number is read from the distribution count end area designated by the address K, and the data number is used as the write address in the same manner as the previous time.
Data is written to the XT pointer area.

The device in this embodiment repeatedly writes data in the NEXT pointer area for recording such a chain data number.

When the sorting of the upper 8 bits of the data memory 10, ie, the H area, is completed, the result of the sorting is stored in the H area of the sort memory 12 as a sort address.

Then, in this embodiment, it is determined whether or not there is an area designated by the clip control circuit 16. (Step S3) For example, sorting processing is performed in ascending order in the range of 0 to N on the H side, and the data at address 0 on the H side is read, and it is determined whether or not the data is clipped. When clipping is performed, the lower 8 bits of the data, that is, sorting of the L area is not performed, and processing corresponding to the Z value of the next H area is performed.

The address read from the sort address area in the H area of the sort memory 12 is
Data number. Now, data at address 0 is read from the H area, and if that area is not to be clipped, the L area is sorted (step S4).

Then, in the L side sort processing circuit 18, the Z value data stored in the L area of the data memory 10 described above is read out, and the data is distributed to the distribution count start area and the distribution count area of the distribution count memory 11. The data is stored in the end area, and is similarly stored in the NEXT pointer area of the data memory 10, that is, the NEXT pointer area of the L area. This operation is performed in the same manner as the above-described H area data write processing. That is, the processing of the H area uses the H area of the data memory 10 and the H area of the distribution count start area and the distribution count end area of the distribution count memory 11 to write the chain data to the NEXT pointer area of the data memory 10. On the other hand, for the data in the L area, the data stored in the data memory 1 using the data sorted by the sorting process on the H side.
The Z value data of the L area of 0 is read out, the data numbers are stored in the distribution count start area and the distribution count end area of the L area of the distribution count memory 11 according to the data, and the NEXT pointer area of the L area of the data memory 10 is stored. The chain data. Then, a distribution count start value is read from the minimum address of the distribution count memory 11, and if data is set in the NEXT pointer area, the NEXT pointer value is chained and sorting is performed.

That is, in the present invention, sorting processing is first performed on the H area, that is, the upper 8 bits of data, and it is determined whether or not the data needs to be clipped at the stage when the sorting processing has been performed.
For those whose data does not need to be clipped,
The next L-side sorting process is performed. In the L-side sorting process, the same processing as that for the H-side area is performed, and the sorting is completed. Then, the sorted result is similarly written into the sort address area of the L area of the sort memory (step S5), and it is determined whether or not all the data has been sorted. Clipping is performed until all the data is sorted. The L-side sorting is repeated from the processing determination as to whether or not it is necessary.

When all sorting is completed, the operation is completed.

Next, a case where 16 sorts of Z value data output from the image information supply device 5 are sorted in ascending order using such a sorting circuit will be described as an example.

In this embodiment, since 16 pieces of Z value data are to be sorted, the data memory 10 has one
Z value area and L value of H area specified by data numbers
What is necessary is just to form so that it may have a Z value area | region. Also,
As described above, the Z value data is composed of 8 bits × 2, that is, 8 bits in the H area and 8 bits in the L area.

First, from the image information supply device 5 to the data memory 10, the upper 8 bits, that is, the data of the H value,
1, 2, 4, 5, 3, 0, 0, 1, 5, 6, 7, 9, 1,
When input is performed in the order of 0, 1, 2, 1, the input Z value data sequentially addresses data numbers 1, 2, 3,.
It will be written to the storage area of the area.

The lower 8 bits, that is, the data in the L area is 5, 6, 3, 1, 5, 4, 10, 2, 8, 5, 7, 1,.
When the data is input in the order of 1, 2, 7, and 5, the input Z value data is sequentially written to the storage areas addressing the data numbers of 1, 2, 3, 4, 5,... In the L area. .

As described above, L in the data memory 10 is
When the Z value data is written in the area and the H area, the sorting of the Z value data is performed using the data number instead of the Z value data itself.

Thus, even when the Z-value data to be sorted has a large number of digits, the Z-value data can be sorted at a high speed with a simple circuit.

In this embodiment, when the Z value is written in the Z value data memory 10 as described above, the Z value is sequentially read from the data memory 10 in the order of the data number. FIG. 19 is a schematic diagram showing a state in which the Z-value data transferred from the image supply device 50 has been written into the data memory 10.

In this embodiment, when the Z value data is written in the data memory 10 as described above, the data is sequentially read from the data memory 10 in the order of the data number. First, only the H area is read out, and the H area is sorted as shown in FIGS.

As shown in FIG. 20, when data number 1, that is, Z-value data 1 specified by address 1 is output from data memory 10, the distribution count start area and the end of distribution count are set using this Z-value data 1 as an address. Data number 1 is written in the area.

The sort processing of the H area is continued, and as shown in FIG. 21, the data number 2 is input to the distribution count start area and the distribution count end area using the Z value data 2 specified by the data number 2 as an address. You. Subsequently, as shown in FIG.
When the value data 4 is output, the data number 3 is input to the distribution count start area and the end area using the Z value data 4 as an address.

As shown in FIGS. 23 to 25, data numbers 4 to 6 are sequentially stored in the distribution count start area and the end area in the same manner.

As shown in FIG. 26, with the Z value data 0 specified by the data number 7 as an address, the data number 2 is stored in the distribution count start area and the distribution count end area.
Is entered. At this time, since a data number has already been written in the distribution count start area, no new data number is written. On the other hand, the previous data number 6 is updated to the new data number 7 in the distribution count end area. Therefore, NE of the data memory 10
The updated data number 7 is written in the XT pointer area using the data number 6 before the update as an address.

Next, as shown in FIG.
The data number 1 is input to the distribution count start area and the distribution count end area using the Z value data 0 specified by the address as an address. At this time, since a data number has already been written in the distribution count start area, no new data number is written. On the other hand, the previous data number 1 is updated to the new data number 8 in the distribution count end area. Therefore, the data memory 10
In the NEXT pointer area, the updated data number 8 is written using the data number 1 before update as an address.

Next, as shown in FIG. 28, the Z value data 5 specified by the data number 9 is read from the data memory 10. Using the Z value data 5 as an address, the data is written to the distribution count start area and the distribution count end area. At this time, since a data number has already been written in the distribution count start area, a new data number is not written. On the other hand, the previous data 4 is rewritten to a new data number 9 in the end area, and update recording is performed. I do. Then, the updated data number 9 is written in the NEXT pointer area of the data memory 10 using the data number 4 before the update as an address.

Similarly, as shown in FIGS. 29 to 35, data is read from data numbers 9 to 6 of the data memory 10, and data is written in the distribution count start area and the distribution count end area, respectively. If data has been written to the distribution count start area, the data is not rewritten and the data number before update is addressed, and the data number after update is NEX.
Writing is performed in the T pointer area. FIG. 35 shows the result of sorting only the H region in this manner.

By such a series of writing operations, Z
The data number at the time when each Z value first appears is written in the distribution count start area having value data as an address.

In the distribution count end area having the Z value data as an address, the data number when the value of each Z value appears last is stored.

Further, NEX using a data number as an address
Each time the data in the count end area is updated and stored in the T pointer area, the updated data number is sequentially written using the data number before update as an address. Therefore, when the same Z value data is output from the data memory 10a a plurality of times, a history of the data number order of the Z value data is recorded in the NEXT pointer area.

When the Z value data is read in this way, the corresponding data number is written into the distribution count start area and the end area of the distribution count memory using the read Z value as an address. Accordingly, when the data number 1, that is, the Z value data 1 specified by the address 1 is output from the data memory 10, the data number 1 is written in the distribution count start area and the end area using the Z value data 1 as an address.

Next, the case where the Z value of the H area is a value of 0 will be described with reference to FIG. First, the data number of the address 0 area of the distribution count start memory of the H area is read. In this case, since the data number of address 0 is 6, 6 is written in the sort address.

Then, the NEXT pointer of the area of the H data 6 is read, and since the NEXT pointer area indicates 7, the NEXT pointer of the data number 7 is read. In this case, since nothing is written in the NEXT pointer of 7, the data number 7 is written in the sort address, and all data corresponding to the H area 0 is written, and the data is sorted into the counter value (CNTX). The address data number 2 is set, and the process proceeds to the L area.

First, when the data number 4 of the L value specified by the data memory 10 of data number 6 is read, 6 is written in the distribution count start area 4 and 6 is written in the distribution count end area using the data number 4 as an address.

Next, when the data number 10 specified by the data number 7 is output from the L area of the data memory 10, the data of 7 is written into the distribution count start area and the distribution count end area using the data number 10 as an address. , CNTX only, the H area 0
Is completed, and the number of data items in the sort address L area is set in CNTX2.

Next, the sorting of the L area when the H area is 1 will be described with reference to FIG.

The data number 1 designated by the address 1 of the distribution count start area is written to the sort address 1,
Then, the NEXT pointer written at the address 1 is read. In this case, since the data number 8 is written in the NEXT pointer, the data number 8 is written in the sort address and the N
The data number 14 in the EXT pointer area is read. Then, the data number 14 is written in the sort address, the data number 16 of the NEXT pointer indicated by the data number 14 is written in the sort address, and nothing is written in the NEXT pointer of the address 16.
This means that all data corresponding to the H area 1 has been written to the sort address.

Then, first, the L area of data number 1 written in the sort address 1 of the H area is read. The data number 1 is written in the distribution count start area 5 using the L data 5 written in the data number 1 as an address. Then, the data number 8 written at the address 2 in the H area
Is read out. The data number 8 is written in the distribution count start area and the distribution count end area having the Z value 2 indicating the address 8 as an address. Then, the Z value 2 having the address 14 is called, and the data number 14 is written in the distribution count start area and the distribution count end area addressing the Z value 2. Since the data has already been written in the distribution count start area, it is not rewritten. In contrast, in the distribution count end area, the previous data number 8 is rewritten with a new data number 14. Therefore, the updated data number 16 is written in the NEXT pointer area of the data memory 8 using the data number 8 before the update as an address.

Then, a call is made to the distribution count start area indicated by the sort address 16. Since the data number of the distribution count start area 16 is 5, it is used as an address and the data is written to the distribution counter start area and end area. Since the data has already been written to the distribution counter start area, the data is rewritten. Instead, the previous data number 1 is written to the distribution count end area as a new data number 16. Therefore, in the NEXT pointer area of the data memory 1, the data number 1 before update is used as an address, and the data number 1 after update is used.
6 is written.

In the L area of the sort address, the data 8 written in the address 3 of the distribution count start area is stored in the address 3, and the end area is 1
4, the data number 14 written in the NEXT pointer area 8 of the data memory is read, and the data 14 is stored in the address 4 of the L area of the sort address.
Write. Then, the data number 1 written in the address 5 of the next distribution count start area is written in the sort address 5, and since the distribution count end area indicates 16, the data number 1 is written in the NEXT pointer area of the address 1 in the data memory. The data number 16 is written to the address 6 of the sort address, and the number of data 6 in the L area of the sort address is set to the counter CNTX2. Thus, the sorting process for the L region with respect to the H region 1 is completed.

FIG. 39 shows a case of sorting the L region when the number of H regions is two. The data numbers 2 and 15 are written in the H area of the sort address, the addresses 2 and 15 in the L area of the data memory of this data number are read, and the sort processing is performed in the same manner as described above, and the sort processing is performed as shown in FIG. Data is written.

FIG. 40 shows a sort process for the L region in the case of the H region 3, FIG. 41 shows a sort process for the L region in the case of the H region 4, and FIG. 43 shows the sorting process for the L region in the case of the H region 7, and FIG. 44 shows the sorting process for the H region 9 in FIG.

FIG. 45 shows the result in the case of the H area 10, that is, the result when all the sort processes have been completed.

Then, the sort processing is completed and written in ascending order of the data in order from address 1 of the sort address in the L area of the sort memory 12. That is, by sequentially reading data from address 1 in the L area of the sort address 12, data sorted in ascending order of the Z value can be read.

FIG. 7 is a block diagram showing a specific embodiment of the sorting apparatus according to the present invention.

In FIG. 7, reference numeral 52 denotes a third counter, which accesses the L area of the distribution count memory 11 and the flag 2. A first counter 53 accesses the H area of the distribution count memory 11 and the flag 1. 54
Is a multiplexer, and the first and third counters 53, 5
2 and predetermined data is selected from the data input input from the data memory 10 via the multiplexer 68 and is supplied to the first register 58.

Reference numeral 67 denotes a third register, to which data from the H area and the L area read from the distribution count memory 11 is given. Data is transferred from third register 67 to multiplexer 59. This multiplexer 59
, The output from the second address converter 66 and the outputs from the second, fourth, and fifth counters 61, 62, and 63 selected and provided by the multiplexer 64. Then, the multiplexer 59 selects predetermined data from the input data and supplies the selected data to the second register 55.

The data given to the second register 55 is transferred to a predetermined area of the data memory 10 and the sort memory 12 via the demultiplexer 69.

The first address conversion unit 56 is configured to store the data in the data memory 1 based on the data sent from the multiplexer 60.
0, H area (upper address) of the sort memory 12, L
Outputs the address of the area (lower address).

As shown in FIG. 15, the first address conversion section 56 includes registers 71, 73, 74, and 75 and a multiplexer 72, outputs data sent from the multiplexer 60 as a lower address, and By selecting the Z value address given to the register 73, the NEXT pointer address given to the register 74, and the sort address given to the register 75 by the multiplexer 72, the Z value address, the NEXT pointer address, A sort address value is selected and output.

The second address converter 66 outputs the addresses of the H area (upper address) and the L area (lower address) of the distribution count memory 11 based on the data sent from the first register 58.

As shown in FIG. 16, the second address conversion unit 66 includes registers 80, 82, 83 and a multiplexer 81, outputs data sent from the first register 58 as a lower address, and As a result, the value of the distribution count start area given to the register 82 and the value of the distribution count end area given to the register 83 are selected and output by the multiplexer 81 as upper addresses. The second address conversion unit 66 stores the data transferred from the first register 58 in the distribution counter memory 11.
H / L area designation and distribution count start address / distribution count end address are switched.

Reference numeral 57 denotes a flag detection unit which detects whether or not the distribution count memory 11 has a flag based on the output of the first register 58.

As shown in FIG. 14, the flag detecting section 57 includes flip-flop groups 153 and 16 of 0 to 255.
3, 173 and 183, and flip-flop group 1
53 indicates a flag 1L corresponding to the distribution count memory 11 in the H region, a flip-flop group 173 indicates a flag 2L corresponding to the distribution count memory 11 in the L region, and each of the distribution count memories 0 to 255 has a value. To indicate That is, the output C1 from the controller 65 is provided to the decoder 151 or 171 via the multiplexer 150, and the output from the flip-flop is determined depending on whether the flip-flop group 153 or 173 decoded by the decoder 151 or 171 is set. Selector 152 or 172 selects multiplexer 16
0 is output.

The group of flip-flops 163 corresponds to the flag 1H of the distribution count memory 11, and the group of flip-flops 183 corresponds to the flag 2H of the distribution count memory 11, and indicates whether the address value is only one or plural. That is, the output C1 from the controller 65 is
0 to the decoder 161 or 181 and whether the flip-flop group 163 or 183 decoded by the decoder 161 or 181 is set.
The output from the flip-flop is selected by the selector 162 or 182 and output via the multiplexer 160.

The H area is selected by the C1 signal from the controller 65, and the flip-flop is selected by the value of the third register 67.
, The flip-flop is set.

Reference numeral 61 denotes a second counter for accessing the Z value area of the H area of the data memory 10 and the sort address area of the sort memory 12.

Reference numeral 62 denotes a fourth counter, which accesses the sort address area in the H area of the sort memory 12.

Reference numeral 63 denotes a fifth counter, which accesses the sort address area in the L area of the sort memory 12.

Numeral 70 denotes a clip flag detecting unit, which is shown in FIG.
As shown in FIG. 7, a flip-flop group 7 of 0 to 255
03 and the flag C set in the flip-flop
L corresponds to the distribution count memory 11 in the H area, and if the flip-flop is “1”, the area corresponding to that value does not need to be processed, so that an address having this value has L
Control not to perform area sorting. That is, the input data is decoded by the decoder 702, the output of the flip-flop of the corresponding flip-flop group 703 is output from the selector 704, and if the output of the flip-flop is "1", the area corresponding to that value is output. Since it is not necessary to perform the processing, the address having this value is controlled not to perform the sort processing of the L area.

Also, the controller 15 is shown in FIGS.
The entire operation is controlled according to the flowchart shown in FIG.

This embodiment will be further described with reference to the flow charts of FIGS. First, when the operation is started, in step S10, a desired CL of the clipping flag detection unit 57 is set to set an area to be clipped.
Set the flag to "1".

Next, in step S11, the values of the second and third counters are reset, and the flow advances to step S12.
In step S12, the value of the second counter is counted up, and the process proceeds to step S13.

In step S13, the Z value is read from the Z value area of the H area of the data memory 10 indicated by the second counter, and is set in the first register. Then, the process proceeds to step S14.

In step S14, it is determined whether the value of the flag 1 indicated in the first register is "0". When the value of the flag 1 is “0”, the process proceeds to step S20, and when it is not “0”, the process proceeds to step S15.

In step S15, it is determined whether the value of the flag 1 indicated by the first register is "1". If "1", the process proceeds to step S16, and if not "1", the process proceeds to step S35.

If it is determined in step S14 that the value of the flag 1 is "0", the flow advances to step S20. In step S20, the value of the second counter is transferred to the distribution count start area of the H area indicated by the first register. Write. Then, the value of the flag 1 indicated by the first register is set to "1", and the process proceeds to step S19.

On the other hand, in step S16, the end point value is read from the distribution count end area of the H area indicated by the first register, and is set in the third register. And
Proceed to step S17. In step S17, the value of the second counter is written in the pointer area of the H area indicated by the third register, and the process proceeds to step 18.

In step S18, the value of the second counter is written to the distribution counter end area of the H area indicated by the first register. Then, the process proceeds to step S19. In step S19, the value of the second counter is compared with the number of data. If the value of the second counter is smaller than the number of data, the processing of all the H areas has not been completed. Is repeated. When the value of the second counter becomes larger than the number of data, the process proceeds to step S21.

In step S21, the value of the first counter is counted up, and the flow advances to step S22. Step S
At 22, the value of the first counter is set in the first register, and the process proceeds to step S23.

In step S23, it is determined whether the value of the CL flag indicated by the first register is "1" or whether the value of flag 1 indicated by the first register is "0". If the value of the CL flag indicated in the first register is “1” or “0”, the process proceeds to step S32, where “
If not “0” or “1”, the process proceeds to step S24.

In step S24, the end point value is read from the distribution counter start area of the H area shown in the first register, and the end point value is read from that area and set in the third register. And step S
Proceed to 25. In step S25, the count value of the fourth counter is counted up, and the process proceeds to step S26. In step S26, the value of the third register is set in the H area of the sort memory 12 indicated by the fourth counter.

Then, the process proceeds to a step S27. Step S2
7, the H of the data memory 10 indicated by the third register
The value of the pointer area of the area is read and set in the first register. Then, the process proceeds to step S28.

In step S28, it is determined whether the value of the first register is "0". If “0”, the process proceeds to step S32, and if not “0”, the process proceeds to step S29. In step S29, the value of the fourth counter is counted up, and the process proceeds to step S30.

In step S30, the value of the first register is set in the H area of the sort memory indicated by the fourth counter, and the flow advances to step S31. In step S31, the value of the pointer area in the H area of the data memory indicated by the first register is read and set in the first register. Then, the process returns to step S28. The value of the first register is "0"
This operation is repeated until the value becomes equal to, and when the value of the first register becomes "0", the flow proceeds to step S32.

Then, in step S32, it is determined whether or not the value of the fourth counter is "0". If not, the flow advances to step S33. Step S33
Then, a subroutine for sorting the L area is called.

If the value of the fourth counter is "0", the flow advances to step S34 to set the value of the first counter to 25.
It is determined whether the value is greater than 5, and if it is less than 255, the process returns to step S21 and the above-described operation is repeated. When the value of the first counter becomes greater than 255, the operation is terminated because all the operations have been completed.

Next, a subroutine for performing the sorting process for the L area will be described. When this subroutine starts, in step S50, the second and third counters are reset, and the flow advances to step S51. In step S51, the count value of the second counter is counted up, and the process proceeds to step S52.

In step S52, from the sort address area in the H area of the sort memory indicated by the second counter,
The sort address is read and set in the first register.

Subsequently, the flow advances to step S53. Step S
At 53, the data is read from the Z value area of the L area of the data memory indicated by the first register and set in the first register.

Next, in step S54, it is determined whether or not the value of the flag 2 indicated by the first register is "0". If the value is "0", the flow advances to step S60. The value of the second counter in the distribution counter start area of the indicated L area is written. Then, the value of the flag 2 indicated by the first register is set to “1”, and the process proceeds to step S59.

If it is determined in step S54 that the value of the flag 2 indicated by the value of the first register is not "0", the flow advances to step S55. In step S55, the value of the flag 2 indicated by the first register is "1". It is determined whether there is. If not "3", step S39 shown in FIG.
Proceed to. If “1”, the process proceeds to step S56, and the first
The end point value is read from the distribution counter end area in the L area of the data memory 10 indicated by the register, and is set in the third register. Then, the process proceeds to step S57.

In step S57, the value of the second counter is written in the pointer area of the L area of the data memory indicated by the third register, and the flow advances to step S58. Step S5
In step S8, the value of the second count is written to the distribution count end area of the L area indicated by the first register.
Go to 59.

In step S59, the count value of the second counter and the count value of the fourth counter are compared. If the count value of the fourth counter is larger, the process returns to step S51 and the above-described operation is repeated. When the count value of the second counter increases, the process proceeds to step S61.

In step S61, the count value of the third counter is counted up, and in step S6
Proceed to 2. In step S62, the value of the third counter is set in the first register, and the flow advances to step S63.

In step S63, it is determined whether or not the value of the flag 2 indicated by the first register is "1".
In this case, the process proceeds to step S64, and if not “1”, the process proceeds to step S72.

In step S64, the start point pointer value is read from the distribution counter start area in the L area indicated by the first register, and is set in the third register.
Proceed to 65. In step S65, the value of the fifth counter is counted up, and the process proceeds to step S66.

In step S66, the value of the third register is set in the L area of the sort memory 12 indicated by the fifth counter, and the flow advances to step S67.

In step S67, the value of the pointer area in the L area of the data memory 10 indicated by the third register is read and set in the first register, and the flow advances to step S68.

In step S68, it is determined whether the value of the first register is "0". If the value is "0", the flow advances to step S72; if not, the flow advances to step S72.
Go to 69.

In step S69, the value of the fifth counter is counted up, and the flow advances to step S70. In step S70, the sort memory 12 indicated by the fifth counter
The value of the first register is set to the sort address of the L area of FIG.

Next, in step S71, the pointer area of the L area of the data memory 10 indicated by the first register is read and set in the first register. In step S68, until the value of the first register becomes "0". The above operation is repeated. When the value of the first register becomes “0” in step S68, the process proceeds to step S72.

When the value of the third counter reaches 255 in step S72, this subroutine operation ends, and the flow returns to step S34.

On the other hand, in step S55, if the value of the flag 2 indicated by the first register is not "3",
The process proceeds to step S39 shown in FIG.

In step S39, the starting point pointer value is read from the distribution count start area of the L area indicated by the first register, set in the third register, and the flow advances to step S40.

In step S40, the value of the second counter is written in the pointer area of the L area of the data memory indicated by the third register, and the flow advances to step S41. Step S
At 41, the value of the second counter is written to the distribution count end area of the L area indicated by the first register, and step S4
Proceed to 2.

In step S42, the value of the flag 2 indicated by the first register is set to "2", and the process returns to step S59 in FIG.

On the other hand, if the value of the flag 1 indicated by the first register is not "1" in step S15 in FIG. 8, the process proceeds to step S35 in FIG.

In step S35, the start point pointer value is read from the distribution count start area of the H area indicated by the first register, set in the third register, and the flow advances to step S36.

In step S36, the value of the second counter is written in the pointer area of the H area of the data memory indicated by the third register, and the flow advances to step S37. In step S37, the value of the second counter is written into the distribution count end area of the H area indicated by the first register, and
Proceed to 38.

Then, in step S38, after the value of the flag 2 indicated by the first register is set to "2", the flow returns to step S19 in FIG.

By performing the processing as described above, the aforementioned FIG.
As shown in FIG. 45, data is sequentially written to the data memory 10 and the sort memory 12, and the data is sorted.

FIGS. 49 and 50 show examples in which clipping is performed. In this example, it is assumed that the Z value of the H area of the data memory 10 is 0, 1, or 2 as a clipping target. For this reason, the flip-flop group 70 of the clip flag detection unit 70
As the value of the CL flag of 3, the 0th, 1st and 2nd bits are
Set to 1 ".

In the sorting process for the L area, the Z
Since the values are not sorted for the values of 0, 1, and 2, FIG.
As shown in FIG. 9, polygons 6, 7, 16, 1, 8, 14,
The addresses 2 and 15 are not included in the sort address area of the L area. Therefore, as shown in FIG.
1, 2 polygons are clipped.

FIG. 51 is a schematic diagram showing a state of picking and clipping. FIG. 51A is a schematic diagram showing a state where picking or clipping is not performed.

FIG. 51 (b) shows H in front of the screen.
The Z value “0” of the area and the H area “5” behind the visibility limit
FIG. 6 is a schematic diagram showing an example in which a polygon is clipped.
When performing this clipping, the 0th and 5th bits may be set to “1” as the value of the CL flag of the flip-flop group 703 of the clip flag detection unit 70.

FIG. 51 (c) shows that the Z value of the H region is
It is a schematic diagram which shows the example which picked the polygon with respect to 2 "," 3 ". When this picking is performed, 0,1,4,4 is set as the value of the CL flag of the flip-flop group 703 of the clip flag detection part 70. The 5th bit is
Set it to 1 ".

FIG. 51D shows that the Z value of the H area is “2”, “2”.
FIG. 9 is a schematic diagram showing an example in which a polygon is clipped to 3 ″. When this clipping is performed, the CL of the flip-flop group 703 of the clip flag detection unit 70 is set.
As the value of the flag, the second and third bits may be set to “1”.

In the above-described embodiment, the case where the reference value data, that is, the Z-axis data is divided into two regions of the H region and the L region and the sorting process is performed.
If the axis data is divided into two or more areas and the processing is performed, the degree of parallelism increases, and the sorting processing can be performed at high speed. For example, H, L
Dividing into three regions of H, M, and L increases the degree of parallelism and increases the speed of the sorting process, compared to a system that divides only the region into two.

Next, an embodiment in which the Z-axis data is divided into three regions of H, M, and L and the sorting process is performed will be described.

In the clipping process in this embodiment, as shown in FIG. 60, by dividing into H, M, and L sections, it is possible to perform small clipping using the H and M sections with a small number of processes. is there.

FIG. 60A shows the method of this embodiment.
(B) is a view obtained by removing the M region from the (a) method,
Compared with (a), fine clipping cannot be performed, and wasteful processing is performed to perform sorting of an area that requires clipping, thereby reducing the speed. (C) corresponds to the case where there is no H area in the method (a). In this case, fine clipping is possible, but the clipping flags of all the H areas are required. For example, if the H area has 10 bits, 1024 flags are required. On the other hand, when divided into 5 bits for each of the H and M areas, 32 + 3
Only 2 × 2 (both ends of the clipping area) is required.

Also, it is necessary to determine whether or not to perform clipping processing on all the H areas, and the sorting processing speed is reduced.

Next, the sorting apparatus of this embodiment will be described. FIG. 52 is a block diagram showing the overall configuration of the sorting apparatus.

This sorting device includes a data memory 10a, a sort circuit 100, and a distribution count memory 11a, as in the above-described embodiment.

The data memory 10a has a storage area for storing 1 to N Z-value data specified by the data number pointer. As shown in FIG. 57, the storage area is largely divided into an H area, an M area, and an L area. Each of these areas is composed of a Z-value area for storing Z-value data and a NEXT for storing an associated NEXT address.
It is divided into a pointer area, an H area stores upper data of the reference value data, an M area stores middle data of the reference value data, and an L area stores lower data of the reference value data. Here, the Z value data is 16 as shown in FIG.
If it is composed of bit data, in the H area,
The upper 5 bits of the reference value data, the middle 5 bits of data in the M area, and the lower 6 bits of data in the L area.

As shown in FIG. 57, the sort memory 12a has a sort address area for storing the sort result.
This sort memory 12a also has the same H as the data memory 10a.
The area is divided into an area, an M area, and an L area.

The NEXT pointer area of the data memory 10a stores a pointer value indicating the address of the data having the same value, and the sort address area of the sort memory 12a stores the address value of the data having the smaller Z value in the order of the address. Is stored.

The sort circuit 100 includes a data memory 10a
Count memory 11 for the Z value input from
Using a as a working, the addresses sorted in the H, M, and L areas of the Z value are written in the sort memory 12a in the sort address areas of the H, M, and L areas, respectively.

As shown in FIG. 58, the distribution count memory 11a is divided into an H area, an M area, and an L area in the same manner as the data memory 10a, and this area is divided into a distribution count start area and a distribution count end area. And divided into In this embodiment, the distribution count memory 11a stores 0 bits corresponding to the 5-bit, 5-bit, and 6-bit data stored in the respective Z value areas of the data memory 10a.
Has an address from 0 to 31 and an address from 0 to 63,
The distribution count start area has the head address of the data of the address value. The distribution count end area has the end point address of the address value.

The clip control circuit 16 specifies a Z value area to be deleted in advance to perform the above-described 3D clipping or picking processing, and sends the specified area to the H / M sort processing circuits 15a and 15b.

The H / M sort processing circuits 15a and 15b
It is determined whether or not the sorted area is subject to clipping processing, and control is performed so that the L sorting processing circuit 18 does not perform the sorting processing on the targeted area.

H sort processing circuit 1 in this embodiment
5a, M sort processing circuit 15b, L sort processing circuit 18
Performs the same sort processing as in the above-described embodiment.

Next, the sorting operation of this embodiment will be described. FIG. 53 is a flowchart showing this sort operation.

When a plurality of reference axis data (Z-value data) to be sorted are input from the image information supply device 5, data numbers 1 to N in the input order are assigned, and an address is specified by a data number pointer. 1 to N of H
The upper 5 bits of the reference value data are
In the M area of N, the middle 5 bit data of the reference value data is 1
The lower 6 bits of the reference value data are sequentially stored in the L areas of N to (N) (step S100).

When the storage of a plurality of Z-value data to be sorted in the data memory 10a is completed in this way, the H area is sorted (step S10).
1). The sorting of the H area is performed in the data memory 10a.
, The Z value data stored in the H area are sequentially read out in the order of data numbers 1 to N, and output to the distribution count start area and the end area of the distribution count memory 11a.

In this embodiment, the reading of the Z value data is performed by sequentially outputting the data numbers in the order of 1 to N as the data number pointer read address. When the address is specified by the data number, the Z value data is read from the H area of the specified Z value data to the distribution count start area and the end area of the distribution count memory 11a.

The distribution count start area and the end area of the distribution count memory 11a have areas corresponding to all possible values of the Z value data on a one-to-one basis.

As in this embodiment, when the H bit and the M bit of the Z value data are composed of 5 bits,
31, 32 values of 0, 1, 2,... Also,
When the L bits of the Z value data are composed of 6 bits, a total of 64 values of 0, 1, 2, ... 63 can be taken.

Therefore, H of distribution count memory 11a,
The distribution count start and end areas of the M area are 0,
32 storage areas designated by respective addresses of 1, 2,... 31 are provided, respectively.
The L count distribution start area and the end area are provided with 64 storage areas designated by respective addresses 0, 1, 2,... 63, respectively.

The data number of the Z value data output from the data memory 10a is written in the distribution count start area and the end area of the distribution count memory 11a.
In this embodiment, the data numbers are represented by 1 to N, and the maximum value is N.

When the Z value is input from the data memory 10a to the distribution count start area and the end area,
These distribution count start area and end area write the data number of the Z value into the storage area designated by the corresponding address pointer.

As in the above-described embodiment, in this embodiment, data writing is performed as follows. That is, when the Z value data of the data number designated by the data number pointer is output from the data memory 10a, the Z value data is set to the address pointer, and the set Z value data is output from the address pointer. It is output as a write address. Then, the data number (data number corresponding to the Z value) specified by the data number pointer is written into the distribution count start area and the end area specified by the write address.

Here, once the data number is stored in the distribution count start area, the data memory 10a
, The new data number is not overwritten even if new Z-value data of the same value is sequentially output. On the other hand, even if a data number is once stored in the distribution count end area, when the same Z value is output from the data memory 10 next time, the data number of the Z value is newly updated and stored. It is configured as follows.

In the distribution count start area, a data number when the Z value first appears is stored. On the other hand, in the distribution count end area, the data number at the time when each Z value appears last is stored.

For this reason, when the same Z value is output from the data memory 10a only once at the same address in the distribution count start area and the end area, the same data number is written. When the Z value is output a plurality of times, different data numbers will be finally stored.

Therefore, when the value of the distribution count end area of the distribution count memory 11a is updated and recorded a plurality of times, if it is known how this update is performed, the reference value data is sorted in ascending or descending order. The sequence of the data numbers of each reference value data at the time is determined.

Therefore, in the data memory 10a, there is provided a NEXT pointer area in which addresses are specified in the order of 0 to N based on the data number to be output as a new pointer.

When the contents of the distribution count end area are updated and recorded, the data number before the update recording is set in the address pointer, and the address of the NEXT pointer area is specified. Then, the updated new data number is written in the designated NEXT pointer area.

When the distribution count end area is updated and recorded in this manner, the update history is sequentially written to the pointer area in the data memory.

As described above, according to this embodiment,
When the Z-value data is output from the data memory 10 in the order of the data numbers, the output Z-value data is used as a write address, and the data numbers are written to the distribution count start area and the distribution count end area. NEX of data memory 10 from count end area
Data transfer writing to the T pointer area is performed.

When such data transfer is started, H
The sort circuit 15a performs the following transfer control.

First, the data number stored in the distribution count end area is set in the address generation circuit 13. Next, the data number of the distribution count start area having a predetermined correspondence with the designated address is written in the NEXT pointer area addressed by the address generation circuit 13.

The writing of such data numbers is slightly different between the case where data is sorted in ascending order and the case where data is sorted in descending order. Here, the case where data is sorted in ascending order will be described as an example.

For example, when a data number is stored in the distribution count end area specified by the address 0,
First, the data number stored at address 0 is set in the address pointer.

Then, the data number is read from the distribution count start area specified by the address 1, and this data number is written to the NEXT pointer area of the data memory 10 specified by the address pointer.

At this time, if the data number is not stored in the distribution count start area specified by the address 1, the data number is read from the storage area specified by the address 2 and the NEXT pointer area of the data memory 10a is read. Write to. If no data number is stored in the distribution count start area designated by address 2, the address is sequentially incremented in the same manner as address 3, address 4,... Until data is found.

When the data number is read from the storage area specified by the address K, this data number is stored in the NE of the data memory 10a specified by the address pointer.
It is written to the XT pointer area.

When such reading and writing are completed, the data number is read from the distribution count end area designated by the address K, and the data number is set as the write address in the same manner as in the previous time.
Data is written to the EXT pointer area.

The device in this embodiment repeatedly writes data in the NEXT pointer area for recording such a chain data number. When such a series of write operations is completed, the data memory 10a
In the storage area of the NEXT pointer area, data numbers are stored so as to be linked in ascending order of the H area of the reference value data, that is, the data of the upper 5 bits.

When the sorting of the upper 5 bits of the data memory 10a, that is, the H area is completed, the sorting result is stored in the H area of the sort memory 12a as a sort address.

Then, in this embodiment, it is determined whether or not there is an area designated by the clip control circuit 16 (step S102). For example, sorting processing is performed in ascending order in a range from 0 to N on the H side, and the H
The data at address 0 on the side is read, and it is determined whether or not the data is clipped. When clipping is performed, the middle 5 bits of the data, that is, sorting of the M area is not performed, and processing corresponding to the Z value of the next H area is performed.

The address read from the sort address area in the H area of the sort memory 12a is the data memory 1
This corresponds to a data number of 0. Now, if data at address 0 is read from the H area and that area is not to be clipped, a sorting process for the M area is performed (step S103). Then, similar to the H-side sorting process described above, the M-side sorting process is performed. It is determined whether all the data have been sorted (step S103), and the M-side sorting is repeated from the processing determination as to whether clipping is necessary until all the data is sorted.

Subsequently, in this embodiment, it is determined whether or not there is an area designated by the clip control circuit 16 (step S105). For example, sorting processing is performed in ascending order in the range of 0 to N on the M side, and the M
The data at address 0 on the side is read, and it is determined whether or not the data is clipped. When clipping is performed, the lower 6 bits of the data, that is, sorting of the L area is not performed, and processing corresponding to the Z value of the next M area is performed.

Thereafter, in the L-side sorting circuit 18, the Z-value data stored in the L area of the data memory 10 is read out, and the data is stored in the distribution count start area and the distribution count area of the distribution count memory 11a. It is stored in the end area, and
, The NEXT pointer area of the L area. This operation is performed in the above-described H region, M
This is performed in the same manner as the area sorting process. That is, the processing of the H area and the M area uses the H area and the M area of the data memory 10a, the H area and the M area of the distribution count start area and the distribution count end area of the distribution count memory 11a, and transfers the data to the NEXT pointer area of the data memory 10. The writing of the chain data is performed. On the other hand, regarding the data in the L area, the Z in the L area in the data memory 10a is
The value data is read, the data numbers are stored in the distribution count start area and the distribution count end area of the L area of the distribution count memory 11a according to the data, and the chain data is written in the NEXT pointer area of the L area of the data memory 10. Thus, the sorting process is performed.

That is, in the present invention, sorting processing is first performed on the H region, that is, the upper 5 bits of data, and it is determined whether or not the data needs to be clipped at the stage when the sorting processing has been performed.
For those whose data does not need to be clipped,
The next M-side sorting process is performed. Further, it is determined whether or not the data needs to be clipped at the stage when the sorting process has been performed, and the next L-side sorting process is performed on data whose data does not need to be clipped. In the L-side sorting process, the same processing as that for the H-side area and the M-side area is performed, and the sorting is completed. Then, the sorted result is similarly written into the sort address area of the L area of the sort memory 12a (step S107), and it is determined whether or not all the data have been sorted (step S1).
08), L-side sorting is repeated from the processing determination of whether clipping is necessary until all data is sorted.

When all sorting is completed, the operation is completed.

Next, a case will be described as an example in which twelve Z value data output from the image information supply device 5 are sorted in ascending order using such a sorting circuit.

In this embodiment, since 12 pieces of Z-value data are to be sorted, the data memory 10 has 1
Z value area and L value of H area specified by data numbers
What is necessary is just to form so that it may have a Z value area | region. Also,
The Z value data is as described above, that is, 5 bits in the H area,
The M area is composed of 5 bits, and the L area is composed of 6 bits.

First, from the image information supply device 5 to the data memory 10a, the upper 5 bits, that is, the data of the H value,
When input is performed in the order of 1, 2, 4, 5, 3, 0, 0, 7, 9, 1, 2, 1, the input Z value data is sequentially 1, 2,.
.. Are written in the storage area of the H area of the data memory 10a for addressing the data numbers of 3.

The middle 5 bits, that is, the data of M value is 1,
2, 3, 4, 6, 7, 8, 2, 3, 1, 5, 6 and the lower 6 bits, that is, data in the L area is 5, 6, 3, 1, 5,.
4, 5, 1, 1, 2, 7, 5 in that order, the input Z value data is sequentially stored in 1, 2, 3, 4, 5,... Of the M area and the L area of the data memory 10a. The data number will be written to the storage area for addressing.

When the Z value data is written in the H, M, and L areas in the data memory 10a in this manner, the Z value data is sorted using the data number instead of the Z value data itself.

By doing so, even if the number of digits of the Z-value data to be sorted is large, sorting of the Z-value data can be performed at high speed with a simple circuit.

In this embodiment, when the Z value is written in the Z value data memory 10a, the Z value is sequentially read from the data memory 10a in the order of the data number.

When the Z-value data is written in the data memory 10a, the data is sequentially read from the data memory 10a in the order of the data numbers. First, only the H area is read out, and the H area is sorted as shown in FIGS.

When the Z value data is read in this way, the corresponding data number is written to the distribution count start area and the end area of the distribution count memory 11a using the read Z value as an address. First, FIG.
As shown in (1), when the data number 1, that is, the Z value data 1 specified by the address 1 is first output from the data memory 10a, the Z number data 1 is used as an address in the distribution count start area and the end area. 1 is written.

The sorting process for the H area is continued, and the data number 6 is input to the distribution count start area and the distribution count end area using the Z value data 0 specified by the data number 6 shown in FIG. 62 as an address. Subsequently, when the Z value data 0 specified by the data number 7 is output, the data number 7 is input to the distribution count start area and the end area using the Z value data 0 as an address. At this time, since a data number has already been written in the distribution count start area, no new data number is written. On the other hand, the previous data number 6 is updated to the new data number 7 in the distribution count end area. Therefore, the updated data number 7 is written in the NEXT pointer area of the data memory 10a using the data number 6 before the update as an address.

Next, as shown in FIG. 63, Z value data 1 specified by data number 8 is read from data memory 10a. The data is written to the distribution count start area and the distribution count end area using the Z value data 1 as an address. At this time, since a data number has already been written in the distribution count start area, a new data number is not written. On the other hand, the previous data 1 is rewritten to a new data number 8 in the end area, and update recording is performed. I do. Then, an updated data number 8 is written in the NEXT pointer area of the data memory 10a using the data number 1 before the update as an address.

In the same manner, data is read from data numbers 9 to 12 of the data memory 10a, and data is written into the distribution count start area and the distribution count end area, respectively. If it is, the data is not rewritten and the number of the data before update is addressed,
The updated data number is written into the NEXT pointer area. FIG. 64 shows the result of sorting only the H region.
Shown in

By such a series of writing operations, Z
The data number at the time when each Z value first appears is written in the distribution count start area having value data as an address.

In the distribution count end area having the Z value data as an address, the data number when the value of each Z value appears last is stored.

Further, NEX using a data number as an address
Each time the data in the count end area is updated and stored in the T pointer area, the updated data number is sequentially written using the data number before update as an address. Therefore, when the same Z value data is output from the data memory 10a a plurality of times, a history of the data number order of the Z value data is recorded in the NEXT pointer area.

Referring to FIG. 66, a description will be given of a case where the Z value of the H area is 0 and the M area is sorted. First, the data number of the area at the address 0 of the distribution count start area of the distribution count memory 11a in the H area is read. In this case, since the data number of address 0 is 6, 6 is written in the sort address.

Then, the NEXT pointer of the area of the H data 6 is read, and since the NEXT pointer area indicates 7, the NEXT pointer of the data number 7 is read. In this case, since nothing is written in the NEXT pointer of 7, the data number 7 is written in the sort address, and all data corresponding to the H area 0 is written, and the data is sorted into the counter value (CNTX). The number of data 2 in the H area of the address is set, and the process proceeds to the M area.

First, when the M-valued Z-value data 7 specified by the data memory 10a of the data number 6 is read, the distribution count memory 11 having the Z-valued data 7 as an address is used.
6 is written in the distribution count start area and 6 is written in the distribution count end area as addresses of the M area a, and the M value Z specified by the data memory 10a of data number 7
When the value data 8 is read, 7 is written to the distribution count start area and 7 is written to the distribution count end area as addresses of the M area of the distribution count memory 11a having the Z value data 8 as an address.

Next, data number 6 specified by data number 7 is output from the M area of the sort address. Finish sorting the M area for H area 0 and M area 7
Set the number of data 7 in the sort address M area to X2,
Move on to processing of L region.

When the Z value data 4 specified by the data number 6 is read as the sorting of the L area, the Z value data 4 is used as the address of the L area of the distribution count memory 11a, and 6 is distributed to the distribution count start area. 6 is written in the end area, the data number 6 is written in the sort address L area, and all the data in the H area 0 and the M area 7 have been written, and the number of data 1 in the sort address L area is set in CNTX3. . Next, when the data number 7 indicated by the data number 8 is output from the M area of the sort address, since nothing is written in the NEXT pointer, the M area is sorted for the H area 0 and the M area 8. When the processing is completed, the number of data 1 in the sort address M area is set in CNTX2, and the process proceeds to the L area.

Subsequently, as shown in FIG.
When the Z value data 5 specified by the data number 7 is read as the sort of the L region of the M region 8, the Z value data 5 is distributed to the distribution count start region as an address of the L region of the distribution count memory 11a. 7 is written in the count end area, data number 7 is written in the sort address L area, and all the data in the H area 0 and M area 8 are written, and the number of data 2 in the sort address L area is set in CNTX3. I do.

Next, the sorting of the M area when the H area is 1 will be described with reference to FIG.

The data number 1 designated by the address 1 of the distribution count start area of the H area is written to the sort address 1 and the NE written at the address 1 is written.
Read the XT pointer. In this case, since 10 is written in the NEXT pointer, the address of 10 is written in the sort address, and the data number 12 in the NEXT pointer area written in the address 10 is read.
Then, the data number 12 is written in the sort address. Since nothing is written in the NEXT pointer of the address, all data corresponding to the H area 1 is written to the sort address, and the number of data in the sort address H area 3 is set in CNTX. Move on to processing.

Then, first, the M area of data number 1 written at address 1 of the sort address H area is read. Data number 1 is written in distribution count start area 1 having M data 1 written in data number 1 as an address. Then, the L area of data number 10 written at address 2 of the sort address H area is read. The data number 8 is stored in the distribution count start area and the distribution count end area having the Z value 1 indicating the address 10 as the address.
Write. Since data has already been written in the distribution count start area, the data is not rewritten. In contrast, in the distribution count end area, the previous data number 1 is rewritten with a new data number 10. Therefore, the updated data number 10 is written in the NEXT pointer area of the data memory 10a using the data number 1 before the update as an address.

Similarly, an L area sorting process is performed.

Subsequently, as shown in FIG. 68, the data value of the M area indicated by the sort address 12 is called. Since the data number of the data value in the M area is 6, the data number is used as an address and the data is written into the distribution counter start area and end area.

In the M area of the sort address, data 12 written at address 1 of the distribution count start area at address 1 and at the end area 12 are shown, so that 1 is set in the counter CNTX2. ,
The sort processing of the M area with respect to the H area 1 ends. Similarly, an L area sorting process is performed. FIG. 69 shows the result in the case of the H area 10, that is, the result after all the sort processes have been completed. Then, the sort processing is completed and written in ascending order of data in order from address 1 of the sort address in the L area of the sort memory 12a. That is, by sequentially reading data from address 1 in the L area of the sort memory 12, the data sorted in ascending order of the Z value can be read.

FIG. 54 is a block diagram showing a specific embodiment of the sorting apparatus according to the second embodiment.

In FIG. 54, reference numeral 52 denotes a third counter, which accesses the L area of the distribution count memory 11a and the flag 2. A first counter 53 accesses the H area of the distribution count memory 11a and the flag 1.
Reference numeral 7 denotes a sixth counter, which accesses the M area of the distribution count memory 11a and the flag 3. Reference numeral 54 denotes a multiplexer, which selects predetermined data from data input from the first and third counters 53 and 52 and the data memory 10a via the multiplexer 68, and supplies the selected data to the first register 58.

Reference numeral 67 denotes a third register to which data from the H, M, and L areas read from the distribution count memory 11a is given. Data is transferred from third register 67 to multiplexer 59. The output from the second address conversion unit 66 and the second signal selected and provided by the multiplexer 64 are applied to the multiplexer 59.
Outputs from the fourth and fifth counters 61, 62, 63 are provided. Then, the multiplexer 59 selects predetermined data from the input data, and selects the predetermined data from the second register 55.
Give to.

The data provided to the second register 55 is transferred to predetermined areas of the data memory 10a and the sort memory 12 via the demultiplexer 69.

The first address conversion section 56 performs data memory 1 conversion based on the data sent from the
0a and the H area (upper address) of the sort memory 12;
The address of the M area (middle address) and the address of the L area (lower address) are output.

The first address converter 56 has the same structure as that of the first embodiment, and includes registers 71, 73, 74 and 75 and a multiplexer 72 as shown in FIG. The received data is output as the lower address, and the Z-address value given to the register 73 and the register 74
NEXT pointer address value given to register 7, register 7
5 to the multiplexer 72.
, The Z value address, the NEXT pointer address, and the sort address value are selected and output as the upper address.

The second address conversion section 66 determines the H area (upper address), M area (middle address), and L area (lower address) of the distribution count memory 11a based on the data sent from the first register 58. Output address.

As shown in FIG. 16, the second address conversion section 66 includes registers 80 and 8 as in the above-described embodiment.
2 and 83 and a multiplexer 81, and the first register 5
8 is output as the lower address, and the controller 55 selects and outputs the value of the distribution count start area given to the register 82 and the value of the distribution count end area given to the register 83 by the multiplexer 81 as the upper address. I do. The second address conversion unit 66 uses the data transferred from the first register 58 as the lower address of the distribution counter memory 11 to
M / L area designation and distribution count start address / distribution count end address switching are performed.

Reference numeral 57 denotes a flag detection unit which detects whether or not the distribution count memory 11a has a flag based on the output of the first register 58.

As shown in FIG. 55, the flag detecting section 57 includes flip-flop groups 153 and 16 of 0 to 31.
3, 173 and 183, two flip-flop groups 193 and 203 from 0 to 63, and two flip-flag groups.
The flip-flop group 173 corresponds to the flag 3L in the M area of the distribution count memory 11a, the flip-flop group 193 corresponds to the flag 2L in the L area of the distribution count memory 11a, 1 to 31 or 0 to 63, respectively.
Indicates whether 1a has a value. That is, the controller 65
The output C1 is supplied to the decoder 151 or 171 via the multiplexer 150,
Flip-flop group 1 decoded in 1 or 191
Depending on whether 53, 173 or 193 is set,
The output from the flip-flop is the selector 152, 1
It is selected at 72 or 192 and output via the multiplexer 160.

The flip-flop group 163 corresponds to the flag 1H of the distribution count memory 11a, the flip-flop group 183 corresponds to the flag 2H of the distribution count memory 11a,
The flip-flop group 183 includes the distribution count memory 11a.
Corresponding to the flag 3H, and the address value is only one,
Indicates multiple. That is, the output C1 from the controller 65 is supplied to the decoders 161 and 181 via the multiplexer 150.
Or 201 to the decoder 161, 181 or 2
01 flip-flop group 163, 1
Depending on whether 83 or 203 is set, the output from the flip-flop is selected by the selector 162, 182 or 202 and output via the multiplexer 160.

The H region is selected by the C1 signal from the controller 65, and the flip-flop is selected by the value of the third register 67.
, The flip-flop is set.

Reference numeral 61 denotes a second counter for accessing the Z value area of the H area of the data memory 10a and the sort address area of the sort memory 12.

Reference numeral 62 denotes a fourth counter, which accesses the sort address area in the H area of the sort memory 12.

Reference numeral 63 denotes a fifth counter, which accesses the sort address area in the L area of the sort memory 12.

Reference numeral 72 denotes a seventh counter, which accesses the sort address area of the M area of the sort memory 12.

Reference numeral 70 denotes a clip flag detection unit,
As shown in FIG.
3 and the flag HC set in the flip-flop
L corresponds to the distribution count memory 11a in the H area, and if the flip-flop is "1", the area corresponding to that value does not need to be processed. Control not to perform. The flag MCL corresponds to the distribution count memory 11a in the M area, and if the flip-flop is "1", the area corresponding to that value does not need to be processed. Control not to perform sort processing. That is, the input data is decoded by the decoder 702, the output of the flip-flop of the corresponding flip-flop group 703 is output from the selector 704, and if the output of the flip-flop is "1", the area corresponding to that value is output. Since it is not necessary to perform the processing, the address having this value is controlled not to perform the sort processing of the L area.

[0268]

According to the present invention, the sorting process is performed by dividing the reference value data into two or more data groups. That is, distribution count sorting is performed on the reference value data on the upper side. By performing a distribution sort of only the lower-order reference value data with respect to the data group of the same reference value data from the smaller reference value data address, and sequentially writing the sorted data to the sort memory address, Sorting can be performed at high speed even for data having a large bit length.

Further, according to the present invention, after the sorting of the upper-order reference value data is completed, the sorting of the lower-order reference value data is omitted for the upper-order reference value data of the address corresponding to clipping. Can be configured,
3D clipping and 3D picking that exclude polygons of arbitrary reference value data can be performed without performing extra data transfer, and 3D clipping, 3D picking, and the like can be performed at high speed. The reference value data is divided into upper digits and lower digits, and the sorting process is performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a three-dimensional image processing apparatus to which the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of the sorting apparatus of the present invention.

FIG. 3 is a flowchart showing a sorting processing operation according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating the concept of a sorting process.

FIG. 5 is a schematic diagram showing an address area of a data memory and a sort memory used in the first embodiment of the present invention.

FIG. 6 is a schematic diagram showing an address area of a distribution count memory used in the first embodiment of the present invention.

FIG. 7 is a block diagram showing a specific configuration example of the sorting apparatus according to the first embodiment of the present invention.

FIG. 8 is a flowchart for explaining the operation of the sorting apparatus of the present invention shown in FIG. 7;

FIG. 9 is a flowchart for explaining the operation of the sorting apparatus of the present invention shown in FIG. 7;

10 is a flowchart illustrating the operation of the sorting apparatus of the present invention shown in FIG.

11 is a flowchart illustrating the operation of the sorting apparatus of the present invention shown in FIG.

FIG. 12 is a flowchart illustrating the operation of the sorting apparatus of the present invention shown in FIG. 7;

FIG. 13 is a flowchart illustrating the operation of the sorting apparatus of the present invention shown in FIG. 7;

FIG. 14 is a specific circuit diagram of a flag detection unit in FIG. 7;

FIG. 15 is a specific circuit diagram of a first address conversion unit in FIG. 7;

FIG. 16 is a specific circuit diagram of a second address conversion unit in FIG. 7;

FIG. 17 is a specific circuit diagram of the clip flag detection unit in FIG. 7;

FIG. 18 is a schematic diagram illustrating an example of sort data.

FIG. 19 is a data memory in a case where the number of data is 16 with an H-side sort data length of 8 bits and an L-side sort data length of 8 bits;
It is a schematic diagram which shows the storage state of a distribution count memory and a sort memory.

FIG. 20 shows a data memory and distribution count memory when the data stored at the address 1 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 21 shows a data memory and a distribution count memory in the case where the data stored at address 2 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 22 shows a data memory and distribution count memory when the data stored at address 3 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 23 shows a data memory and a distribution count memory when the data stored at address 4 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 24 shows a data memory and a distribution count memory in the case where the data stored at address 5 of the data memory in the H area has an H-side sort data length of 8 bits and an L-side sort data length of 8 bits and a data number of 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 25 shows a data memory and distribution count memory when the data stored at the address 6 of the data memory in the H area is processed when the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 26 shows a data memory and a distribution count memory when the data stored at address 7 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 27 shows a data memory and a distribution count memory when the data stored at address 8 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 28 shows a data memory and distribution count memory when the data stored at address 9 of the data memory in the H area is processed when the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits is 16. FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 29 shows a data memory and a distribution count memory when the data stored at address 10 of the data memory in the H area is processed when the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 30 shows a data memory and distribution count memory in the case where the number of data of the H-side sort data length of 8 bits and the L-side sort data length of 8 bits is 16 when data stored at address 11 of the data memory in the H area is processed. FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 31 shows a data memory and distribution count memory when the data stored at the address 12 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 32 shows a data memory and distribution count memory when the data stored at address 13 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 33 shows a data memory and a distribution count memory when the data stored at the address 14 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 34 shows a data memory and distribution count memory when the data stored at the address 15 of the data memory in the H area is H-side sorted data length 8 bits and L-side sorted data length 8 bits and the number of data is 16; FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 35 shows a data memory and a distribution count memory when the data stored at address 16 of the data memory in the H area has a data number of 16 for the H-side sorted data length of 8 bits and the L-side sorted data length of 8 bits. FIG. 4 is a schematic diagram illustrating a storage state of a sort memory.

FIG. 36 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “0” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 37 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “1” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 38 shows a data memory in a case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “2” in the H area is sorted in the L area. FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 39 is a data memory in the case where the number of data of the H-side sort data length is 8 bits and the L-side sort data length is 8 bits when only data having a value of “3” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 40 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “4” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 41 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “5” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 42 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “6” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 43 is a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “7” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 44 is a data memory in the case where the number of data of the H-side sort data length is 8 bits and the L-side sort data length is 8 bits when only data having a value of “9” in the H area is sorted in the L area; FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 45 shows a data memory in the case where the number of data of the H-side sorted data length is 8 bits and the L-side sorted data length is 8 bits when only data having a value of “10” in the H area is sorted in the L area. FIG. 4 is a schematic diagram showing storage states of a distribution count memory and a sort memory.

FIG. 46 is a schematic diagram showing clipping in the Z direction.

FIG. 47 is a schematic diagram showing picking in the Z direction.

FIG. 48 is a schematic view showing clipping in the Z direction.

FIG. 49 is a schematic diagram showing storage states of a data memory, a distribution count memory, and a sort memory in an example in which values having “0”, “1”, and “2” in the H area are sorted by clipping. .

FIG. 50 is a schematic diagram showing an example in which clipping and sorting are performed on values having values of “0”, “1”, and “2” in an H region.

FIG. 51 is a schematic diagram showing an example of sorting by performing clipping or picking.

FIG. 52 is a block diagram showing a second embodiment of the sorting apparatus of the present invention.

FIG. 53 is a flowchart showing a sorting processing operation according to the second embodiment of the present invention.

FIG. 54 is a block diagram showing a specific configuration example of a sorting device according to a second embodiment of the present invention.

FIG. 55 is a specific circuit diagram of the flag detection unit in FIG. 54.

FIG. 56 is a specific circuit diagram of a clip flag detection unit in FIG. 54;

FIG. 57 is a schematic diagram showing address areas of a data memory and a sort memory used in the present invention.

FIG. 58 is a schematic diagram showing an address area of a distribution count memory used in the present invention.

FIG. 59 is a schematic diagram showing an example of sort data.

FIG. 60 is a schematic diagram showing a concept of a sorting process.

FIG. 61 shows data of an H-side sorted data length of 5 bits, an M-side sorted data length of 5 bits, and an L-side sorted data length of 6 bits when only data stored at address 1 of the data memory in the H area is sorted. It is a schematic diagram which shows the storage state of the data memory in case of Formula 16, a distribution count memory, and a sort memory.

FIG. 62 shows an H-side sorted data length of 5 bits, an M-side sorted data length of 5 bits, and an L-side sorted data length of 6 bits when only data stored at address 6 of the data memory in the H area is sorted. It is a schematic diagram which shows the storage state of the data memory in case of Formula 16, a distribution count memory, and a sort memory.

FIG. 63 shows an H-side sorted data length of 5 bits, an M-side sorted data length of 5 bits, and an L-side sorted data length of 6 bits when only data stored at address 8 of the H area data memory is sorted. It is a schematic diagram which shows the storage state of the data memory in case of Formula 16, a distribution count memory, and a sort memory.

FIG. 64 shows a data memory, a distribution count memory, and a sort memory in a case where the number of data is 16 with an H-side sort data length of 5 bits, an M-side sort data length of 5 bits, and an L-side sort data length of 6 bits when only the H area is sorted. It is a schematic diagram which shows the storage state of.

FIG. 65 shows an H-side sorted data length of 5 bits, an M-side sorted data length of 5 bits, and an L-side sorted data length of 6 when only data having a value of “0” in the H area are sorted in the M and L areas. It is a schematic diagram which shows the storage state of the data memory, the distribution count memory, and the sort memory when the number of bit data is 16.

FIG. 66: H-side sorted data length 5 bits, M-side sorted data length 5 bits, and L-side sorted data length 6 when only data having a value of “0” in the H area are sorted in the M and L areas. It is a schematic diagram which shows the storage state of the data memory, the distribution count memory, and the sort memory when the number of bit data is 16.

FIG. 67: H-side sorted data length 5 bits, M-side sorted data length 5 bits, L-side sorted data length 6 when only data having a value of “1” in the H area are sorted in the M and L areas It is a schematic diagram which shows the storage state of the data memory, the distribution count memory, and the sort memory when the number of bit data is 16.

FIG. 68: H-side sorted data length 5 bits, M-side sorted data length 5 bits, and L-side sorted data length 6 when only data having a value of “1” in the H area are sorted in the M and L areas. It is a schematic diagram which shows the storage state of the data memory, the distribution count memory, and the sort memory when the number of bit data is 16.

FIG. 69 shows an H-side sorted data length of 5 when only data having a value of “12” in the H area is sorted in the M and L areas.
FIG. 7 is a schematic diagram showing the storage states of a data memory, a distribution count memory, and a sort memory when the number of data is 16 with bits, M-side sort data length of 5 bits, and L-side sort data length of 6 bits.

[Explanation of symbols]

 Reference Signs List 10 data memory 11 distribution count memory 12 sort memory 15 H area sort processing circuit 16 L area sort processing circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/24 G06T 15/40

Claims (9)

(57) [Claims] 1. A sorting apparatus for sorting a plurality of input reference value data, comprising: data number generating means for generating a data number corresponding to each input reference value data; First storage means which divides the data into upper and lower data and holds the first address of a chain list of a data group having a value equal to the data at an address corresponding to the value of each data; Second storage means for holding the address of the end point data of the chain list of the data group having the same value as the data value at the address corresponding to the value of the data value, and data having the same value as the reference value data attached to each of the divided data. A third storage unit for storing a pointer of a chain list indicating a group; and data of the same value by sorting from upper data obtained by dividing the reference value data. Means for controlling so as to process only the divided lower-order data. 2. A sorting apparatus for sorting inputted reference value data comprising a plurality of digits, comprising:
A data number generating means for generating a data number corresponding to each input reference value data, and a plurality of means for dividing the input reference value data into two or more data groups and storing the divided data at addresses corresponding to the respective data numbers A digit reference value data storage area, and a storage area corresponding to a data group whose address is specified based on the reference value data of each divided data group;
When the reference value data corresponding to each area is input for the first time, a count start area for storing a data number generated by a data number generation means in this storage area, and an address designated based on the reference value data A count end area for updating and storing the data number generated by the data number generating means in this storage area each time the reference value data corresponding to each area is input; A new data area to be updated is stored in a pointer area for specifying the next address to which the address is specified and a pointer area specified by the data number before the update each time the data number in the count end area is updated. First control means for writing a number, and a sort method having a sort address area corresponding to the divided data group for storing the sort result. After the data number has been written to the upper count start area and the upper count end area according to the upper reference value data of the divided data group, the data written to the upper count start area Second control means for linking the number, the data number written in the upper pointer area and the data number written in the upper count end area and writing them in the sort memory, and sorting the upper reference value data After completion of the above, the reference value data from the lower reference value data storage area corresponding to the upper reference value data of the same value data of the upper reference value data is transferred to the lower count start area and the lower count. After writing to the end area, the data number written to the lower count start area and the lower pointer area Sorting device including a third control means for writing the sort memory data number written in the data number and the lower count end regions incorporated come in association chain, a. A first flag area corresponding to the count start area; and a second flag area respectively corresponding to the count end area, wherein the first flag area has data in the count start area. The sorting apparatus according to claim 2, wherein the flag is set when the data is stored, and the second flag area is set when data in the count end area is updated. 4. A system comprising: a flag group corresponding to an address based on upper-level reference value data; and means for setting a flag of the flag group at an address corresponding to an area where clipping or picking processing is performed. 3. The method according to claim 2, wherein after the sorting of the reference value data, the third control means skips the sorting of the reference value data on the lower side with respect to the reference value data on the upper side of the address corresponding to clipping. Or the sorting device according to 3. 5. The sorting apparatus according to claim 2, wherein the input reference value data is divided into two data groups of an upper digit and a lower digit. 6. The sorting apparatus according to claim 2, wherein the input reference value data is divided into three data groups of an upper digit, a middle digit, and a lower digit. 7. A sorting apparatus for sorting inputted reference value data comprising a plurality of digits, comprising:
A data number generating means for generating a data number corresponding to each input reference value data, and dividing the input reference value data into upper and lower digit data and storing the divided data at an address corresponding to each data number It has an upper digit and lower digit reference value data storage area and a first storage area in which an address is specified based on the upper digit reference value data, and the upper digit reference value data corresponding to each area is input first. When this is done, this storage area has an upper digit count start area for storing the data number generated by the data number generation means, and a second storage area whose address is specified based on the reference value data. Each time the corresponding upper digit reference value data is input, the upper digit count end area for updating and storing the data number generated by the data number generating means in this storage area, And a third storage area in which an address is specified based on the reference value data of the lower digit, and a lower digit pointer corresponding to each area. When reference value data is first input, a lower digit count start area for storing a data number generated by the data number generation means in this storage area, and a fourth storage area for specifying an address based on the reference value data And a lower digit count end area for updating and storing a data number generated by a data number generating means in this storage area each time reference value data of a lower digit corresponding to each area is inputted, Each time the data number of the lower digit pointer area for specifying the next address to which the address is specified and the data number of the upper row digit or the lower digit count end area is updated The upper digit or lower digits pointer area specified by the pre-update data number, a first control means for writing new data number to be updated,
A sort memory having a sort address area corresponding to an upper digit and a lower digit for storing a sort result, and after finishing writing a data number to an upper digit count start area and an upper digit count end area according to the reference value data of the upper digit, A second control unit for linking the data number written in the upper digit count start area, the data number written in the upper digit pointer area, and the data number written in the upper digit count end area to the sort memory, and After the sorting of the upper digit reference value data is completed, the reference value data from the lower digit reference value data storage area corresponding to the upper digit reference value data having the same value as the upper digit reference value data is counted. After writing to the area and the lower digit count end area, write to the lower digit count start area. Or data number, the sorting device including a third control means for writing the sort memory data number written into the data number and the lower digit counting end region written in the low-order pointer area in association chain, a. 8. A first flag area corresponding to an upper digit and a lower digit count start area, and a second flag area respectively corresponding to an upper digit and a lower digit count end area, wherein the first flag The sorting according to claim 7, wherein the area is set when data is stored in the count start area, and the second flag area is set when data in the count end area is updated. apparatus. And means for setting a flag of a flag group corresponding to an address based on reference value data of an upper digit, and setting a flag of the flag group of an address corresponding to an area for performing clipping or picking processing. 8. The method according to claim 7, wherein after the sorting of the reference value data, the third control means omits the sorting of the reference value data of the lower digit for the reference value data of the upper digit of the address corresponding to the clipping. Or the sorting device according to 8.