JPH01103785A - Sorting circuit - Google Patents

Abstract

PURPOSE:To execute the sorting of data at a time point the transferring processing of a highest order digit is finished by repeatedly executing the transferring processing between booth memory areas while a search digit is shifted respectively by one digit from the low order digit of reference information to the high order digit. CONSTITUTION:A sorting circuit 10 includes a sorting memory 12, which has two pairs of memory areas 12-1 and 12-2, and a sorter 14. A pair of reference axis information to be inputted are stored to the area 12-1. The sorter 14 sorting-processes a pair of the reference axis information, which are stored in the area 12-1, which alternatively transferring the information between the areas 12-1 and 12-2. Then, the information are rearranged in the order of a small value or in the order of the large value. A reading pointer 14-1 of the sorter 14 designates the address of the memory area to execute a data reading and one increment is executed each time the reading is executed. A writing pointer 14-2 designates the address of the memory area to execute a data writing and one increment is executed each time the writing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sorting circuit, and particularly to a circuit that sorts data based on information on a plurality of reference axes.

[Prior Art] An image synthesis circuit synthesizes and outputs various image signals for CRT display based on image information supplied from the outside, and produces a three-dimensional image rather than a two-dimensional flat image. Since it is possible to synthesize and output 3D images, for example, video games for 3D images, flight control simulators for airplanes and various vehicles, computer graphics, CA
It is widely used for D device displays and other uses.

By the way, when synthesizing three-dimensional images with depth in real time using an image synthesis circuit, the three-dimensional information of each specimen is processed at high speed for each frame based on the coordinate values in the depth direction of the screen, that is, the two-axis information. It is necessary to sort by.

For this reason, it has been desired to develop a sorting circuit that can quickly sort a plurality of three-dimensional data based on predetermined reference axes, that is, two-axis information.

[Problem to be solved by the invention 1 However, conventionally, such sorting is
The task of successively comparing and sorting the axis information itself,
Since this was performed on all two-axis information, a relatively large computer had to be used to perform high-speed sorting, resulting in a problem that the entire device became complicated and expensive.

[Object of the Invention] The present invention has been made in view of such conventional problems, and its purpose is to provide a sorting circuit that can perform sorting processing of a plurality of data at high speed with a simple configuration. There is a particular thing.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a circuit for sorting a plurality of data based on predetermined reference axis information, comprising at least two memories for writing reference axis information. A sorting memory having a sorting area and a set of reference axis information stored in one memory area are searched for the value of a predetermined search digit, and the set of reference axis information is sorted based on the searched value in ascending order or a sorter that repeats a transfer process of copying to the other memory area in descending order between both memory areas while shifting the search digit one by one from the lowest digit to the highest digit of the reference axis information; The feature is that the data is sorted based on the reference axis information.

The present invention also provides a circuit for sorting a plurality of data consisting of reference axis information and combination information thereof based on predetermined reference axis information, comprising an information memory in which combination information of each data is written, and a reference of each data. a sorting memory having at least two memory areas in which axis information and combination information write addresses are written in pairs; and a set of predetermined search digits for reference axis information stored in one memory area. The standard transfer process is to search for the value of , and copy this set of reference axis information and the paired combination information write address to the other memory area in ascending or descending order while classifying them based on the searched values. A sorter that repeatedly moves between both memory areas while shifting the search digit one digit at a time from the lowest digit to the highest digit of axis information; The present invention is characterized in that the data is sorted based on the reference axis information by reading the combination information from the information memory based on the combination information write address forming the .

[Operation] According to the present invention, the transfer process is repeated between both memory areas while shifting the search digit one digit at a time from the lower digit to the upper digit of the reference axis information. When the transfer process is completed, the data is sorted in ascending order or descending order based on the reference axis information.

Therefore, according to the present invention, the value of a predetermined search digit of a set of reference axis information stored in one memory area is simply searched, and the set of reference axis information is ordered in ascending or descending order based on the searched value. By simply repeating the transfer process of classifying data into one area and copying it to another memory area, multiple data can be sorted at high speed based on predetermined reference axis information, which is similar to the sorting process of the image synthesis circuit described above. It can be used not only as a circuit but also for a wide range of other purposes.

[Example] Next, preferred embodiments of the present invention will be described based on the drawings.

111th Example FIG. 1 shows a preferred embodiment of the sorting circuit according to the present invention.

The sorting circuit 10 of the present invention includes a sorting memory 12 having at least two sets of memory areas 12-1 and 12-2;
Sorter 1 that sorts reference axis information using -2
4, and is characterized in that it sorts and outputs data in ascending or descending order based on a set of reference axis information randomly input to the sorting memory 12.

Here, each of the memory areas 12-1 and 12-1
-2 must be formed to have a memory capacity sufficient to store a set of input reference axis information. A set of reference axis information input to the sorting memory 12 is stored in either one of the memory areas 12-1 and 12-2. In the embodiment, it is configured to be stored in the memory area 12-1.

The sorter 14 also sorts a set of reference axis information stored in the memory area 12-1 while alternately transferring it between the memory areas 12-1 and 12-2. Sort in descending order.

In the embodiment, this sorter 14 uses two address pointers: a read pointer 14-1 and a write pointer 14-2.

The read pointer 14-1 specifies the address of the memory area from which data is to be read, and data is always read from the address pointed to by the pointer 14-1. The address is incremented by one.

Further, the write pointer 14-2 specifies the address of the memory area to which data is to be written, and the read data is always written to the address pointed to by this pointer 14-2. The value is incremented by one every time writing is performed.

FIG. 2 and FIG. 3 show a set of reference axis information in which the number of data is N, and each data is expressed as an M-bit binary number.
An example is shown in which sorting processing is performed in ascending order from the smallest memory area address.

The characteristic feature of the present invention is to search for the value of a predetermined search digit of a set of reference axis information stored in one memory area,
The objective is to perform a transfer process in which this set of reference axis information is classified based on the searched values and transferred to the other memory area in ascending or descending order.

By repeating this transfer process between both memory areas while shifting the search digit one by one from the lowest digit to the highest digit of the reference axis information, the transfer process for the most significant digit is completed. At that point, the reference axis information can be sorted and stored in one memory area in ascending or descending order.

Here, when attempting to sort one set of reference axis information in ascending order, it is sufficient to classify the reference axis information based on the value of each search digit and transfer processing in ascending order. When attempting to sort the axis information in descending order j1@, it is sufficient to classify the reference axis information based on the value of each search digit, contrary to the previous case, and then transfer the information in descending order.

FIGS. 4 to 7 show an example of the sorting process performed according to the flowcharts shown in FIGS. 2 and 3. In the same figure, one set of reference axis information to be subjected to sorting processing is 4-bit (M=4) 2
It is composed of a total of eight pieces of reference axis information expressed in base numbers "1" to "8".

First, a set of reference axis information randomly input into the sorting memory 12 is stored in one sorting area 12-1.
Assume that the data is stored as shown in FIG.

When the sorting shown in Fig. 2 is started for the set of reference axis information stored in this way, the variable m representing the search digit is first reset to O, and then the sorting shown in Fig. 3 is started. Transfer processing begins.

Then, when the transfer process is started, each pointer 14-1 . and 14-2 are both reset to 0 and specify the starting address of the memory area from which data is read and the memory area from which data is written.

Then, according to flow A in FIG.
A transfer process is performed in which the addresses are sequentially read from the memory area 12-2 in ascending order of address and sequentially written to the other memory area 12-2.

Then, when all the reference axis information for which the value of the search digit of m=0 is r
'' reference axis information is read out sequentially from the youngest address,
Transfer processing to the other memory area 12-2 is performed.

In this way, the sorting circuit 10 of this embodiment has 1
In the transfer process, reading from the memory area 12-1, which is the transfer source, is performed in two stages as shown in flow A and flow B, and writing of the transfer information to the memory area 12-2 is performed once.

Therefore, if the read and write operations for N pieces of reference axis information are not performed simultaneously and the read and write access times for each memory area are equal, one transfer process requires NX (2+1 > = 3N... - As expressed in (1), a total transfer time of 3N access cycles is required.

In addition, when performing such a transfer process, the order relationship between the reference axis information whose search digit m is "0" and the reference axis information whose search digit m is "1" should not be interchanged. There is a need.

In this way, when the transfer process for m=o is completed, the sorting circuit 10 converts the search digit m to 1 as shown in FIG.
Increment by 1 and set m=1.

Then, as shown in FIG. 5, one memory area 12
The transfer process shown in FIG. 3 is similarly performed on the reference axis information stored in -2.

As a result, the reference axis information written in this memory area 12-2 is transferred to the other memory area 12-2 as shown in FIG.
Then, when the transfer process for m=1 is completed, while incrementing the search digit m in the same way, m=2 as shown in FIGS. 6 and 7.
Then, transfer processing is performed for the search digit m-3.

In this way, when the transfer process using the most significant digit m=3 of the reference axis information as the search digit is completed, the memory area 12-1
The reference axis information transferred and processed within is as shown in Figure 7.
The information will be sorted in ascending order from ``1'' to ``8''.

In this way, in the sorting circuit 10 of this embodiment, a set of reference axis information is sorted in ascending or descending order by performing transfer processing M times (M is the number of bits of reference axis information) for each reference axis information. can be sorted into Therefore, as shown in Figures 4 to 7, if the reference axis information is M = 4 bits, then -15 = then the sorting process is completed by performing the transfer process four times for each reference axis information. .

According to the sorting circuit 10 of the embodiment, if the number of bits M of the reference axis information is an even number, the reference axis information is first stored in the memory area 12-1, and if M is an odd number, the other memory area is stored. A set of reference axis information for which sorting has been completed is stored in 12-2.

Further, in the embodiments shown in FIGS. 4 to 7, the case where one set of reference axis information is sorted in ascending order has been described as an example, but the present invention is not limited to this. For example, the flowchart shown in FIG. , if the transfer process is performed so that the flow shown by B is executed first, and then the flow shown by A is executed,
Contrary to the above embodiment, a set of reference axis information can be sorted in descending order.

Further, in the above embodiment, the case where a set of reference axis information expressed in binary numbers is sorted is explained as an example, but the present invention is not limited to this, and the present invention can be applied to ternary numbers, quaternary numbers, etc. Sorting can also be done in the same way.

For example, when sorting a set of reference axis information expressed in ternary numbers in ascending order, first m
The lowest digit of =o is the search digit. Then, first, the reference axis information whose search digit has a value of "0" is transferred, then the reference axis information whose value is "1" is transferred, and then the reference axis whose value is "2" is transferred. Transfer and process axis information.

When such a transfer process is completed, the same transfer process may be repeated while incrementing the search digit m by one, as shown in FIGS. 9 and 10.

By doing this, as shown in Figure 10, when the transfer process of the most significant digit is completed, the 1
It will be appreciated that the sets of reference axis information are sorted in ascending order.

Further, in the above embodiment, the case where a set of reference axis information represented by integers is sorted is explained as an example, but the present invention is not limited to this, and the sorting process can be performed similarly for floating point data. It can be done by

In this case, if the reference axis information is a decimal number, normalized floating point data is input to the sorting memory 12 as shown in the following formula, mX10 (10-1≦m<100) or , when the reference axis information is a binary number, floating point data expressed by the following equation is input.

mX2 (26m×2) In each of the above formulas, m represents the normalized mantissa part, and e represents the exponent part (an integer of e≧0).

In the present invention, when sorting such floating point data, pay attention to the number of digits and sort each data by
It is necessary to rearrange them in advance in order of the mantissa.

Therefore, when sorting floating point data, a normalized data processing circuit 30 is provided before the sorting memory 12, and this normalized data processing circuit 30 is used to sort input floating point data into exponent and mantissa parts. It is necessary to convert the data into rearranged data in the order of , and input it to the sorting memory 12 .

By using such a normalization data processing circuit 30, for example, decimal floating point data consisting of 2 digits for the exponent and 3 digits for the mantissa, for example floating point data of 0, 123X 107, can be converted to 07123. and the value of 0.3X 10” floating point data is 14300
is converted into a value and input to the sorting memory 12.

Also, floating point data consisting of a binary number with a 2-digit exponent and a 3-digit mantissa, for example, floating point data of 0.101 x 21 is converted to data of 01101, and floating point data of 0, 110 x 210 is converted to 10110. is converted into a value and input to the sorting memory 12.

In this way, according to the present invention, even when floating point data is input as reference axis information, the normalization data processing circuit 30 is used to rearrange it in the order of exponent part and mantissa part, and the data is stored in the sorting memory 12. By inputting the information, the input reference axis information can be sorted in ascending order or descending order in the same manner as in the above embodiment.

For example, as shown in Figure 29, the mantissa part is 3 digits and the exponent part is 1 digit.
Assuming that a set of reference axis information consisting of a decimal number of digits is input, each floating point data making up the reference axis information is data processed so that the exponent part and the mantissa part are arranged in the order of the exponent part and the mantissa part, and then stored in the sorting memory 12. is input.

Therefore, it will be understood that the set of reference axis information thus input to the sorting memory 12 is sorted in ascending or descending order in the same manner as in the previous embodiment.

Furthermore, as shown in Figure 30, assuming that a set of reference axis information consisting of a binary number with 2 digits for the mantissa and 2 digits for the exponent is input, each floating point data of the reference axis information is The sorting memory 12 is sorted in the order of part and mantissa part.
is input to.

= 20- Therefore, the 11 sets of reference axis information thus input to the sorting memory 12 are sorted in ascending or descending order in the same manner as in the previous embodiment.

Further, in the above embodiment, the case where positive reference axis information is sorted is explained as an example, but the present invention is not limited to this, and the present invention is also applicable to a set of negative reference axis information. The sorting can be done similarly by using complements.

Further, according to the present invention, even for a set of reference axis information in which positive and negative numbers are mixed, by dividing this into a positive group and a negative group and sorting them respectively, a set of reference axis information can be divided into a positive group and a negative group. The axis information can be sorted as a whole in ascending or descending order.

Note that in binary data that normally uses a complement for a negative number, a value of 0 is given to the most significant bit as a positive or negative sign, and a value of 1 is given to the most significant bit when it is negative. Therefore, when dividing the reference axis information containing a mixture of positive and negative data into positive and negative groups, it is sufficient to divide the reference axis information into 5 groups, the most significant bit of which is 0 and the most significant bit is 1.

Also, if you set the most significant bit to 0 if it is negative and 1 if it is positive, you can use the entire reference axis information without having to group the reference axis information into positive and negative groups. You can also sort in ascending or descending order.

Further, in the embodiment, the sorting memory 12
Although the description has been made by taking as an example a case where only one set of reference axis information is written in the memory area 12-1 of the memory area 12-1 and the reference axis information is sorted, the present invention is not limited to this. Similar sorting can be performed on sorting data consisting of information that pairs with axis information.

In this case, one set of input sorting data may be sequentially written into one memory area 12-1, and sorting may be performed in the same manner as in the previous embodiment, focusing on the reference axis information.

Note that if this is done, the amount of data per piece of sorting data will increase, so the time for reading and writing data will become longer. Therefore, it is inevitable that the time required for sorting processing increases in proportion to the amount of data.

Second Embodiment In order to solve such problems, when sorting data including combination information is sorted based on its reference axis information, a sorting circuit 10 shown in FIG. 11 is used.
It is preferable to use

When a set of sorting data is input, this sorting circuit 10 stores only the reference axis information of the sorting data in the sorting memory 12 in the same manner as in the above embodiment, and stores the combinations paired with each reference axis information. Information is configured to be stored within the information memory 16.

At this time, it is necessary to provide some form of correspondence between the combination information stored in the information memory 16 and the reference axis information stored in the sorting memory 12.

Several methods can be considered to provide such a correspondence relationship, but in this embodiment, the information memory 16
The write address of each combination information written in is defined as an index, and this index is stored in the sorting memory 12 in association with each reference axis information.

That is, in the sorting memory 12 of this embodiment,
Each pair of reference axis information and index is written to an adjacent address (for example, the reference axis information is written to an even address and the index is written to an odd address). The transfer process by the sorter 14 is performed using the reference axis information and its index as one unit.

Therefore, in the sorting circuit 10 of the embodiment, it is necessary to read and write about twice as much data to transfer data as compared to the sorting circuit shown in the previous embodiment, and therefore, the time required for - times of transfer processing also increases. This is approximately twice as long as the time shown in the first equation.

Then, the process of transferring the reference axis information written in the sorting memory 12 is carried out repeatedly while sequentially incrementing the search digit m from the least significant digit to the most significant digit, in the same manner as in the first embodiment. , a set of reference axis information stored in the sorting memory 12 can be sorted in ascending order or descending order.

The output of the sorting data from the sorting circuit 10 is such that when reading out the sorted reference axis information from the sorting memory 12, the corresponding combination information is read out from the information memory 16 based on the index paired with each reference axis information. It is carried out as follows.

By doing so, the sorting circuit 10 of the embodiment outputs sorting data that has been sorted based on predetermined reference axis information.

As described above, according to this embodiment, the reference axis information sorting process using the sorting memory 12 can be performed in a short time regardless of the amount of information of the sorting data. Therefore, even when the amount of information per unit of sorting data is large, the sorting process can be performed efficiently in a short time.

Here, the sorting time of the sorting circuit 10 of this embodiment will be compared with that of the sorting circuit 10 shown in FIG.

In the embodiment described above, only the reference axis information needs to be transferred, but in this embodiment, both the reference axis information and the index are transferred.
Since two pieces of information must be transferred, the transfer process takes approximately twice as long.

Therefore, the transfer process of this embodiment requires 6N access cycle time, as shown in (2): 2 (NX (2+1>) = 6N).

In addition, in such a sorting circuit 10, at the start and end of the sorting operation shown in FIG. In addition, it is necessary to provide a margin of approximately 2 access cycles for each transfer process.

Therefore, the sorting circuit 10 of the embodiment requires an access cycle time expressed by the following equation in order to perform the sorting process.

((6N+2>M+2)...(3) In addition, when the sorting circuit 10 of this embodiment is applied to a three-dimensional image synthesis apparatus to be described later, the sorting process for one screen can be performed in one field time ( Approximately 1/60 second = 1
6.5m5ec), but even in such a case, the sorting circuit 10 of the embodiment can perform the sorting process with sufficient margin.

That is, sufficient conditions for compositing images, e.g.
Assuming that the number of sets of information is N=1023 and the number of bits of each piece of information is M-15, the sorting time is calculated as 921 from the third equation above.
02 access cycle time.

Here, assuming that the RAM access of the sorting circuit 10 is performed in synchronization with a 6.144 MHz clock, the sorting time is expressed by the following equation.

92102/<6.144xlO6) =15.0
m5ec-(4) In this way, in the circuit of the embodiment, the sorting processing time is within one field time (16.5m5ec) of the CRT mentioned above, so the sorting processing can be completed within one field time. It will be understood that it is possible to carry out the following with ease.

Furthermore, in this embodiment, the sorting time can be further shortened by performing the transfer process as follows.

For example, when searching for data "0" in a predetermined search digit m, if data "1" is found, there is no need to read up to that index.

Conversely, if data of "0" is found while searching for "1", there is no need to read the index in the same way.

Therefore, when performing transfer processing, if such unnecessary indexes are not read, the transfer processing time can be shortened by N access cycles in one transfer process, and as a result, the overall sorting time is reduced. The processing cycle can be reduced to (5N+2') M+2=76757 access cycles. For example, assuming that this sorting circuit 10 is applied to a three-dimensional image under the same conditions as described above, the processing time is 76757/ (6,144xlO6) -12,5m
It will be 5ec.

A third preferred embodiment of the sorting circuit 10 according to the present invention is shown in FIG. 2 and 14-3 are provided, and a spare pointer 14-4 is also provided.

Here, the one write pointer 14-2 is
It is used to specify the write address of the reference axis information where the data of the search digit m is "0", and the other write pointer 14-3 is the write address of the reference axis information where the data of the search digit is "11". Used to specify.

In addition, in the spare pointer 14-4, the data in the digit one digit above the search digit m, that is, the digit <m+1) is "0".
This is used to count the number of pieces of reference axis information indicating the value of .

The characteristic feature of this embodiment is that such a set of pointers 1
4-2 and 14-3 and the preliminary pointer 14-4, by performing only one search for each search digit m, the data of the digit is not only the reference axis information of r□, but also the ” reference axis information can also be transferred and processed.

FIG. 13 shows an example of a sorting operation performed using the sorting circuit 10 of this embodiment. For example, as shown in FIG. When a sorting operation for a set of reference axis information is started, an initial counting operation is first performed. This initial count is used to count the number of pieces of reference axis information in which the value of the lowest digit m=o is "o".

An example of this initial counting operation is shown in FIG. 14. When the initial counting starts, the count k is first reset to 0, and then the value of each reference axis information in the m=o digit is set to the address. Search in descending order of age.

Then, each time the reference axis information whose value is "0" is searched, the count value k is incremented by one.

When such an initial count ends, the transfer process shown in FIG. 15 is started.

When this transfer process starts, first the read pointer 14
-1 and write pointer 14-2 are reset, and each of these pointers 14-1 and 14-2 specifies the read address and write address of the beginning of memory areas 12-1 and 12-2.

At the same time, the count value k counted using the preliminary pointer 14-4 in the preliminary counting operation is set as an initial value in the write pointer 14-3.

Therefore, the first write address specified by the write pointer 14-3 specifies the first write address of the reference axis information in which the value of the search digit m indicates "1".

When such initial settings are completed, the value of the preliminary counter 14-4 is reset to 0, as shown in FIG.
A series of transfer processing operations consisting of flows E and F are performed.

That is, in flow E, reference axis information is read from the transfer source read area specified by the read pointer 14-1, and the value of the read pointer 14-1 is incremented by one.

Then, the search digit m(
In the case shown in FIG. 4, if the value of m=0) is [0], write the reference axis information and point it to the pointer 14-2.
, and increments the value of the write pointer 14-2 by one.

Also, the value of the search digit m of the read reference axis information is “1”.
”, the reference axis information is transferred to the address in the memory area 12-2 specified by the write pointer 14-3, and then the value of the write pointer 14-3 is set to 1.
Increment by one.

When the transfer of the first reference axis information is completed, as shown in flow F, the value of the digit one digit above the search digit m, that is, <m+1) is determined for the read reference axis information. It is determined whether the value is 0 or not, and if the value is "O", the count value k of the preliminary counter 14-4 is incremented by one.

In this way, the sorting circuit 10 of the embodiment performs a transfer process according to the value of the search digit each time the reference axis information is read out, and also determines whether the value of the digit one above the search digit is 0 or not. If it is 0, the value of the preliminary counter 14-4 is incremented each time.

As a result, if a search is performed once for a predetermined search digit m, for example m=o, using the sorting circuit 10 of the embodiment, all transfer processing for the search digit is completed, and Upper digit (m=, 1 digit)
It is possible to detect how many pieces of reference axis information whose value is "0" by using the preliminary pointer 14-4.

Therefore, according to the sorting circuit 10 of the embodiment, each time the search for each search digit m is completed, the search digit m is incremented by one as shown in FIG. 13, and the transfer process shown in FIG. 15 is repeated. By doing so, for example, Figures 4 to 7
As shown in the figure, sorting of a set of reference axis information can be performed in the same manner as in the first embodiment.

At this time, the sorting circuit 10 of this embodiment can significantly shorten the access cycle time required for one transfer process and shorten the time required for sorting, compared to the sorting circuit shown in FIG. .

That is, according to the sorting circuit 10 of this embodiment,
In one transfer process, it is sufficient to perform one round of data reading from the transfer source memory area and one round of data writing to the transfer destination memory area.

Therefore, when transferring N pieces of reference axis information, the transfer process can be completed in an access cycle time of N(1+1)=2N (5).

Further, the sorting circuit 10 of this embodiment may be
If applied to the sorting circuit 10 of the type shown in FIG. 1, the data subject to transfer processing will be doubled (reference axis information and its index information). Therefore, the time used for one transfer process is twice the value shown in Equation 5, that is, the access cycle time of 2×2N=4N (6).

Furthermore, when the sorting circuit 10 of this embodiment is applied to the circuit shown in FIG. 11, it is necessary to provide a margin of two access cycles, one access cycle each for initializing and detecting the end of the sorting process. In addition, in addition to this, two steps are required for the transfer process of flow E shown in FIG.
It is necessary to check the access cycle margin, and the first
The initial count shown in Figure 4 requires (N+2) access cycles. Therefore, the entire sorting requires an access cycle time of <4N+2)M+ (N+2)+2 = (4N+2)M+N+4 (7).

The access cycle time shown by this seventh equation is M=1
If the calculation is performed on the assumption that a set of reference axis information consisting of 5.N=1023 is to be sorted, the sorting will require 62437 access cycle times.

Therefore, this sorting is performed at 6.144MHz, for example.
The sorting time is 62437/ (6,144x106) = 10.2m
5ec, and it will be understood that the sorting time can be significantly shortened compared to when the sorting circuit of the first embodiment is applied to the circuit shown in FIG.

In this embodiment, the case where data is sorted based on reference axis information consisting of binary numbers has been explained as an example, but in addition to this, data can be sorted based on reference axis information consisting of ternary numbers, quaternary numbers, etc. It can also be used when sorting.

For example, if the reference axis information is a ternary number, "0", "1", "
A total of three write pointers for ``2'' and a total of two reserve pointers for rQJ and rlJ are provided. Then, the write pointer for "2" has rQJ rl as its initial value.
It is sufficient to set the added value of each spare pointer for J. By doing so, data can be sorted well based on the reference axis information consisting of ternary numbers.

As described above, according to the present invention, by using a sorting memory having two sets of memory areas, it is possible to quickly sort one set of reference axis information whose values are randomly input.

In particular, according to the present invention, sorting can be performed by the simple operation of transferring data between two memory areas according to predetermined rules, making the entire circuit extremely simple. becomes possible.

Furthermore, according to the present invention, even when the reference axis information is combined with various information to create sorting data with a large amount of data, such data can be processed by adopting the circuit configuration shown in FIG. It becomes possible to sort a large amount of each sorting data at high speed according to its reference axis information.

Application As explained above, sorting circuit 1 according to the present invention
0 can perform high-speed sorting of various data based on its reference axis information. Therefore, when sorting a large amount of data, for example, when sorting database information based on reference axis information such as date,
It can be used in a wide range of other applications.

A preferred example in which the sorting circuit 10 of the present invention is applied to a three-dimensional image synthesis device will be described below.

Specific Example FIG. 16 shows a preferred example of a three-dimensional image synthesis device using the present invention. It is composed of a circuit 22 and is configured to display a three-dimensional two-dimensional image, that is, a pseudo three-dimensional image, on a CRT.

The polygon information generation circuit 20 handles three-dimensional three-dimensional information and performs various transformations such as rotation, parallel translation, and perspective projection to convert the three-dimensional information to be displayed into two-dimensional polygon combination information. , the (X, Y) coordinates of the vertices of each polygon are calculated as polygon information.

The polygon information generating circuit 20 also calculates the display point in the depth direction of each polygon, that is, the two-axis coordinates of the center of each polygon, as polygon information, and further calculates color information and brightness of the polygon as necessary. Compute information etc. as accompanying data.

In this embodiment, in order to simplify the explanation, the following explanation will be given assuming that color information is calculated as the accompanying data.

In this way, when the polygon information of each polygon (XY coordinates at each vertex position of the polygon, Z axis coordinate at the center point, and color information) is calculated and output from the polygon information generation circuit 20, the sorting circuit 10 The plurality of output polygon information is sorted based on predetermined reference axis information, in this case Z-axis information, and output to the polygon information display circuit 22.

That is, the sorting circuit 10 of the embodiment sorts and outputs a plurality of pieces of polygon information calculated for each screen of the CRT to the polygon display circuit 22 in order of decreasing Z-axis coordinate value.

Therefore, as shown in FIG. 17, if the CRT screen is used as a reference point and the three-dimensional coordinates of XYZ are set so that the Z axis increases in the depth direction, the sorting circuit 1
From 0 onwards, polygon information is sorted and output in order from polygons displayed in the front of the screen, that is, polygons with a high priority.

Then, the polygon display circuit 22 synthesizes the polygon information of each polygon output in this way into an image based on its priority. For example, when multiple polygons are displayed in a superimposed manner, Three-dimensional images are synthesized so that polygons with high priority are displayed preferentially.

In this embodiment, the sorting circuit 10 has been described using an example in which the polygon information of a polygon is sorted and outputted in ascending order based on its two-axis coordinate values, but the present invention is not limited to this, and the present invention can be modified as required. It is also possible to sort and output the polygon information in descending order based on the reference axis information, or in the case of the embodiment, the Z-axis information.

Polygon Ikuchi FIG. 18 shows a specific configuration of a polygon information generation circuit 20 applied to an airplane flight control simulator device. This simulation image is output to the sorting circuit 10 as combination information of a plurality of polygons.

In the embodiment, this polygon information generation circuit 20 includes an operation section 20-1, a main CPU circuit 20-2, a three-dimensional information memory 20-3, and a three-dimensional calculation circuit 20-4. The operation section 20-1 is formed exactly like the cockpit of an actual airplane, and the operation information is converted into an electrical signal via a switch or a variable resistor, and the main CPU circuit 2
Output to 0-2.

The main CPU circuit 20-2 forms the central part of the operation of the simulator, and calculates data representing the flight position of the airplane based on the signals output from the operation unit 20-1, and calculates the data representing the flight position of the airplane. Output to 4.

The main CPU circuit 20-2 also receives various status signals output from the three-dimensional calculation circuit 20-4, such as "The airplane collided with another object,""The airplane entered turbulence," It receives information such as "The airplane has arrived at its destination", calculates situation data corresponding to this, and outputs it to the three-dimensional calculation circuit 20-4.

Furthermore, the three-dimensional information memory 20-3 stores all objects expressed as polyhedra, three-dimensional coordinate data representing each vertex of this polyhedron, and polygon data representing each surface of the polyhedron as a connection between each vertex. Written and memorized. Here, each of the polyhedral data is expressed using a fixed coordinate system.

Furthermore, the three-dimensional calculation circuit 20-4 calculates the scene visible from the airplane based on the current position of the airplane calculated by the main CPU, while referring to various polyhedral data stored in the three-dimensional information memory 20-3. do. The scene is then outputted to the sorting circuit 10 as a combination of graphical information.

The polygon information generating circuit 20 in this embodiment has the above configuration, and its operation will be explained next.

43 The three-dimensional calculation circuit 20-4 of one embodiment assumes a moving coordinate system with the airplane as the origin, and as shown in FIG. 17, the right direction in the figure is the X coordinate, the downward direction is the Y coordinate, and the forward direction is the Set to Z coordinate.

When the main CPU circuit 20-2 outputs movement coordinates representing the current position of the airplane, the three-dimensional calculation circuit 20-4 reads predetermined polyhedral data from the three-dimensional information memory 20-3.

In the embodiment, since the information written in the three-dimensional information memory 20-3 is expressed using a fixed coordinate system, the three-dimensional calculation circuit 20-4 uses the information read from the three-dimensional information memory 20-3. It is necessary to convert the data into coordinate data of the moving coordinate system.

This transformation can be achieved by a combination of two calculation elements: coordinate rotation and translation, and during this calculation process, information that is found to be out of the pilot's field of vision (such as <2<a) is removed. The situation data obtained through the conversion is output to the main CPU circuit 20-2. Then, each coordinate-converted polyhedron information is then converted to z×0, assuming that the display screen is on the plane of Z=0.
Perspective projection transformation is performed toward the viewpoint of .

Through such perspective projection transformation, each polyhedron data is represented as a collection of point information obtained by converting the coordinates of each vertex of the polyhedron into two dimensions of X and Y.

Furthermore, in performing such perspective projection transformation, the distance between the viewpoint and the coordinates of each vertex of the polyhedron is determined in advance.

Then, the two-dimensional point coordinates (vertex coordinates of the polyhedron) obtained by the perspective projection transformation are classified for each polygon representing the surface of the polyhedron, and as soon as the classified polygon enters the field of view of the pilot, that is, the field of view of the screen. Polygons that do not fit into the field of view are removed.

Thereafter, this three-dimensional calculation circuit 20-4 accepts the polygon that falls within the coordinate range, and calculates the Z value at the center point of the polygon.
Determine the axis coordinate value as a representative value.

At the same time, the three-dimensional calculation circuit 20-4 calculates associated data of each polygon within the coordinate range, and in the embodiment, color information.

Then, the three-dimensional calculation circuit 20-4 outputs the XY coordinates of the vertices of each polygon, the two-axis coordinates of the center position, and color information obtained in this way for each polygon as polygon information.

The polygon information of each polygon output from the polygon information generation circuit 20 of the embodiment is composed of 17 words, of which 1 word is the 2 coordinates of the center point, the remaining 16 words are the XY coordinates of the apex of the polygon, It is used to express color information, etc.

Further, one word is composed of 17 bits.

In this way, the polygon information generation circuit 20 of the embodiment converts the situation in the field of view of the pilot into combination information of a plurality of polygons, and sequentially outputs the polygon information of each polygon to the sorting circuit 10. Become.

Here, each polygon is displayed closer to the screen as the two-axis coordinate value included in its polygon information is smaller.
The smaller the Z-axis coordinate value included in the polygon information, the higher the priority of the polygon. Therefore, by sorting the polygon information of each polygon that is randomly output in this way in descending order of its Z-axis coordinate value, it becomes possible to easily and quickly synthesize a three-dimensional image using the polygon display circuit 22. .

(The following is a blank space) The sorting circuit 10 of the present invention is characterized in that it sorts a plurality of data including predetermined reference axis information in ascending order or descending order based on the reference axis information. It is something.

FIG. 19 shows a specific configuration of the sorting circuit 10 according to this embodiment.

The sorting circuit 10 of the embodiment is formed as a circuit of the type shown in FIG. 11, and uses a sorting RAM 12 as a sorting memory and an XVRAM 16 as an information memory.

The sorting RAM 12 and XVRAM 16 are
It is formed as a so-called multi-board RAM in which writing of data by the polygon information generation circuit 20 at the front stage and reading of data by the polygon display circuit 22 at the rear stage are performed independently.

Of the polygon information for one screen of polygons outputted from the polygon information generation circuit 20, its reference axis information (in the embodiment, Z-axis information) is written to the sorting RAM 12, and the remaining information is written to the XVRAM 16. .

The sorter 14 sorts the Z-axis information written in the sorting RAM 12 and also controls these RAMs 12 and 16.

In this embodiment, the sorting RAM 12 sorts Z written in the sorting RAM 12.
Only axis information is provided, and polygon information written in the XVRAM 16 is transmitted as is from the input side to the output side.

Therefore, after the sorting process is completed, the sorted Z-axis information and XVRA in the sorting RAM 12 are
An "index" is required to indicate the relationship with the polygon information written in M16.

Therefore, from the polygon information generation circuit 20 to
6 and the sorting RAM 12, when the polygon information of each polygon is written into the sorting RAM 12, the start address of each polygon information written into the XVRAM 16 is written into the sorting RAM 12 as an "index."

At this time, the index written to the sorting RAM 12 is given as a one-word value for each polygon,
Sorting RAM in pairs with the Z-axis coordinate of the corresponding polygon
It is written in 12.

(a) Cycle Steal By the way, the XYRAM 16 is formed as a dual port RAM that is accessed by both the polygon information generation circuit 20 and the polygon display circuit 22. Also,
The sorting RAM 12 is formed as a triple-port RAM that is accessed from the top by adding a sorter 14 to the previous two circuits.

In order to make normal RAM multi-board like this,
Generally, a method called cycle steal is used.

In this embodiment, as shown in FIG.

XYR in synchronization with Tarokku CPI of 3.072 MHz
, AM16 is multi-boarded, and this clock C
The sorting RAM 12 is multi-ported using a clock CP2 obtained by dividing PI into two.

In the figure, ■ represents a writing period by the polygon information generation circuit 20, ■ represents a reading period by the polygon display circuit 22, and ■ represents a writing or reading period by the sorter 14.

(b) Area switching Further, in this embodiment, the sorting RAM 12 and the XYRAM 16 each have a plurality of memory areas, and each area is formed to have a capacity of one screen (one field). .

In these RAMs 12 and 16, different memory areas are accessed by various conversion circuits within one field period, and at the time of field switching,
It is formed so that the area accessed by the peripheral circuits can be switched.

As a result, polygon information generation circuit 20→sorter 1
4→polygon display circuit 22=51−pipeline processing is realized.

(b-1) Area switching of sorting RAM 12 Although it is sufficient that the sorting RAM 12 of the present invention is formed to have at least two memory areas,
In this embodiment, in order to speed up the sorting process, it is formed to have four memory areas.

FIG. 21 shows an example of the area switching operation of each memory area 12-1, 12-2, ... 12-4 of the sorting RAM 12, and the sorting R
Four memory areas 12-1.12-2 in AM12,
. . 12-4 is schematically shown how the memory areas of 12-4 are switched over time.

In the figure, to simplify the explanation, the memory area located in the area 100 is the polygon information generating circuit 20.
The memory areas located in areas 102 and 104 are accessed by the sorter 14,
It is assumed that the memory area located in the area 106 is accessed by the polygon display circuit 22.

Here, A (not shown), B (not shown), and C are two-axis information for each field before sorting, a
, b, c are Z for each field during sorting
Axis information A-, B-1C- respectively represent Z-axis information for each field after sorting.

Here, when focusing on the two-axis information of C, c, and C-, first, in field 1, memory area 12-1
The two-axis information of C is written by the polygon information generation circuit 20.

Then, at the same time as switching from field 1 to field 2, area switching is performed between area 12-1 accessed by the polygon information generation circuit 20 and area 12-2 accessed by the sorter 14. At the same time, the area 12-3 accessed by the sorter 14 and the area 12- accessed by the polygon display circuit 22
Area switching is performed between 4 and 4.

Such switching of each memory area is performed instantaneously every time a field is switched, and then each memory area is accessed by the polygon information generation circuit 20, polygon display circuit 22, and sorter 14 according to the timing chart shown in FIG. Ru.

At this time, as described above, the sorter 14 searches for the value of a predetermined search digit of the set of reference axis information stored in the negative memory area, and sets the set of reference axis information based on the searched value. The sorting process is repeated in which the data is sorted and transferred to the other memory area in ascending or descending order.

When such sorting is completed, the Z-axis information of C is written in the memory area 12-1 or 12-4 in a sorted state in ascending order or descending order.

At this time, if the number of bits M of the reference axis information is an odd number,
Final reference axis information is written into memory area 12-4. However, if the number of bits M is an even number, the reference axis information is written in the memory area 12-1, so in this case, it is necessary to transfer the value to the other memory area 12-4. Thereafter, at the same time as switching from field 2 to field 3, the memory area 12-4 will be accessed by the polygon display circuit 22.

Further, when the number of bits M is an even number, the final reference axis information written in the memory area 12-1 as described above is not transferred to the memory area 12-4, and for example,
The polygon display circuit 22 may be configured to directly read out the final sorted reference axis information from the memory area 12-1 at the same time as field 3 is switched to field 4. At this time, it is necessary to perform area switching so that the reference axis information randomly output from the polygon information generation circuit 20 is written into the memory area 12-4.

In this way, in the present embodiment, in field 1, the polygon information generating circuit 2o is connected to the memory area 1.
In field 2, the C biaxial information written randomly in field 2-1 is sorted in ascending or descending order by sorting circuit 10, and in field 3, it is read out from memory area 12-3 by polygon display circuit 22. Become.

By the way, as is clear from FIG. 21, the polygon display circuit 20 of the embodiment reads Z-axis information C two fields past.

Therefore, from XYRAM16, sorting RAM1
It is necessary to read the data two fields before in synchronization with 2.

(b-2) XYRAM area switching The XYRAM 16 of this embodiment has three areas as shown in FIG.
It has memory areas 16-1.16-2.16-3.

Then, in accordance with the timing chart shown in FIG. 20, the memory area in the area 110 of this XYRAM 16 is accessed by the polygon information generation circuit 20.
The memory area in area 4 is accessed by the polygon display circuit 22, and the memory area in area 112 is not accessed from anywhere and is controlled to only hold information.

In the XYRAM 16 of the embodiment, each memory area 1
6-1.16-2.16-3 are formed so as to be controlled to be switched one by one in synchronization with each field switching while being rotated one by one.

Therefore, for example, the polygon information of C written from the polygon display circuit 20 to the memory area 16-1 in field 1 is held as is in field 2, and is read out by the polygon display circuit 22 in field 3. As a result, the polygon display circuit 22 reads out the polygon information C- of two fields past.

At this time, the read address of the XYRAM 16 is specified by an "index" paired with the two-axis coordinates of each polygon read from the sorting RAM 12, and each polygon information is sequentially read out in the sorting order of the two-axis coordinates.

In this way, the sorting circuit 10 of this embodiment
Polygon information of a plurality of polygons calculated and output from the polygon information generation circuit 20 for each field is sorted in ascending order based on the Z-axis coordinate within one field time, and output to the polygon display circuit 22. Can be done.

(b-3) Switching memory areas when there is a delay in writing screen information By the way, in principle, the polygon information generation circuit 20 completes writing of information for one screen within one field. Depending on the processing content, writing may not be completed within one field and may extend to the next field.

When such a write delay occurs, the sorting circuit 10 cannot switch the input memory area even when updating a field, and must wait for the switching until the next field update.

In this case, if switching of all memory areas is stopped, the pipeline delay will increase, so some kind of countermeasure is required.

For example, when updating from field 1 to field 2,
Assume that the write delay occurs and information "C" is written across both fields.

In this case, if no write delay occurs, "B", which is the information immediately before "C", is output in field 2.

However, if all area switching is stopped at the same time,
"A" is output across two fields, r13J
The output is delayed by one field.

In order to reduce such pipeline delay as much as possible, the sorting circuit 10 of this embodiment performs irregular area switching as described below when a write delay occurs.

■: Sorting RAM area switching In Figure 23,
An example of the area switching operation of the sorting RAM 12 when a delay in writing one screen worth of information "C" occurs when updating from field 1 to field 2 is shown. When switching from field 2 to field 3, area switching of memory areas 12-1 and 12-2 is stopped, and when switching from field 2 to field 3, memory areas 12-4 and 12-2 are stopped.
Stop area switching in step 3.

Note that the sorting between memory areas 12-2 and 12-4 performed in field 2 at this time is invalidated.

■: Area switching of XYRAM Also, FIG. 24 shows an example of the area switching operation of the XYRAM 16 when there is a delay in writing information "C" to the memory area 16-1 when updating from field 1 to field 2. In this case, when updating from field 1 to field 2, memory area 1
6-1 is stopped, and when updating from field 2 to field 3, switching of memory area 16-3 is stopped by -60=.

In this way, in the sorting circuit 10 of the embodiment,
If there is a delay in writing one screen worth of information to the memory area, the memory area is switched irregularly as shown in Figures 23 and 24 to minimize the delay due to pipeline processing. ing.

In this embodiment, the case where the area switching of the XYRAM 16 and the sorting RAM 12 is performed for each field has been described as an example, but the present invention is not limited to this, and the area switching may be performed every time the screen is updated. It is sufficient to form it.

For example, if the screen is updated every frame, every few frames, or every few fields, 1
Area switching may be performed every frame, every several frames, or every several fields.

(c) Memory map FIG. 25 shows the sorting RA used in this embodiment.
An example of the memory map of M12 and The circuit is configured to be accessed via a data bus.

In the figure, (1) is the input side memory map, (2)
represent the memory map on the output side.

In the following explanation, the polygon information of each polygon randomly output from the polygon information generation circuit 20 will be
01NO11, -t40. Give the number <n-1>. Further, Pr is arranged in descending order of priority for the polygon information of the polygon output in this way.

0, Pr, 1,...Pr, (gives the number n-1>).

Here, n represents the number of polygon information of a polygon displayed on one screen, and is set in the range of 0≦n≦1023 in the embodiment.

(C1) Memory map of XYRAM (common input and output) Figure 26 shows the memory map of one memory area of the XYRAM16, and the physical address of this memory area when viewed from the input side and output side is Both 00
It is in the range of 0011 to 3 F F F H.

This memory area is provided with a data write area of 16 words for each polygon.

FIG. 26 (2) shows a detailed memory map of the memory area given to one polygon. Nine words of the XY coordinates of one vertex are written, and the remaining seven words are empty.

(C-2) Memory map of the input side memory area of the sorting RAM FIG. 27 shows an example of the memory map of the input side memory area of the sorting RAM 12, and the two-axis coordinates at the center position of each polygon are as described above. like 1
It is given by 5 bits of data. For this reason, each of these Z-axis coordinates is written in a predetermined area of an even word in the memory area shown in the figure (an area of bits 0 to 14 of the even word). Also, the most significant bit of each even word (the area of bit 15 of the even word) is “
The "end flag" is configured to be writable.

Note that the memory map shown in FIG. 27 is
Comparing the memory map of YRAM, the input side sorting RAM and XYRAM have polygons of 0.1.2,
... It is understood that the information is in the same order in JIM of n-1.

Using this data arrangement, as mentioned above,
The starting address of the polygon information writing area of each polygon written in AM16 is defined as an index.

Then, as shown in FIG. 27, the sorting RAM 1
Every time the two-axis coordinate values of each polygon are written into the even words of the input side memory area 2, the indexes of the polygons are sequentially set in the odd words of the memory area.

As shown in FIG. 26, 16 words are allocated to the memory area of the XYRAM of this embodiment for writing polygon information of one polygon. Therefore, for example, the starting address of the polygon information writing area of the k-th polygon is given by 16.

Therefore, the index of the second polygon written in the memory area of the sorting RAM 16 becomes the address information for number 16.

(C-3) Memory map of the output side area of the sorting RAM FIG. 28 shows an example of the memory map of the output side memory area of the sorting RAM 12, and as shown in the figure, each polygon is The Z-axis coordinates of are written in Jl[ having the smallest value, that is, sorted in descending order of priority.

Here, the Z-axis coordinate value of each sorted polygon is written in the even number address of this memory area, and its index is written in the odd number address. Here, the polygon of Pr, k is NO, k- before sorting
Assuming that Pr, the index of the polygon of k is given by 16.

In the embodiment, since both k and - are given in 10 bits, - is given in the index information 16 as 14 bits. Furthermore, as shown in FIG. 26(2), since the XYRAM 16 writes each polygon information in units of 16 words, the lower 4 bits of the index are always 0.

In this way, in this embodiment, the Z coordinate is written to the even address of the sorting RAM memory area, and the index information is written to the odd address.Moreover, the end area (15 bits) is written to the address where the last Z coordinate or index is written. ) is written with the "end flag".

The polygon display circuit 22 then displays the "end flag" written in either an even address or an odd address.
By detecting this, it is possible to determine the final Z-axis information written in the memory area and move on to the next operation. By doing this, it is possible to reduce wasted processing time caused by reading out data in the empty area of the memory area, and to perform the sorting process at a higher speed.

Further, the polygon display circuit 22 normally performs sorting RA
The polygon information of each polygon is read from the memory area of M16 in the order pr, o, Pr, 1, -Pr, (n-1>), but in addition to this, the polygon information can also be read in the reverse order. In consideration of this point, the memory area of the embodiment is formed so that the "total number of polygons" is written in the final address.

Therefore, in the case of n=1023, the total number of polygons and the end flag are written together in the same word, as shown by the dotted line on the right side of FIG.

[Effects of the Invention] As explained above, the present invention has the effect of providing a simple and inexpensive sorting circuit that can sort a large amount of data at high speed based on its reference axis information. It can be used in a wide range of applications that require.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a preferred first embodiment of the sorting circuit according to the present invention, FIGS. 2 and 3 are flowcharts of sorting processing performed using the circuit shown in FIG. 1, and FIG. ~7th
The figure is an explanatory diagram showing an example of sorting a set of reference axis information consisting of 4-digit binary numbers, and Figures 8 to 10 are illustrations of sorting a set of reference axis information consisting of 3-digit ternary numbers. FIG. 11 is a block diagram showing a second preferred embodiment of the present invention; FIG. 12 is a block diagram showing a third preferred embodiment of the present invention; FIGS. 12 is a flowchart showing the operation of the embodiment shown in FIG. 16, FIG. 16 is a block diagram showing an embodiment in which the sorting circuit according to the present invention is applied to a three-dimensional information calculation circuit, and FIG. 18 is a block diagram showing a specific configuration of the polygon information generation circuit shown in FIG. 16; FIG. 19 is a three-dimensional conceptual diagram of an image displayed using the circuit shown in FIG. 16; FIG. 19 is a sorting circuit 10 shown in FIG. 20 is a timing chart showing a cycle steal for making the sorting circuit shown in FIG. 19 multi-vote, and FIGS. 21 and 22 are the sorting RAM and
An explanatory diagram showing the YRAM area switching operation, Figures 23 and 24 are sorting RA when a data write delay occurs in the polygon information generation circuit.
FIG. 25 is a conceptual diagram of the memory map of the XYRAM and sorting RAM used in the embodiment. FIG. 26 is a detailed diagram of the memory map of the XYRAM used in the embodiment. FIG. 27 28 is a detailed explanatory diagram of the memory map of the sorting RAM used in the embodiment, and FIGS. 29 and 30 are explanatory diagrams when floating point data is sorted using the apparatus shown in FIG. 1. . 10... Sorting circuit 12... Sorting memory 12-1.12
-2.12-3.12-4... Memory area 14... Sorter 16... Information memory 20... Polygon information generation circuit 22
... Polygon display circuit agent Patent attorney Yukio Fuse (1 other person) Fig. 2 Fig. 3 Fig. 4 mm3 mm2 mml m=0 regular r Rk Fig. 6 mm3 m-2m-1m expansion O o O Figure 7 Off ~I Country m=3 m=2 mml m=0 m-3m-2m-1m-0 o Ol and -I
Figure 22, Figure 23, Figure 24, Figure 25, Figure 28, Figure 29, Figure 30.

Claims (4)

[Claims] (1) A circuit that sorts a plurality of data based on predetermined reference axis information, which includes a sorting memory having at least two memory areas for writing reference axis information, and a set of memory areas stored in one memory area. The transfer process of searching for the value of a predetermined search digit of the reference axis information, classifying this set of reference axis information based on the searched value, and copying it to the other memory area in ascending or descending order is performed. Search digit 1 from the lowest digit to the highest digit
A sorting circuit comprising a sorter that repeatedly performs operations between both memory areas while shifting digits one by one, and sorting data based on reference axis information. (2) A circuit that sorts a plurality of data consisting of reference axis information and combination information thereof based on predetermined reference axis information, and includes an information memory in which combination information of each data is written, and reference axis information of each data. , a sorting memory having at least two memory areas in which combination information write addresses are written in pairs, and a set of reference axis information stored in one memory area of a predetermined search digit value. The reference axis information is searched and transferred to the other memory area in ascending or descending order while sorting this set of reference axis information and the paired combination information write address based on the searched values. A sorter that repeats between both memory areas while shifting the search digit one by one from the least significant digit to the most significant digit, and is a pairing combination when reading reference axis information from the sorting memory. A sorting circuit that sorts data based on reference axis information by reading combination information from an information memory based on an information write address. (3) Claims (2) applicable to the image synthesis device
In the described circuit, the information memory has at least three memory areas for data writing, data holding, and data output, which are switched each time the screen is updated, and the sorting memory has at least three memory areas for data writing, data holding, and data output. It has at least four memory areas used for writing, data sorting, and data output, and at least two of the memory areas are switched and used for data writing and data sorting each time the screen is updated. . A sorting circuit characterized in that the remaining at least two memory areas are used for data sorting and data output in a switching manner each time a screen is updated, and the calculated image information is sorted and output. (4) The sorting circuit according to any one of claims (2) and (3), wherein the reference axis information is composed of binary data.