JPH02223861A - Velocity signal detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a velocity signal having high accuracy by counting a rotational pulse signal in a sampling time, and thereafter, detecting and calculating a final pulse of the rotational pulse and a fraction interval existing in a final period of the sampling time. CONSTITUTION:A rotational pulse signal 11 inputted from an encoder of the outside is detected by a pulse counter 12, and the number of pulses Ni in a sampling time Z0 is counted and inputted to an output latch 13. A counter 14 detects a rotational pulse interval Z2, a final rotational pulse in the sampling time Z0, and a fraction interval Z1 existing in a final period of the sampling time Z0. Subsequently, Z1/Z2 is calculated by a divider 15, and inputted to the output latch 13. As a result, from the latch 13, a velocity signal V = Ni + Z1/Z2 is outputted as a digital velocity signal.

Description

DETAILED DESCRIPTION OF THE INVENTION a. Industrial Application Field The present invention relates to a speed signal detection circuit, and particularly to a speed signal detection circuit that can detect even decimal values below an integer value of a rotation pulse signal generated based on rotation, and can detect ripple-free rotation pulse signals. Concerning novel improvements for obtaining highly accurate speed signals.

b. Prior art There are various speed signal detection circuits of this type that have been used in the past, but a typical configuration is one that includes an encoder, etc., as shown in FIGS. 4 and 5. The rotation pulse signal 1a from the rotation pulse signal generator 1 is input to a differentiator 2, and the pulse edge of this rotation pulse signal 1a is differentiated by the differentiator 2.

The differential output 2a from the differentiating circuit 2 is integrated by an integrating circuit 3, and a speed signal 3a consisting of an analog signal is output.

C1 Problems to be Solved by the Invention Since the conventional speed signal detection circuit was configured as described above, the following problems existed.

In other words, since the pulse edge of the rotation pulse signal is detected and differentiated, ripples cannot be removed, as shown in Figure 5, and when applied to motors that require highly accurate speed control. This may involve incorrect control, making it impossible to obtain a ripple-free speed signal.

In addition, since the pulse edge is detected and differentiated by a differentiator circuit, the speed signal is obtained based only on the integer value of the rotation pulse signal, so for example, when the rotation speed of a motor etc. becomes extremely low, , the pulse interval became longer, reducing the accuracy of the speed signal.

The present invention has been made to solve the above-mentioned problems. In particular, the present invention can detect even decimal values below an integer value of rotation pulse signals generated based on rotation, and can also detect high-precision speed signals without ripples. An object of the present invention is to provide a speed signal detection circuit that obtains the following speed signals.

81 Means for Solving the Problems The speed signal detection circuit according to the present invention includes a control unit that outputs a rotation pulse signal consisting of a plurality of pulses based on rotation, and a control unit that outputs a rotation pulse signal consisting of a plurality of pulses based on rotation, and a control unit that outputs a rotation pulse signal consisting of a plurality of pulses based on rotation, and A pulse counter that detects the number of pulses, a fractional interval (Zl) existing between the last pulse in the sampling time (Zo) and the end (Zoo) of the sampling time (Zo), and a pulse interval (Z2) of the rotational pulse signal. ), and a divider connected to the counter.

e. Operation In the speed signal detection circuit according to the present invention, the fractional interval (Zl
) and a counter for detecting the pulse interval (Z2) of the rotation pulse signal, and a divider connected to this counter.
) by the pulse interval 1i (Z2),
A decimal value of the rotation pulse signal can be detected.

In addition, since the counting of the rotational pulse signals mentioned above is performed entirely by digital calculation processing, it is possible to obtain highly accurate speed signals without any problems caused by ripples during differentiation, which is required in the past. can be improved.

f. Embodiments Hereinafter, preferred embodiments of the speed signal detection circuit according to the present invention will be described in detail with reference to the drawings.

In addition, the same reference numerals are attached to the same or equivalent parts as in the conventional art and the explanation will be given.

1 to 3 are for showing the speed signal detection circuit according to the present invention, where FIG. 1 is a block diagram, FIG. 2 is an explanatory diagram showing the pulse detection state of the rotation pulse signal, and FIG. FIG. 2 is a block diagram showing an application example of the speed signal detection circuit.

10 in the figure is a clock 10a.
, the rotation pulse signal 11 LEADIIA and LAGIIB from an encoder (not shown) are inputted, and this control unit 10 inputs the sampling time Z to be detected.
Pulse lla~ of the rotation pulse signal 11 within o
It has a pulse counter 12 that counts the number of llf.

An encoder pulse counter 1 is connected to the control unit 10, and the encoder pulse counter 1 continuously counts pulses lla of the rotational pulse signal 11 and inputs the encoder signal 1a to the output latch circuit 13. .

A counter] 4 is connected to the control unit 10, and as shown in FIG. the fractional interval Z that exists between them, and the pulse interval z of the rotation pulse signal 11
2.

The fractional interval Z which is the output signal from the counter 14
1 and the pulse signal interval z2 are input to a divider 15 connected to the counter 14, and the command signal 10a from the control section 10 is input to the divider 15.

In the divider 15, a signal 15a obtained by dividing the fractional interval z1 by the product is input to the output latch circuit 13.

Another command signal 10b from the control section 10 is input to the output latch circuit 13, and output control of various signals latched by the output latch circuit 13 is performed.

The speed signal detection circuit 20 according to the present invention is configured as described above, and its operation will be explained below.

First, a rotation pulse signal 11 inputted from an external encoder (not shown) is detected by a pulse counter 12, and the number of pulses Ni within a sampling time Zo is counted and inputted to an output latch circuit 13.

The fractional interval z1 and the pulse interval z2 detected by the counter 14 are inputted to the division processing 13 by the divider 15, and as a result, the speed signal V is outputted as a binary signal as ■ = nil degree signal. .

Therefore, this speed signal (■) is obtained entirely by digital calculation processing, and is also detected in fractional units of integers or less of each pulse number, so extremely accurate speed detection is possible. It is possible to improve speed detection accuracy when rotating at a habitual speed.

Further, as an application example of the speed signal detection circuit 20 described above,
As shown in FIG. 3, it can be applied to a motor encoder 30.

That is, in FIG. 3, a motor indicated by the reference numeral 31 is provided with an encoder 33 via a rotating shaft 32, and a speed command 35 sent via an adder/subtractor 34 is sent to the motor 31. , are input via the speed control amplifier 36.

The rotation pulse signal 11 from the encoder 33 is input to the speed signal detection circuit 20.
The above-mentioned speed signal V is inputted to the adder/subtractor 34 via the D/A converter 37 as an analog voltage signal 20a.

Therefore, in the above-mentioned motor encoder 30, the extremely high-precision speed signal (2) obtained from the speed signal detection circuit 20 is inputted to the adder/subtractor 34 as an analog voltage signal 20a, and is output from the highly precisely controlled speed control amplifier 36. The rotation of the motor 31 is controlled to a constant value by a drive signal 36a.

g2 Effects of the Invention Since the speed signal detection circuit according to the present invention is configured as described above, it is possible to obtain the following effects.

That is, in addition to the number of pulses in the sampling time, the fractional interval existing between the end of the sampling time and the final pulse is used to show the detection circuit to obtain a decimal value. FIG. 2 is an explanatory diagram showing the pulse detection state of the rotation pulse signal, FIG. 3 is a block diagram showing an application example of the speed signal detection circuit, and FIGS. 4 and 5 are:
This shows a conventional speed signal detection circuit, with FIG. 4 being a block diagram and FIG. 5 being a waveform diagram.

10 is a control unit, 11 is a rotation pulse signal, lla to llf
is a pulse, zo is a sampling time, 11 and d are final pulses, 12 is a pulse counter, Zol is a terminal period, Zl is a fractional interval, Z2 is a pulse interval, 14 is a counter, and 15 is a divider.

can be improved.

Further, since the counting of the rotational pulse signals mentioned above is entirely performed by digital calculation processing, a highly accurate speed signal can be obtained without any trouble caused by ripples during differentiation, unlike in the conventional method.

[Brief explanation of the drawing]

1 to 31 are speed signals according to the present invention. Nt Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] a control unit (10) that outputs a rotation pulse signal (11) consisting of a plurality of pulses (11a to 11f) based on rotation;
a pulse counter (1) that detects the number of pulses (Ni) of the rotation pulse signal (11) within the sampling time (Z_o) to be detected;
a counter (14) for detecting a fractional interval (Z_1) existing between the final pulse (11d) in o) and the end (Z_o_1) of the sampling time (Z_o) and a pulse interval (Z_2) of the rotation pulse signal (11); ) and a divider (15) connected to the counter (14), and the divider (15) divides the fractional interval (Z_1) by the pulse interval (Z_2). , a speed signal detection circuit characterized in that a decimal value of the rotation pulse signal (11) is detected.