JPH02222562A - Chip carrier - Google Patents

Abstract

PURPOSE:To accurately mount a chip carrier preventing it from deviating positionally when the chip carrier is mounted on a printed board with a component mounting device by a method wherein the external dimension of the chip carrier is made smaller than that of a sealing ring joined to the upside of the chip carrier. CONSTITUTION:Two or more pieces of ceramic green sheets are laminated and burned, and the burned ceramic laminated body is divided along lines which connect castellated holes 2 to obtain a chip carrier 1, a sealing ring 4 highly accurate in external dimension is joined to the upside of the chip carrier 1, and an external dimension L1 of the chip carrier 1 is made smaller than that L2 of the sealing ring 4. By this setup, the external dimension of a package becomes equal to that of the sealing ring even if flashes occur at the division area of the chip carrier 1 or the chip carrier shrinkes at burning, so that the package is improved in dimensional accuracy as a whole. Therefore, a chip carrier becomes accurate in mounting position when it is mounted on a printed board with a component mounting device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a chip carrier as a type of IC package.

(Prior art) Surface-mounted IC with IC1 and other elements mounted on the surface
Ceramic chip carriers as packages are known for a long time.

Fig. 3 is a plan view of a conventional ceramic chip carrier, and Fig. 4 is a cross-sectional view of the same ceramic chip carrier. You can get it by doing that.

That is, the fired ceramic body 10 has castellation holes for dividing and separating the individual ceramic chip carriers 11! 2... are each ceramic layer 10a, 10b,
It is formed to penetrate through 10c. Further, a seal ring 13 is soldered to the upper surface of the upper ceramic layer 10a, and a lid seals the inside of the chip carrier 11 via this seal ring 13! Install 4.

(Problems to be Solved by the Invention) In the conventional chip carrier 11 described above, its external dimension L1 is larger than the external dimension L2 of the seal ring 13. As described above, the chip carriers 11 are separated into individual pieces by splitting the fired ceramic body 10 along the line (imaginary line) connecting the castellation holes 2..., so the dimensional accuracy of the separation surface is low and there is no chipping. and Paris, etc. Furthermore, the shrinkage when firing the ceramic green sheet is large and the external dimension L of the chip carrier 11 is large.
1 is not accurate.

On the other hand, the chip carrier 11 on which ICs and the like are mounted is automatically mounted onto a printed circuit board by a component mounting machine. However, since the component mounting machine grips and mounts the chip carrier by its outer shape, if the outer dimensions are inaccurate, the mounting position will also be inaccurate.

(Means for Solving the Problems) In order to solve the above problems, the present invention makes the external dimensions of the chip carrier slightly smaller than the seal ring bonded to the upper surface of the chip carrier.

(Function) The seal ring is made of metal such as Kovar and has highly accurate external dimensions.By making the external dimensions of the chip carrier smaller than the external dimensions of the seal ring,
The dimensional accuracy of the entire package is improved.

(Example) Embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 1 is a plan view showing a chip carrier according to the present invention in a state before separation, and FIG. 2 is a longitudinal sectional view of the chip carrier.

Chip carrier 1 includes a plurality of ceramic layers 1a.

The ceramic layer 1a consists of lb and lc.

1b and 1c are obtained by laminating a plurality of ceramic green sheets and then firing them.

Further, a castellation hole 2 is formed passing through each ceramic layer ia, 1b, 1c, and a seal ring 4 made of metal such as Kovar and having a highly accurate external dimension L2 is formed on the upper surface of the upper ceramic layer 1a by brazing material 3. After bonding and mounting an element 5 such as an IC on the top surface of the chip carrier 1, a metal or ceramic lid 6 is bonded onto the seal ring 4 to seal the inside.

Furthermore, among the ceramic layers, the lower ceramic layer 1
Electrode pad 7 is formed on the back side of c by vapor deposition, metallization, etc.
is formed, and an element 5 is formed on the upper surface of the intermediate ceramic layer 1b.
Further, a metal layer 9 for connecting the seal ring 4 to the ground is formed on the inner peripheral surface of the castellation hole 2 by metallization.

Here, a portion 18 between the chip carriers 1, 1 is a portion that is removed as a surplus portion, and by dividing and removing this portion 1, each chip carrier 1, 1 is separated. Further, the outer dimension L1 of the chip carrier 1 is smaller than the outer dimension L2 of the seal ring 4. However, if the external dimension L1 of the chip carrier 1 is made too small, it will be difficult to bond the seal ring 4 and it will be disadvantageous in terms of strength.
The difference ΔL between and Ll shall be within 0.2 mm on one side.

(Effects of the Invention) As explained above, according to the present invention, the external dimensions of the chip carrier to which the seal ring is bonded to the upper surface are made smaller than the external dimensions of the seal ring, so that no cracks are formed on the dividing surface of the chip carrier. Even if the chip carrier shrinks during firing or firing, the external dimensions of the package will be the same as that of the seal ring, so when the chip carrier is mounted on the printed circuit board by a component mounting machine, it will be difficult to misalign, and it will be accurate. It can be installed on.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a chip carrier according to the present invention, Fig. 2 is a longitudinal cross-sectional view of the same chip carrier, Fig. 3 is a plan view of a conventional chip carrier, and Fig. 4 is a longitudinal cross-section of the conventional chip carrier. be. In addition, 1 in the drawing is a chip carrier, la, lb. 1c is a ceramic layer, 4 is a seal ring, 5 is an element, L
l is the external dimension of the chip carrier, and Ll is the external dimension of the seal ring.

Claims (1)

[Claims] In a chip carrier obtained by laminating and firing multiple ceramic green sheets and separating the fired ceramic laminate along a line connecting castellation holes, the top surface of this chip carrier has highly accurate external dimensions. What is claimed is: 1. A chip carrier having a seal ring joined thereto, and an external dimension of the chip carrier being set smaller than an external dimension of the seal ring.