JPH02222332A - Phase detecting circuit - Google Patents

Abstract

PURPOSE:To make the circuit scale small by inputting a pulse position by an address in a frame, and using in common a maximum value detecting part, a minimum value detecting part and an arithmetic part, even when plural pieces of groups containing a terminal group exists. CONSTITUTION:Pulses from terminals A-D are stored as addresses in a frame in address memories 2-5, respectively, and the maximum value and the minimum value of these addresses are detected by a maximum value detecting part 6 and a minimum value detecting part 7, respectively. Subsequently, in an arithmetic part 8, an operation is executed, based on data from the maximum value detecting part 6 and the minimum value detecting part 7, and (the maximum value - the minimum value)/2 is calculated. On the other hand, an output of the arithmetic part 8 and an output of an address counter 1 are inputted to an EOR gate 9. Accordingly, at the time point when an output of an address counter of the next frame coincides with an output of the processing arithmetic part 8, a pulse of a LOW level is outputted. In such a way, even at the time of deriving, for instance, the center phase of plural groups, the circuit scale does not become large.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 4 and 5) Means for solving the problem to be solved by the invention (Figure 1) Working examples (Figures 2 and 3) Effects of the invention [Summary] Regarding a phase detection circuit that detects the phase at a specific position between multiple pulses, the phase of the pulse is received as an address value within a frame, and the calculation is performed to detect the phase at a specific position. A phase detection circuit whose purpose is to output a phase and detects a specific phase between pulses output at specific different timings includes a plurality of terminal groups into which pulses generated at specific positions are input, and address counter means for generating an address to indicate the position within the frame; address holding means for receiving the output of the address counter means and holding each intra-frame address from the terminal group; maximum value detection means for detecting the maximum value of the address values held in each address holding means; minimum value detection means for detecting the minimum value of the address values held in each address holding means; and a specific value intermediate between the maximum value and the minimum value. A phase detection circuit comprises a calculation means for calculating , and a coincidence detection means for detecting coincidence between an output from the calculation means and an output from the address counter means.

C. Field of Industrial Application] The present invention relates to a phase detection circuit, and more particularly to a phase detection circuit that can compare the phases of a plurality of pulses and determine, for example, their center phase.

(Prior Art) In a data processing device, there are cases where it is required to find the center phase of a plurality of pulses having different phases.

FIG. 4 shows such an example, in which pulses are output from four subscriber lines A, B, and C1D at the timing shown in FIG. 4(A). That is, from the concave line A, at the time of frame address 2, from line B, similarly at the time of frame address 5, and from line C
It is assumed that a pulse is emitted from the line at address 10 in the frame, and from address 1 in the frame from the line. As shown in FIG. 4(B), when a group of lines like this are connected via an OR gate, a multiplexed pulse train is obtained, but it is required to find the center position of this pulse train within the frame. Sometimes.

FIG. 5 shows a conventional example of determining the center phase of a plurality of pulses having different phases.

FIG. 5 shows a case where multiplexed outputs of four lines are used as inputs. In the figure, 51 is a quaternary counter, and 52 is a flip-flop (F.

53 is a counter, 54 is a shift register, and 55 is an EOR (exclusive OR) gate.

Now, when the multiplexed pulse shown in FIG. 4 is input to the terminal [A] in FIG. 5, the quaternary counter 51 counts the pulse and after counting the fourth pulse, F, F, 5
Output a reset output to the reset terminal of 2. On the other hand, F, F,
The multiplexed pulse from terminal [A] is directly input to the 520 cent terminal, and is set by the first pulse. Therefore, signals that rise at the first pulse and fall at the last pulse are output from F, F, and 52.

Since the outputs of F, F, and 52° are input to the enable terminal of the counter 53, the counter 53 counts the clocks during the period from the first pulse to the last pulse of a. This counter output is input to the shift register 44, and half of the counter value is calculated here. The output of this shift register 54 is input to the EOR 55, and the output of the counter 53 is input directly to the EOR 55.

The shift register 54 outputs 5 as the center phase of the first frame, for example, in the example of FIG.
When the output of 3 becomes 5, a low level pulse as shown is output to terminal [C]. By this, terminal A
,B,C,,D, the center phase between the pulses can be found.

[Problem to be solved by the invention]

However, in the conventional example described above, when there are multiple sets of pulse groups whose phases should be compared, a circuit network for determining the center phase of each set is required as many as the number of pulse groups, which increases the circuit scale. There is a problem with this.

The present invention has been made in view of these points,
It is an object of the present invention to provide a phase detection circuit that does not increase the circuit scale even when determining, for example, center phases of a plurality of sets.

[Means to solve the problem]

FIG. 1 is a basic block diagram of the present invention.

In FIG. 1, 1 is an address counter which receives frame pulses and clocks and outputs the position of each pulse as an address within the frame. 2.3.4.5 is an address memory for storing addresses within the frame of pulses input from terminals A, B, C, and D, respectively.

6 is a maximum value detection unit that finds the maximum value of the address of the pulse manually input from terminals A, B, C, and D; 7 is the terminal A;
This is a minimum value detection unit that finds the minimum value of the addresses of pulses input manually from B, C, and D.

8 is an arithmetic unit which calculates 1/2 of the difference between the maximum address and the minimum address from the maximum value detection unit 6 and the minimum value detection unit 7. Reference numeral 9 denotes an EOR gate, which receives the output of the arithmetic unit 8 and the output of the address counter 1 as inputs.

[Effect]

Pulses from terminals AXB, C, and D are stored in the address memory 2.3.4.5 as addresses within the frame, and the maximum value and minimum value of these addresses are respectively stored in the maximum value detection section 6 and the minimum value. It is detected by the value detection section 7. Then, the calculation section 8 performs calculations based on the data from the maximum value detection section 6 and the minimum value detection section 7, and calculates (maximum value - minimum value)/2. On the other hand, the output of the arithmetic unit 8 and the output of the address counter 1 are input to the EOR gate 9.

Therefore, when the output of the address counter of the next frame matches the output of the arithmetic unit 8, a LOW level pulse as shown is output. For example, in the example shown in FIG. 4(B), the address counter l
When counts 5, the EOR gate 9 obtains a match with the calculated value of the calculation unit 8 which has already been calculated. This pulse is output at half the maximum and minimum addresses in the frame stored in each address memory, so it ends up being output at terminals A, BXC, and D.
A LOW level pulse will be output at the center position of the pulse from.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which three comparators 6162.63 are used as the maximum value detection section 6, and three comparators 71.72.73 are used as the minimum value detection section 7.
is used.

Comparator 61 compares the addresses stored in address memory 2.3 and outputs the larger one, and similarly comparator 62 compares the addresses stored in address memory 4.5 and outputs the larger one. Output. Furthermore, the comparator 63 compares the outputs of the comparators 61 and 62, and outputs the address of the larger one. Therefore, the output of the comparator 63 is the largest address among address memories 2-5.

Further, the comparator 71 compares the addresses stored in the address memory 2.3 and outputs the smaller one, and similarly the comparator 72 compares the addresses stored in the address memory 4.5. Output the smaller one. Furthermore,
Comparator 73 compares the outputs of comparator 71 and comparator 72,
Output the larger address. Therefore, the output of the comparator 73 is the smallest address among address memories 2-5.

The calculation unit 8 receives the outputs of the comparators 63 and 73 and calculates (maximum value - minimum value)/2.

The subsequent operation is as described in conjunction with FIG. 1, and when the count value of the arithmetic unit 8 matches the output of the next address counter 1, a pulse indicating the phase position is output.

It goes without saying that by changing the calculation in the calculation unit 8, it is possible to obtain not only the center phase but also various positions such as 1/4. Also, there are only 4 terminals,
The same applies to other numbers such as 5, 6, etc.

FIG. 3 shows an example where there are a plurality of terminal groups whose central phases are to be determined. This figure 3 shows group 1 (C
I), terminals A, B, C, D are connected to group 2 (G
2) shows the case of two terminal groups including terminals E, FSG, and [I.

Figure 3 (A) shows the case where pulses from each group are mixed in the frame, and Figure 3 (B) shows the case where the pulses from each group are divided into groups. ing.

Figure 3 (A) shows each group (A, B, C, D), (E,
A case where FSG, H) -1 pulses are mixed will be explained. In order to recognize this group, the timing generation section 30 needs the following information. The phase of this group is determined by the frame format, and timing is created to recognize the phase.

This will be explained below using a specific example shown in the lower part of FIG. 3(A).

Assume that in a frame in which seven groups coexist, the allocation of the groups is defined by the frame format as shown in the figure. (Addresses within the frame are 1 to N) At this time, timing is created by the timing creation section 30 in order to identify the seven groups within one address.

The timing generation unit 30 cannot predict where each pulse will be input from addresses 1 to N. The embodiment shown in FIG. 3(A) calculates the value of the input address of each pulse and detects the center phase.

Reference numerals 31 and 32 denote an extraction memory section, which stores the data of group 1 in the extraction memory section 31 and the data of group 2 in the extraction memory section 32, and reads them out in a time-sharing manner.
It is sufficient to input it to the comparison section at the next stage. Note that 33 is a multiplexer.

However, Fig. 3(A) is an example of the circuit required when each pulse input terminal is provided individually, and Fig. 3(B)
is an example of a circuit in which each pulse is time-division multiplexed and there are four input terminals.

The output from the multiplexer 33 in FIG. 3(A) corresponds to the four inputs in FIG. 3(B).

Next, the example shown in FIG. 3(B) will be explained. in this case,
As shown in the frame format, the pulses from each group are divided, so each group is connected in parallel to the phase detection circuit, and the output is time-divided according to the input timing of each group. Just do it.

In FIG. 3(B), 35 indicates the entire phase detection circuit according to the present invention explained in FIGS. 1 and 2, and includes an address memory section 36, a comparison section 37, and an operation section 38 This is shown schematically as follows.

It goes without saying that the input side may be switched in time division according to the input timing of each group, if necessary.

This allows the maximum value detection section, the minimum value detection section, and the calculation section to be used in common for each group.

In the above description, an example in which the center phase is determined and an example in which the number of input terminals is four are described, but the invention is of course not limited to these.

〔Effect of the invention〕

As described above, according to the present invention, even when a pulse position is input as an intra-frame address and there are multiple groups including terminal groups, the maximum value detection section, the minimum value detection section, and the calculation section can be shared. This allows the circuit scale to be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the phase detection circuit of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention; FIG. 3 is a diagram showing an example of having multiple terminal groups; FIG. 4 is a diagram showing an example of a pulse train, FIG. 5 is a diagram showing a conventional example. l ・Address counter 2. 3. 4. 5.--address memory 6-Maximum value detection section 7-・Minimum value detection section 8.- Arithmetic section 9...EOR gate

Claims (1)

[Claims] In a phase detection circuit that detects a specific phase between pulses output at specific different timings, a plurality of terminal groups (A, B, C,
D...), address counter means (1) for generating an address to indicate the position of the pulse within the frame, and receiving the output of the address counter means (1) for each frame from the terminal group address holding means (2, 3, 4, 5...) for holding the addresses within, maximum value detection means (6) for detecting the maximum value of the address values held in each address holding means, and each address holding means (6) for detecting the maximum value of the address values held in each address holding means. minimum value detection means (7) for detecting the minimum value of the address values held in the means; and calculation means (7) for calculating a specific value intermediate between the maximum value and the minimum value.
8), and coincidence detection means (9) for detecting coincidence between the output from the calculation means (8) and the output from the address counter means (1).
A phase detection circuit characterized by comprising: