JPH02222285A - High vision-ntsc converter - Google Patents

Abstract

PURPOSE:To attain efficient image reception while improving the vertical resolution in the case of receiving a High Vision signal by displaying the High Vision signal whose aspect ratio is 16:9 on a cathode ray tube. CONSTITUTION:The converter is provided with a conversion circuit 12 converting a scanning line number and a field frequency of the High Vision signal into a scanning line number and a field frequency of a MTSC signal and a deflection processing circuit 16 supplying a deflection current to a deflection yoke of a cathode ray tube whose aspect ratio is 4:3 and controlling the vertical amplitude based on control information. In the case of receiving a nigh Vision signal, the vertical amplitude of the deflection circuit is reduced to 3/4 and deflected. Since the interval of the scanning lines is reduced to 3/4 in comparison with a conventional vertical amplitude, the aspect ratio of the pattern displayed on the cathode ray tube whose aspect ratio is 4:3 is increased to 16:9. Thus, the substantial vertical resolution is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a high-definition-NTSC conversion equipment for receiving high-definition broadcasting on an NTSC receiver.

(Prior Art) In recent years, television systems (high-definition systems) have been developed in which the aspect ratio has been expanded from 4:3 of conventional television systems (for example, NTSC system) to 16:9.

When receiving high-definition broadcasting on an NTSC receiver, the number of scanning lines is different, so it is not possible to receive the image as is, but it is possible to receive the image by adding a scanning line conversion circuit.

However, even in that case, the aspect ratio of the cathode ray tube screen of an NTSC receiver is different from the aspect ratio of the image of high-definition broadcasting, so the NTSC
Either cut the left and right sides of the high-definition broadcast image on the CRT screen, or cut the left and right sides of the image as shown in Figure 4 (b), and instead cut the top and bottom parts of the image (usually There are methods such as adding a black color to the image and outputting the image.

FIG. 5 shows an example of a scanning line number conversion circuit that converts 1125 scanning lines of a high-definition signal to 525 scanning lines of an NTSC signal.

In FIG. 5, a high-definition signal supplied to an input terminal 1 is converted into an 8-bit digital signal by an A/D converter 2, and then sent to a scanning line conversion memory 3 and a synchronization generation circuit 4.
It's gone to zero. The synchronization generation circuit 4 detects a synchronization signal in the high-definition signal and generates various signals such as a clock based on the synchronization signal. The synchronization of each scale signal output from the synchronization generating circuit 4 matches the high-definition signal. In the scanning line conversion memory 3, the number of scanning lines in one frame can be reduced to 1 by changing the writing speed and reading speed.
Convert from 125 to 525.

After scanning line conversion, a two-dimensional filter 5 removes aliasing due to high-frequency components of the signal, and a D/A converter 6 converts the signal into an analog signal, which is output to an output terminal 7.

After such scanning line conversion, field frequency conversion is performed, and then aspect ratio conversion is performed. Field frequency conversion is performed using the same principle as a frame synchronizer, converting 60Hz of a high-definition signal to 59.94H2 of an NTSC signal.

By the way, in converting the aspect ratio, the method shown in Fig. 4 (b
), if you try to output all the horizontal images of a high-definition signal, there will be areas (black) with no images at the top and bottom of the screen. At this time, if the beam is deflected with the same vertical amplitude as in NTSC broadcasting, the scanning line will scan to areas where there are no upper and lower images, resulting in unnecessary deflection. Furthermore, since the number of scan lines in the picture area is further reduced, the actual vertical resolution is reduced.

(Problems to be Solved by the Invention) As mentioned above, conventionally 1. When receiving high-definition broadcasting on an NTS C receiver, if you perform scanning line number conversion, field frequency conversion, and aspect ratio conversion, and try to display the image as shown in Figure 4 (b), the top and bottom of the screen There is a problem in that the scanning line scans into areas where there is no image, resulting in unnecessary deflection and a reduction in substantial vertical resolution.

The present invention is intended to eliminate the above problem and
It is an object of the present invention to provide a high-definition to NTSC conversion device that can efficiently receive a high-definition signal while increasing vertical resolution when a receiver receives a high-definition signal.

[Structure of the Invention] (Means for Solving the Problems) The high-definition to NTSC conversion device of the present invention converts the number of scanning lines (1125) and field frequency (60H7) of a high-definition signal supplied as input to that of an NTSC signal. Number of scanning lines (525) and field frequency (59,
94Hz), a cathode ray tube with an aspect ratio of 4:3, and a deflection circuit capable of supplying a deflection current to the deflection yoke of the cathode ray tube and controlling the vertical amplitude based on control information. a video circuit that supplies the NTSC signal from the conversion circuit to the cathode ray tube as a video output; and a video circuit that detects that the conversion circuit receives a high-definition signal and reduces the vertical amplitude to 3/4 of the normal amplitude. and a control means for supplying control information for deflection to the deflection circuit, and is characterized in that a high-definition signal with an asbestos ratio of 16:9 is projected on the cathode ray tube.

(Function) In the present invention, when receiving a high-definition signal, by reducing the vertical ml amplitude of the deflection circuit to 3/4 and deflecting, the interval between scanning lines can be reduced compared to the case of normal vertical amplitude. Since the ratio is 3/4, the aspect ratio of the screen projected on a cathode ray tube with an aspect ratio of 4:3 can be set to 16:9, and the substantial vertical Q degree can be increased.

(Example) Hereinafter, the present invention will be explained based on the example shown in the drawings.

FIG. 1 shows high-definition-NTSC conversion 4! according to an embodiment of the present invention. ! FIG. 3 is a block diagram showing an i location.

In this figure, from the input terminal 11 to the scanning line conversion circuit 12
A high-definition signal is supplied to the

The scanning line conversion circuit 12 has the function of converting the number of scanning lines and converting the field frequency, and converts a high-definition signal with 1125 scanning lines and a field frequency of 60H2 to an N signal with 525 scanning lines and a field frequency of 59.94Hz.
Convert to TSC signal.

At the same time, the scanning line conversion circuit 12 operates in two image output modes (FIG. 4(a),
It has a function of outputting a control signal corresponding to the method shown in (b)). That is, the scanning line conversion circuit 12
has the function of outputting a video signal having the number of scanning lines and field frequency of the NTSC system, and also has the function of outputting a control signal in accordance with switching of the image output system.

The NTSC video signal from the scanning line conversion circuit 12 is supplied to a cathode ray tube 14 having an aspect ratio of 4:3 via a video circuit 13 constituting a video output stage. The part surrounded by broken lines indicates the part corresponding to the NTSC receiver.

The control signal from the scanning line conversion circuit 12 is a logic H signal in the case of the image output method shown in FIG. 4(a), for example.
In the case of the method shown in FIG. 4(b), it is a logical level signal. This control signal is supplied to the CPU of the microcomputer 15, and the microcomputer 15 creates vertical amplitude information based on this control signal and uses a deflection processing circuit (D P L
J: Deflection Processing
(Abbreviation for Unit) 16. Microcomputer 15
When the control signal is at H level, the Lumi amplitude information transferred to the deflection processing circuit 16 has a normal amplitude of 5, which corresponds to normal NTSC broadcast reception. Also, the fourth
When the microcomputer 15 detects an L level control signal when the method corresponding to figure (b) is selected, the microcomputer 1
5 transfers information for reducing the amplitude to 3/4 as vertical amplitude information to the deflection processing circuit 16. The deflection processing circuit 16 generates a vertical deflection signal corresponding to the vertical amplitude information from the microcomputer 15 and supplies it to the deflection output circuit 17. The deflection output circuit 17 includes a vertical amplification and a vertical output circuit, and supplies a vertical deflection current to the deflection yoke of the cathode ray tube 14. NaJ
3. The deflection output circuit 17 includes a horizontal output circuit, and supplies a horizontal deflection current to the deflection yoke of the cathode ray tube based on a horizontal deflection signal supplied from a horizontal deflection circuit (not shown).

In this way, when using the image output method shown in FIG. 4(b), the cathode ray tube 14 of the television receiver (aspect ratio 4
In 3), the vertical amplitude becomes 3/4, and the spacing between the scanning lines is reduced to 3/4 compared to the case of normal vertical amplitude. Therefore, on a cathode ray tube with an aspect ratio of 4:3, the picture can be displayed reduced to 3/4 in the vertical direction, and the picture aspect ratio can be set to 1620, which can match the aspect ratio of high-definition broadcasting. can.

FIG. 2 shows the configuration of main parts of the deflection processing circuit 16, in which numerals 21 to 26 indicate circuits within the deflection processing circuit, and 15
a1. 1' and 2 indicate the CPUs in the microcomputer 15.
4 to 26 are PWM (Pulse Width Nod
ulation) constitutes a circuit. In this figure, the CPU 15a of the microcomputer 15 includes a scanning line conversion circuit 1.
The control signal from J2 is supplied to J3, and the CPU
15a is the vertical amplitude information corresponding to the control signal.
PU interface (CP (written as J I/F) 21
The deflection amplitude data is provided to the memory 22 through. The memory 22 outputs deflection amplitude data Dv corresponding to the vertical amplitude information and supplies it to the integrator 23. Integrator 23 is adder circuit 2
It is composed of aa and a delay circuit 23b. The n delay circuit 23b operates at the timing of the clock fC, and is cleared by the vertical period signal v, at which time the output data of the 8 pits becomes 0'°. After clearing, the output of the integrator 23 becomes the deflection amplitude data Dv at the first clock "C", and the output becomes □v+□v-2Dv at the next clock. That is, the output of the integrator 23 becomes the deflection amplitude data Dv. The output of the integrator 23 increases by Dv every time the clock fC starts.The output of the integrator 23 is connected to the input terminal of the counter 24 (DATA
INPUT). Counter 24. counter 2
5. The flip-flop 26 constitutes a PWM circuit, and the counters 24 and 25 operate based on the clock fc. Clock fc is supplied to the clock terminal (GK) of counter 24,25. The carry terminal of the counter 25 is connected to the load terminal of the counter 24, and the carry of the counter 25 is J! I! When the H level is reached, the counter 24 integrates the ? Load the output data of lI23. Further, the carry-1 terminal of the counter 25 is connected to the reset terminal (R) of the flip-flop 26, and when the carry of the counter 25 is [(level), the flip-flop 2
Reset 6. At this time, PWM signal 1 (PWH0t
lT) i, becomes a logic L level. The carry terminal of the counter 24 is the set terminal (S) of the flip-flop 26.
is connected to. Load fil of counter 24 (i.e.
When the integrator 23 output) is small, the key 11 of the counter 24
The timing of the read is delayed, and the load 1 of the counter 24 is delayed.
As the correction becomes larger, the carry timing of the counter 24 gradually becomes earlier. Therefore, the timing for setting the flip-flop 26 becomes progressively earlier as the output of the integrator 23 increases. As a result, flip-flop 2
As the output of 6, a PWM signal (pulse width modulation signal) having a short H level period in the first half of the vertical period and a long H level period in the second half is obtained. Then, by integrating this PWHout signal, it is converted into a sawtooth wave signal, which is an analog signal, and sent to the vertical amplification stage in the deflection output circuit 17.

In the above circuit, the vertical amplitude is adjusted by changing the width plane amplitude data in the memory 22 to change the PWHou signal.

Figure 3 shows the timing of each part of the signals in Figure 2.
(a) shows the vertical period signal @V, (b) shows the integrator 23
shows the output of Further, (C) shows the carry of the counter 25, and (d) shows the carry of the counter 24. (e
) is the PWHOut signal. When the integrator 23 output is small, the carry timing of the counter 24 is delayed,
Set the flip-flop 26 (PWHout signal to H)
level), the counter 25 carry immediately)
” level, so it is reset (P14HOut signal is set to L level). When the output of the integrator 23 is large, the carry of the counter 24 immediately goes to F] level, so the output of the flip-flop 26 (1118 out signal)
The H level period becomes longer. That is, as shown in FIG. 3(0), the duty of the pulse of the PMH0Llt signal changes depending on the output of the integrator 23. flip 70 tube 2
The P14Hout signal output from 6 is integrated by a resistor and a capacitor, converted into a sawtooth wave signal, and input into the vertical amplifier circuit.

In the above explanation, the high-definition picture is referred to as (a) in Figure 4.
) or (b) to display an image on an NTSC receiver.
Switching to and from Cfi transmission can be performed in the same manner.

Furthermore, the embodiment shown in FIG.
DTV (Improved Definition)
Although the block configuration of the present invention is shown in FIG. is possible.

[Effects of the Invention] As described above, according to the present invention, when a high-definition signal is received by an NTSC receiver, the vertical resolution can be increased while converting the aspect ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a high-definition to NTSC conversion device according to an embodiment of the present invention, FIG. 2 is a block diagram showing main parts of the deflection processing circuit shown in FIG. 1, and FIG. 3 is a block diagram showing various parts of the circuit shown in FIG. 2. FIG. 4 is an explanatory diagram illustrating a method of outputting a high-definition signal to a cathode ray tube of an NTSC receiver, and FIG. 5 is a block diagram showing a conventional scanning line number conversion circuit. 11... High-definition signal input terminal, 12... Scanning line conversion circuit, 13... Video circuit, 14... Braun tube, 15... Microcomputer, 16... Deflection processing circuit,
17... Deflection output circuit. 'y-enemy

Claims (1)

[Claims] A conversion circuit that converts the number of scanning lines and field frequency of a high-definition signal supplied as input into the number of scanning lines and field frequency of an NTSC signal, a cathode ray tube with an aspect ratio of 4:3, and this cathode ray tube. a deflection circuit capable of supplying a deflection current to the deflection yoke of the converter and controlling the vertical amplitude based on control information; a video circuit that supplies the NTSC signal from the converter circuit as a video output to the cathode ray tube; control means for detecting that the circuit has received a high-definition signal, and supplying control information to the deflection circuit to reduce the vertical amplitude to 3/4 of the normal amplitude and deflect the signal; Hi-Vision-NT characterized by displaying Hi-Vision signals with an aspect ratio of 16:9
SC conversion device.