JPH02222280A - Electronic still camera equipment - Google Patents

Abstract

PURPOSE:To optionally use even a recording medium using various semiconductor memories by providing a timing control means reading a data from a 1st storage element of the recording medium, converting the timing into a write timing of a 2nd storage element and writing the result in the 2nd storage element. CONSTITUTION:A memory card consists of a memory 51 employing an E<2>PROM having a special write page mode, a memory 52 employing a RAM having no special write timing such as a special write cycle or a write page mode and a timing control circuit 56. Then a picture data outputted from a camera main body is stored in the memory 52 having no special write timing, the data is read from the memory 52 and written in the memory 51 having a special write timing corresponding to the write timing. Thus, the memory card using various memories with different write timings is used optionally to the same camera main body.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic still camera device that converts a photographed optical image into an electrical video signal and records it, and particularly relates to an electronic still camera device that converts a photographed optical image into an electrical video signal and records the video signal. This invention relates to improvements in recording media for recording.

(Prior Art) As is well known, in general cameras, the captured optical image is formed on a silver halide film, so unless the film is chemically processed and developed, the captured image cannot be viewed. is not possible.

In response, in recent years, electronic photographic systems have been developed that eliminate the need for complicated chemical processing by converting the captured optical image into an electrical video signal and displaying the image on a television receiver. , is becoming popular in the market. An example of such an electronic photographic system is a still image recording system.

In this still image recording system, a tape, disk, drum, or the like made of magnetic material is attached to a camera body as a recording medium in the form of a cassette or cartridge. After taking a picture and recording the video signal on a recording medium, the recording medium is removed from the camera body and attached to a playback device, and the still image is displayed on a television receiver connected to the playback device. be.

However, in this type of still image recording system, since the recording medium is made of a magnetic material, a magnetic head and a drive mechanism for the recording medium are required to perform recording and reproduction.
Problems arise in that the configuration becomes more complex and larger, and power consumption also increases.

Therefore, in recent years, it has been considered to use a semiconductor memory as a recording medium to eliminate the need for a magnetic head, drive mechanism, etc., thereby reducing the size, weight, and power consumption. In particular, in recent years, with the advancement of semiconductor element mounting technology,
2. Description of the Related Art Memory cards incorporating semiconductor memories have come into practical use, and development for using these memory cards as recording media is actively underway.

Here, it is desirable that the semiconductor memory used in this type of memory card be large in storage capacity, inexpensive, and non-volatile; for example, E2 FROM or the like is being considered.

However, E2 FROM has special write cycles and write page modes depending on the type, and data write timings are set differently. For this reason, data is stored in E2 FROM.
- In order to do this, it is necessary to provide data at a timing that corresponds to the data write timing of the memory.

On the other hand, since there is only one output timing for the video signal output from the camera body to the memory card, there are memory cards that can be used and memory cards that cannot be used depending on the camera body.

(Problems to be Solved by the Invention) As described above, in conventional electronic still camera devices, the semiconductor memory that can be used is limited depending on the data output timing of the camera body, so various semiconductor memories with different write timings are used. The problem is that the recording medium (memory card) cannot be used arbitrarily and is inconvenient to handle.

Therefore, the present invention has been made in consideration of the above circumstances, and is an extremely good system that can be used arbitrarily even with recording media using various semiconductor memories with different write timings, and can be conveniently handled by the user. The purpose of the present invention is to provide an electronic still camera device.

[Structure of the Invention] (Means for Solving the Problems) The electronic still camera device according to the present invention is intended for recording video signals captured by a camera body on a recording medium that is detachably attached to the camera body. It is said that The recording medium is supplied with a video signal output from the camera body, and includes a volatile first storage element that writes data at an arbitrary writing timing, and a non-volatile first storage element that writes data at a special writing timing. 2 and a timing control means for reading data from the first memory element, converting it to the write timing of the second memory element, and writing the data to the second memory element.

(Function) According to the above configuration, a video signal outputted from the camera body at an arbitrary timing is stored in the first storage element, data is read from the first storage element, and data is read out from the second storage element. Since the write timing is converted and written to the second storage element, it is possible to arbitrarily use recording media using various semiconductor memories with different write timings, making handling convenient for the user. It is something.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 4 shows the basic configuration of the electronic still camera device described in this embodiment. That is,
This electronic still camera device is comprised of a camera body 11 and a memory card 12 that is detachable from the camera body 1.

The camera body 11 has a lens barrel 13. It includes a finder 14 and a shutter 15, as well as an opening 16 into which a memory card 12 is inserted.

FIG. 5 shows the internal structure of the camera body 11. That is, numeral 17 in the figure is a lens disposed within the lens barrel 13, and the lens 17 projects a subject image onto a solid-state image sensor 18, such as a CCD, disposed on the back surface of the lens 17.

The solid-state image sensor 18 outputs an analog electrical signal (video signal) according to the brightness of the image projected through the lens 17, and this electrical signal is
The D (analog/digital) conversion circuit 19 converts the signal into digital data, and the band compression circuit 20 compresses the band, and then supplies the signal to the memory card control circuit 21 .

Further, reference numeral 22 in FIG. 5 is a microphone placed outside the camera body 11. The audio signal output from the microphone 22 is converted into digital data by an A/D conversion circuit 23, subjected to predetermined data processing by a digital audio processing circuit 24, and then supplied to the memory card control circuit 21.

Furthermore, 25 in FIG. 5 is a CPU that performs overall control of the entire electronic still camera device including the memory card 12. For example, it performs drive control of the solid-state image sensor 18 and band compression via the drive system 2B. It controls the compression ratio of the circuit 20, and also controls the memory card control circuit 21 and memory card 12.

FIG. 6 shows the configuration of the memory card control circuit 21 and its surroundings. In the figure, 27 is an I10 control circuit for exchanging data between the band compression circuit 20 or CPU 25 and the memory card 12.
Input/output control is performed between these.

In other words, image-related data from the band compression circuit 20 is input to the I10 control circuit 27 via the data input terminal 28. At the same time, data related to audio from the digital audio processing circuit 24 is inputted via the data input terminal 29. These data and data generated by the CPU 25 are sent to the memory card 12 from the data input/output terminal 30 via the I10 control circuit 27. Further, the data supplied from the memory card 12 via the data input/output terminal 30 is
It is sent to the CPU 25 via the control circuit 27.

Here, a memory 31 is interposed and connected on the data line between the CPU 25 and the I10 control circuit 27, and an interface for data transfer speed is established between them. In other words, the data input/output by the CPU 25 is serial data and low speed, while the data input/output by the I10 control circuit 27 is parallel data and high speed. Or converting parallel data into parallel data or serial data, respectively.

In addition, 32 in FIG. 6 is an address generation circuit, and the CPU 25
It generates address data corresponding to an initial address value specified by and an address value obtained by sequentially adding "1m" to this initial address value, and this address data is sent to the memory card 12 via the address output terminal 33.

Furthermore, 34 in FIG. 6 is a timing signal generation circuit, and C
Based on the designation from PU25, l101! I control circuit 2
7. Memory 31. It generates a predetermined timing signal to the address generation circuit 32 and also generates a timing signal to the memory card 12 via the timing output terminal 35.

Next, FIG. 7 shows a detailed configuration of the memory card 12. As shown in FIG. That is, this memory card I2 has a large number of memories such as RAM and E2 FROM on the board 36, which can electrically rewrite data.
. . , and connection terminals 38 connected to the camera body 11 are arranged in a row at one end of the board 3B.

As shown in FIG. 8, this memory card 12 has a data input/output terminal 39 connected to the data input/output terminal 30 of the camera body IT. This data input/output terminal 39 is connected to a plurality of memories 37, 37 . It is connected to each data input/output terminal of...

The memory card 12 also has an address input terminal 41 connected to the address output terminal 33 of the camera body 11. This address input terminal 41 is connected to the memory 37
．． 37. . . . are connected to each address input terminal and the chip select circuit 42. Note that this chip select circuit 42 selects the memory 37 to be operated based on address data output from the camera body 11.

Further, the memory card 12 has a timing input terminal 43 connected to the timing output terminal 35 of the camera body 11. This timing input terminal 43 is connected to the memory 37.37. It is connected to each timing input terminal of...

FIG. 9 shows a plurality of memories 37°37 of the memory card 12.
, . . . shows a memory map for explaining a memory area configured by . That is, this memory area includes a card header area 44 where data unique to the memory card 12 itself is recorded, a directory area 45 where the start address and end address of the area where each image data is recorded, It is roughly divided into three areas: a data area 46 where each image data is actually recorded;

Of these, the card header area 44 includes a card area 44a for recording on the card N, a residual memory capacity area 44b for recording the remaining amount of data in the area where data can be written in the data area 46, and a card header area 44 for recording data on the memory card 12. a shooting screen number area 44c in which data on the number of images is recorded;
Image data final address area 44 in which data of the final use address of image data is recorded in the data area 46
d etc.

Further, the data area 46 includes a plurality of one-screen data areas 46a and 48a, each of which is divided for each screen.

. . . One screen data area 48a further includes an image header area 48b and an image data area 48c in which actual image data is recorded.

The image header area 48b is the one-screen data area 4.
The information classification area 48d indicates what type of data (for example, images, audio, etc.) is recorded in the image data area 46e of 6a, and the information classification area 48d indicates what type of data processing system (for example, NTSC, CCIR, etc.) is recorded in the image data area 46c. ), a method area 48e indicating whether data is recorded, and a screen number area 481' where screen number data is recorded.
For example, there is an image quality mode area 46g in which data of the image quality mode set by the compression ratio of the band compression circuit 20 is recorded, a time area 48h in which data on the time of shooting is recorded, and data on the title of the recorded image is recorded. It has a title area 461 and the like.

Next, the photographing operation of the electronic still camera device having the basic configuration as described above will be explained. First, when the memory card 12 is inserted into the camera body 11 through the opening IB, each terminal 30, 33, 85 of the memory card control circuit 21 in the camera body 11 and each terminal 39, 41, 43 in the memory card 12 are connected. are connected respectively.

Then, the CPU 25 causes the timing signal generation circuit 34 to output data from the memories 37, 37 . It generates a signal to read data from . Therefore, the data in the card header area 44 of the memory card 12 is stored in the I10 control circuit 40.27.
and is transferred to the CPU 25 via the memory 3I.

Here, the CPU 25 selects the memory 37.37° of the memory card 12 based on the data in the card header area 44.
Check whether image data can be written to memory 37.37. Calculations are performed such as from which address (start address) to which address (end address) should the next image data be written.

Then, if image data can be written, the CPU
25 sets the start address and end address for the address generation circuit 32.

Thereby, the camera body 11 enters a state of waiting for the shutter 15 to be operated by the user.

Therefore, when the user operates the shutter L5 to suppress the CP
U25 outputs the timing signal generation circuit 34 to the memory 3.
7.37. . . . generates a signal for writing data, and causes the address generation circuit 32 to generate the address data set as described above at a predetermined timing.

Therefore, the video signal output from the solid-state image sensor 18 is transmitted to the A/D conversion circuit 19. The signal is sent to the memory card 12 via the band compression circuit 20 and the I10 control circuit 27. At the same time, address data generated by the address generation circuit 32 is also sent to the memory card 12 side.

As a result, in the memory card 12, the memory 37
．． 37. Image data is sequentially written to addresses corresponding to the address data from the address generation circuit 32 in the data area 4B.

When such writing is completed, the ladder data is transferred from the CPU 25 to the updated card via the memory 81 and the I10 control circuit 27.40.
..., the card header area 44 is updated, and the start address and end address data corresponding to the written image data are also sent to the CPU.
25 to memory 37.37. ..., and these data are written in the directory area 45.

Thereafter, the CPU 25 sends the timing signal generation circuit 34 to the memories 37, 37, . Generates a signal to stop a series of write operations for .

In the basic configuration as described above, the features of the present invention will be described in detail below. The embodiment described below solves the above-mentioned problems and can be used arbitrarily with recording media (memory cards) using various semiconductor memories with different write timings, making handling easier for the user. In addition to being convenient, image data and address data can be transferred via a common path line to connect the camera body 11 and memory card 1.
The number of pins for connection with the memory card 12 is reduced, and the memory card 12 can be easily attached and detached.

First, as shown in FIG. 2, in the memory card control circuit 21 described above, its address generation circuit 32
A status generation circuit 47 is provided instead. This status generating circuit 47 distinguishes whether data transferred through a common path line is image data or address data, and generates a status signal indicating the transfer direction in the case of image data. . This status signal is then sent to the memory card I2 via the status output terminal 4B.

On the other hand, FIG. 1 shows the configuration of the memory card I2. That is, 49 in the figure is a data input/output terminal, which is connected to the data input/output terminal 30 of the camera body 11.

This data input/output terminal 49 is connected to a plurality of memories 51, 51 . . . . and the memories 52, 52, . . . are connected to data input/output terminals.

Among these, memory 51.51. . . . uses E2 FROM, which has a special write page mode. Also, memory 52.52. . . . is a memory for storing -time, and uses a RAM that does not have special write timing such as a special write cycle or write page mode. And memories 51, 51 .
The data input terminals of... are connected to the data output terminals of the memory 52.52゜..., and the data input terminals of the memory 51
．． The data output terminal of 51°...- is connected to the memory 52
．． 52. It is connected to the data input terminal of...

Further, numeral 53 in FIG. 1 is a status input terminal, which is connected to the status output terminal 48 of the camera body 11.

This status input terminal 53 is connected to the status decoder 5.
Connected to 4. Furthermore, 55 in FIG. 1 is a timing input terminal and an output terminal, and the timing input terminal 55 is connected to the timing output terminal 35 of the camera body 11. This timing input/output terminal 55 is connected to the timing control circuit 5B. In addition, 57 in the figure
．． Reference numeral 58 represents an address counter for generating predetermined address data.

In the embodiment described here, image data and address data are transferred through a common path line, as described above. That is, image data and address data are transferred along a path line indicated by reference numeral 59 in FIG. this house,
As address data, instead of the address data corresponding to each image data as in the basic configuration described above, the start address and end address for starting reading or writing of image data are transferred, and the address data corresponding to each image data is , - are generated by the address counter 57 after being stored in the address register 60, which is stored in the memory 51.51. . . . and input to the chip select circuit 61. Note that the address register 60 is connected to the timing control circuit 56 along with the address counter 57.

Further, the address counter 58 generates address data based on a signal from the timing control circuit 5B, and this generates address data from the memories 52, 52, . . . . and input to the chip select circuit 62.

By the way, since image data and address data are transferred by the common path line 59 in this way, it is necessary to distinguish whether the data being transferred is image data or address data. Furthermore, it is also necessary to distinguish the transfer direction of image data.

For this reason, the above-described status generation circuit 47 is provided on the camera body 11 side, and a status decoder 54 is provided on the memory card 12 side.

A status signal as shown in FIG. 3 is sent from the status generation circuit 47 to the status decoder 54, and an enable signal is sent from the timing signal generation circuit 34 to the timing control circuit 56.

In Figure 3, "x" means don't care,
"0" indicates L (low) level, and '1' indicates H (high) level. CASEI is in a non-operating state, that is, the pass line 59 is in a high impedance state. Also, from CASE 2 to CASEI 3 is a mode for transferring read or write address data.The existence of multiple modes means that address data consists of a maximum of 24 bits, while
This is because the pass line 59 is 8 bits.

That is, CASE2 is a mode that transfers the lower byte start address for reading, and CASE3 is a mode that transfers the lower byte start address for writing.
CASE 4 is a mode that transfers the middle byte start address for reading, and CASE 5 is a mode that transfers the middle byte start address for writing.
CASE 6 is a mode for transferring the upper byte start address for reading, and CASE 7 is a mode for transferring the upper byte start address for writing.

CASE 8 is a mode that transfers the lower byte end address for reading, and CASE 9 is a mode that transfers the lower byte end address for writing.
SEI O is a mode that transfers the middle byte end address for reading, and CASEI 1 is a mode that transfers the middle byte end address for writing.
2 is a mode for transferring the upper byte end address for reading, and CASEI3 is a mode for transferring the upper byte end address for writing.

However, by combining these modes,
The start address and end address for each read and write case can be transferred.

In addition, CASEI4 is a mode that outputs read data, CASEI5 is a mode that outputs write data, and CASEI6 is a mode that outputs memory 51.51° when reading.
...from memory 52.52. In this mode, CASEI 7 transfers data from memory 52.52° to memory 51.51 when writing.
．． This is the mode for transferring data to...

In this way, using each of these modes, memory card 1
Data is written to the memory card 12 or data is read from the memory card 12.

That is, when reading arbitrary data from the memory card 12, the CPU 25 first reads CASE2. CASE4゜CASE6. CASE8. CASEI O, CAS
In the EI 2 mode, the status generating circuit 47 loads the start address and end address corresponding to the data to be read into the address register 60, and then the address counter 57 is loaded. Then, the start address and end address loaded into the address register 60 are sent to the timing control circuit 5B. Next, in the mode of CASEI6, necessary data is read out and brought into an internal processing state. The above operations complete read preparation.

Then, the address counter 57 starts counting up from the loaded address and stores the value in the memory 51.5.
1. Supply to... As a result, the memory 51
．． 51. The data corresponding to the supplied address is read from . It is supplied to...

As a result, the memory 51.51. The data read from the memories 52, 52.・・・・・・
・Written in

In this case, the timing control circuit 5B controls the signal W
Output “1°” to T and store memory 51.51.
From memory 52.52. When the data transfer to ...... is completed, "0" is output to the signal WT and CASEI
4, the data is stored in memory 52.52. This is the mode to be read from.

In the mode of CASEI4, the address counter 58
starts counting up from “01” again, and the value is supplied to the memory 52.52. and the camera body 11 via the I10 control circuit 50.
is supplied to

On the other hand, when writing data to the memory card 12,
The CPU 25 first performs CASE3. CASE'5. CA
SE7゜CASE9, CASEI1, CAS
In the EI 3 mode, the start address and end address corresponding to the data to be written are loaded from the status generation circuit 47 into the address register 60 and then loaded into the address counter 57. Then, the start address and end address loaded into the address register GO are sent to the timing control circuit 56. Next, the data is stored in the memory 52.52. in the mode of CASEI 5. . . . to be in a state where it should be written. The above operations complete the write preparation.

Then, the address counter 58 starts counting up from "0" and stores the value in the memory 52.52.・・・・・・
・Supply to. This causes memory 52.52. ...
..., data is written in accordance with the supplied address.

In this case, the timing control circuit 5B controls the signal W
Output “02” to T and store memory 52.52.
When the data writing to the memory 52.
52. . . . from memory 51.51.・・・・・・
・The mode is to transfer to.

In CASEI 7 mode, address counter 5
8 again starts counting up from 0°, and the value is supplied to the memory 52.52. At the same time, the address counter 57 starts counting up from the loaded address, and the value is supplied to the memories 51, 51, . . . .

For this reason, the memory 51.51. Memory 5 to...
2.52. The data read from... is written.

Here, the memory 52.52. Memory 51.51 of data read from... As a matter of course, writing to the memory 51, 51.・・・・・・
The write timing is set to be controlled within the memory card 2, that is, within the range of the circuit shown in FIG. 1, in correspondence with the write cycle, write page mode, etc. of .

Next, the procedure for reproducing the image data thus recorded on the memory card 12 using a reproducing device (not shown) will be briefly described. That is, when the memory card 12 is installed in the playback machine, the playback machine reads the memory card 1.
2, and detects the number of screens recorded on the memory card 12 and the start address and end address of each recorded image. Then, when the user specifies a screen to be played back, the start address corresponding to that screen is transferred to the memory card I2, and the desired image data can be read out and played back.

Therefore, according to the configuration of the above embodiment, the image data output from the camera body 11 is stored in the memory 52.52° that does not have special writing timing.
After being stored in the memory 52.52. Memory 5 with special timing for reading and writing from...
1.51. Since the data is written in accordance with the writing timing, it is possible to arbitrarily use memory cards 12 using various memories with different writing timings in the same camera body 11. This makes handling convenient for the user.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to arbitrarily use recording media using various semiconductor memories with different write timings, and it is extremely advantageous in that it can be handled conveniently for the user. It is possible to provide an electronic still camera device.

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of an electronic still camera device according to the present invention, and is a block diagram showing the structure of a memory card, and Fig. 2 shows details of a memory card control circuit used in the camera body of the embodiment. FIG. 3 is a diagram showing the relationship between status signals and operation modes of the same embodiment, FIG. 4 is an external view showing the electronic still camera device that is the basis of this invention, and FIG. 6 is a block diagram showing the detailed configuration of the basic device, FIG. 6 is a block diagram showing the detailed configuration of the memory card control circuit of the basic device, and FIG. 7 is the internal configuration of the memory card of the basic device. FIG. 8 is a block diagram showing the detailed structure of the memory card, and FIG. 9 is a diagram for explaining the memory area of the memory card. 11...Camera body, 12...Memory card, 13
... Lens barrel, 14... Finder, 15... Shutter, 1B... Opening, 17... Lens, 18...
Solid-state image sensor, 19... A/D conversion circuit, 20...
Band compression circuit, 21...Memory card control circuit, 22...Microphone, 23...A/D conversion circuit, 24...Digital audio processing circuit, 25...CP
U. 26... Drive system, 27... I10 control circuit, 28.
29...Data input terminal, 30...Data input/output terminal, 31...Memory, 32...Address generation circuit,
33... Address output terminal, 34... Timing signal generation circuit, 35... Timing output terminal, 3B...
・Board, 37...Memory, 38...Connection terminal, 39
...Data input/output terminal, 40...I10 control circuit,
41... Address input terminal, 42... Chip select circuit, 43... Timing input terminal, 44... Card header area, 45... Directory area, 46...
...Data area, 47...Status generation circuit, 48
...Status output terminal, 49...Data input/output terminal, 50...I10 control circuit, 51゜52...Memory, 53...Status input terminal, 54...Status decoder, 55... Timing input/output terminal, 56.
...Timing control circuit, 57.58... Address counter, 59... Pass line, 60... Address register, 81.02... Chip select circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (1)

[Claims] In an electronic still camera device that records a video signal shot by a camera body on a recording medium that is detachably attached to the camera body, the recording medium is supplied with the video signal output from the camera body and can be used for arbitrary writing. a volatile first memory element to which data is written at specific timing; a non-volatile second memory element to which data is written at special write timing; and a second memory element which reads data from the first memory element. 1. An electronic still camera device comprising: timing control means for converting the writing timing of the element to write timing to the second storage element.