JP2988667B2 - recoding media - Google Patents

Description

Description: Object of the Invention (Field of Industrial Application) The present invention relates to an electronic still camera device, and more particularly, to a recording medium used for recording a subject image photographed by the camera body.

(Prior Art) A conventional camera device for photographing a subject uses a silver halide film as a recording medium, and after photographing the subject on the film, subjecting the film to a chemical treatment and developing the film, an image of the subject is obtained. Since it is possible to view the captured image, it is impossible to instantly view the captured image.

On the other hand, recently, by converting an optical image into an electric signal and displaying an image on a television receiver,
An electronic photography system that does not require chemical processing was developed,
It has been commercialized. As this electronic photographic system,
There is a still image recording system including an electronic still camera device, a reproducing device, a television receiver, and the like. This still image recording system mounts a recording medium in the form of a cassette or cartridge on a tape, a disc, a drum, or the like using a magnetic material to the electronic still camera device,
Information, for example, an image is recorded, and thereafter, a recording medium is taken out, mounted on a reproducing device, and a reproduced image is obtained by a television receiver.

However, since the above-described still image recording system uses a magnetic material as a recording medium, it has to be provided with a magnetic head for recording and reproduction, a mechanism for driving the recording medium, and the like. And the problem that the weight increases. Further, according to this, there is also a problem that power consumption for controlling the driving of the mechanism for driving the recording medium increases.

Therefore, in such a still image recording system,
By using a recording medium called a memory card with a built-in semiconductor storage element such as an SRAM or an EEPROM, it is possible to reduce the mechanism and the like, to reduce the size and weight, and to reduce power consumption. I have. In such a still image recording system, what is required is to achieve organic coupling between the recording medium and the electronic still camera device, realize high-precision data transmission and reception between each other, and improve reliability. That is, it is possible to record a subject image having a high image quality.

FIG. 3 shows an electronic still camera apparatus of such a still image recording system. The camera body 20 has a recording medium attaching / detaching opening 21 through which the recording medium 1 can be attached / detached. Mounted freely. This recording medium 1
As shown in FIG. 3, a semiconductor memory element 3 such as an SRAM or an EEPROM is mounted on a substrate 2, and one end of the semiconductor memory element 3 is mounted on a camera body 20.
A connector 4 that is connected to a control system (not shown) is provided. This recording medium 1 can be used as a camera body 20 and data transmission / reception means, for example, an address bus (direct connection bus) system having an address signal bus and a data signal bus, or an address signal input terminal is not provided in a connector of the recording medium. It is configured by a so-called I / O bus system for transmitting and receiving signals using the same data bus as input data.

The camera body 20 is provided with a lens barrel 22, a finder 23 for setting an angle of view, and a release operator 24.

FIG. 5 shows the recording medium 1 of the address bus system. The connector 4 has an address signal input terminal 4a, a data input / output terminal 4b, a read timing input terminal 4c, a write timing signal input terminal 4d, and a semiconductor memory. A fixed data output terminal 4e for outputting a fixed data signal such as a memory capacity and a type as information on the element is provided. The address signal input terminal 4a is connected to the semiconductor memory element group 3a and the first input terminal of the chip select generating circuit 6 via the buffer 5, and the camera body is connected to the semiconductor memory element group 3a and the chip select generating circuit 6. Sends the address signal from 20. The data input / output terminal 4b is connected to the semiconductor memory element group 3a via the bidirectional buffer 7, and sends out a data signal from the camera body 20 to the semiconductor memory element group 3a, or outputs data residual information of the semiconductor memory element group 3a. Is transmitted to the camera body 20. Read timing input terminal 4c and write timing signal terminal 4d are buffers
Connected to the semiconductor memory element group via 8, 9
An out enable (OE) signal and a write enable (WE) signal from 0 are output to the semiconductor memory element group 3a. The output terminal of the buffer 8 is connected to the second input terminal of the chip select generation circuit 6 and the input terminal of the bidirectional buffer 7. On the other hand, the output terminal of the buffer 9 is connected to the third input terminal of the chip select generation circuit 6. The chip select generation circuit 6 outputs a chip select (CS) signal corresponding to the input address signal, OE signal, and WE signal to the semiconductor memory element group 3a. The fixed data output terminal 4e is connected to the storage element capacity identification circuit 10a and the storage element type identification circuit 10b. The storage element capacity discrimination circuit 10a and the storage element type discrimination circuit 10b are used to set the storage capacity and type information data relating to the mounted semiconductor storage element 3, for example, to set the level of the switch circuit to “H” or “L” level. Thus, when the recording medium 1 is mounted on the camera body 20, the fixed data signal is transmitted to the camera body 20 via the fixed data output terminal 4e.

In the above configuration, when the recording medium 1 is mounted on the camera body 20, first, the recording medium 1
Is sent to the camera body 20 via the fixed data output terminal 4e. As a result, the control system of the camera body 20 is switched and set to a state according to the fixed data signal from the recording medium 1.

When recording image data of a subject image photographed by the camera body 20 and input data such as information data and residual capacity data on the image data on the recording medium 1, first, an address signal, a data signal, and a WE signal are transmitted from the camera body 20. A signal is input via an address signal input terminal 4a, a data input / output terminal 4b, and a write timing signal input terminal 4d. Then, the address signal, the data signal, and the WE signal are input to the semiconductor memory element group 3a via the buffer 5, the bidirectional buffer 7, and the buffer 9. At the same time, the address signal and WE
The signal is input to the CS generation circuit 6. The CS generation circuit 6 obtains a CS signal from the input signal and outputs the CS signal to the semiconductor memory element group 3a. Thus, the input data is recorded in a desired semiconductor memory element 3 of the semiconductor memory element group 3a in response to the address signal and the CS signal.

The recording medium 1 on which the input data is recorded as described above.
When the data is read out, first, the address signal and the OE signal are guided from the camera body 20 to the address signal input terminal 4a and the read timing signal input terminal 4c of the connector 4. The address signal and the OE signal are sent to the semiconductor memory element group 3a via the buffers 5 and 8, and are sent to the CS generation circuit 6. Here, the CS generation circuit 6 obtains a CS signal according to the input address signal and the OE signal, and outputs the CS signal to the semiconductor memory element group 3a. At the same time, OE
The signal is output to the bidirectional buffer 7, and the bidirectional buffer 7 is switched and set to the output mode. This allows
The information stored in the semiconductor memory element group 3a is guided to the camera body 20 via the bidirectional buffer 7 and the data input / output terminal 4b as a data signal in response to the address signal, and the data is read.

FIG. 8 shows the recording medium 1 of the I / O bus system. The connector 4 includes a data input / output terminal 4f, a status signal input terminal 4g, a fixed data output terminal 4e, and a read timing signal input terminal. 4c and a write timing signal input terminal 4d are provided. The I / O control circuit 11 is connected to the data input / output terminal 4f. The I / O control circuit 11 is connected to the semiconductor memory element group 3a. One input terminal of the address counter 12 is connected to the output terminal of the I / O control circuit 11. In the address counter 12, a timing control circuit 13 is connected to the other input terminal, and an output terminal thereof is connected to an input terminal of the semiconductor memory element group 3a. The output terminal of the address counter 12 is connected to a chip select (C / S) generation circuit 14, and the C / S generation circuit 14
Is connected to the output terminal of the timing control circuit 13, and the output terminal is connected to the semiconductor memory element group 3a.

A status decoder 15 is connected to the status signal input terminal 4g, and an output terminal of the status decoder 15 is connected to a first input terminal of the timing control circuit 13.
The timing control circuit 13 has a read timing signal input terminal 4c and a write timing signal input terminal 4d connected to the second and third input terminals, and an output terminal connected to the semiconductor memory element group 3a.

The output terminals of the storage element capacity identification circuit 10a and the storage element type identification circuit 10b are connected to the fixed data output terminal 4e in the same manner as in the address bus method.

In the above configuration, when the recording medium 1 is mounted on the camera main body 20, first, the recording medium is moved to its semiconductor storage element group 3a.
Is sent to the camera body 20 via the fixed data output terminal 4e. Thus, the control system of the camera body 20 is switched and set to a state according to the fixed data from the recording medium 1.

When recording image data of a subject image photographed by the camera body 20 and input data such as information data relating to the image data and residual capacity data on the recording medium 1, first, an initial address signal, a status signal and a WE signal are transmitted from the camera body 20.
Signal is data input / output terminal 4f, status signal input terminal 4g
The data is input to the I / O control circuit 11, the status decoder 15, and the timing control circuit 13 via the write timing signal input terminal 4d. Then, the I / O control circuit 11 outputs an initial address signal to the address counter 12. At the same time, the status decoder 15 decodes the input status signal and outputs it to the timing control circuit 13. The timing control circuit 13 generates a signal corresponding to the input status signal and WE signal, and outputs the generated signal to the address counter 12 and the CS generation circuit 14. Then
The address counter 12 generates an address corresponding to the input control signal from the timing control circuit 13 and outputs the generated address to the semiconductor memory element group 3a. At the same time, CS generation circuit 14
Calculates the CS signal from the input signal and outputs the CS signal to the semiconductor memory element group 3a. As a result, the input data is recorded in a desired semiconductor memory element 3 of the semiconductor memory element group 3a in response to the initial address signal and the CS signal.
At this time, the address value of the address counter 12 is incremented every time 1-byte data is written, for example.

From the recording medium 1 on which the input data is recorded as described above,
When reading the data, first, the initial address signal, status signal, and OE signal from the camera body 20 are transmitted to the I / O control circuit 11 via the data input / output terminal 4f, the status signal input terminal 4g, and the read timing signal input terminal 4c. Are input to the status decoder 15 and the timing control circuit 13. Then, the I / O control circuit 11 outputs an initial address signal to the address counter 12. At the same time, the status decoder 15 decodes the input status signal and outputs it to the timing control circuit 13. The timing control circuit 13 generates signals corresponding to the input status signal and OE signal, and
And to the CS generation circuit 14. Then, the address counter 14 generates an address corresponding to the input control signal from the timing control circuit 13 and outputs the generated address to the semiconductor memory element group 3a. At the same time, the CS generation circuit 14 obtains a CS signal from the input signal, and
Output to 3a. As a result, as for the storage information data of the semiconductor storage element group 3a, the data signal responding to the initial address signal is guided to the camera body 20 from the data input / output terminal 4f of the connector 4 via the I / O control circuit 11, and the data is read out. Is performed. At this time, the address value of the address counter 12 is incremented every time 1-byte data is written, for example.

However, in the recording medium 1, the semiconductor storage element group 3a
The fixed data output terminal 4e is provided on the connector 4 to transmit the fixed data to the camera body 20, and the data is transmitted to the camera body 20 from the fixed data output terminal 4e. If the number of input / output data lines (address signal input data lines) is included, the number of terminals of the connector 4 increases, so that the load when attaching / detaching to / from the camera body 20 is extremely large, and the terminals are likely to be damaged. Had the problem that

The same is true for recording media of either the address bus system or the I / O bus system.

Therefore, it is conceivable that the fixed data of the semiconductor memory element group 3a is directly stored in the semiconductor memory element group 3a. For example, when a volatile memory is used as the semiconductor memory element 3, the backup battery is used. Is consumed, the fixed data is lost.

(Problems to be Solved by the Invention) As described above, in the conventional recording medium, the number of data lines is large, and the connection terminal becomes a large load when being attached to or detached from the camera body, and the connection terminal is damaged. Had.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a recording medium that can be easily attached to and detached from a camera body with a simple configuration and that is easy to use.

[Means for Solving the Problems] The present invention relates to a recording medium including a semiconductor storage element mounted on a camera body and recording a subject image photographed by the camera body as digital data. A data line for transmitting and receiving the digital data to and from the camera body; a recording unit for recording the digital data input via the data line in a semiconductor storage element; and information relating to the semiconductor storage element to predetermined fixed data. A storage element identifying unit that reproduces the data line, and selecting one of the fixed data from the storage element identifying unit and the digital data recorded in the semiconductor storage element based on an address transferred from the camera body, and selecting the data line. And selecting means for transmitting the data to the camera body via the camera.

(Operation) According to the above configuration, the fixed data and the digital data of the semiconductor storage element are sent from the storage element identification means to the camera body via the same data line and read out according to the selection of the selection means. Therefore, it is not necessary to provide a separate data line for transmitting fixed data from the storage element identification unit and digital data from the semiconductor storage element to the camera body as in the related art, thereby reducing the number of connection terminals with the camera body. Therefore, the load at the time of attachment / detachment to / from the camera body can be reduced, simple attachment / detachment is realized, and the reliability of the attachment / detachment operation is improved as much as possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an address bus type recording medium according to an embodiment of the present invention. The connector 50 has an address signal input terminal 50a, a data input / output terminal 50b, a read timing input terminal 50c, and a write timing signal input terminal. A terminal 50d and the like are provided. The address signal input terminal 50a is connected to the buffer 51
Are connected to the first input terminals of a semiconductor memory element group 52, an address detection circuit 53, and a chip select (CS) generation circuit 54 via the semiconductor memory element group 52, the address detection circuit 53
Further, an address signal from the camera body 20 is transmitted to the chip select generation circuit 54. Data input / output terminal 50b
Is a bidirectional multiplexer 56 via a bidirectional buffer 55
The bidirectional multiplexer 56 is connected to the semiconductor memory element group 52. This bidirectional multiplexer
An address detection circuit 53 is connected to one input terminal of the input device 56, and a storage element capacitance identification circuit 57a is connected to the other input terminal.
And a storage element type identification circuit 57b. These storage element capacity identification circuit 57a and storage element type identification circuit 57b
Indicates that the storage capacity and type information data relating to the mounted semiconductor storage element group 52 are previously set as fixed data by setting the level of the switch circuit to “H” or “L” level, for example. The data signal is sent to the bidirectional multiplexer 56.

The read timing input terminal 50c and the write timing signal terminal 50d are connected to the semiconductor memory element group 52 via buffers 58 and 59, and output an out enable (OE) signal and a write enable (WE) signal from the camera body 20 to the semiconductor. Output to the storage element group 52. And buffer 58
Is connected to the second input terminal of the CS generation circuit 54, the signal input terminal of the bidirectional buffer 55, and the other input terminal of the bidirectional multiplexer 56.

On the other hand, the output terminal of the buffer 59 is connected to the third input terminal of the CS generation circuit 54. The CS generation circuit 54 outputs a chip select (C) corresponding to the input address signal, OE signal, and WE signal.
S) Output a signal to the semiconductor memory element group 52.

In the above configuration, when mounted on the camera body 20, first, an address signal and an OE signal are input from the camera body 20 to the address signal input terminal 50a and the read timing signal input terminal 50c of the connector 50. The address signal is input to the address detection circuit 53 via the buffer 51. Then, the address detection circuit 53 generates a fixed data output signal and outputs it to the bidirectional multiplexer 56. In response, the bidirectional multiplexer 56 includes a storage element capacitance identification circuit.
The fixed data signal from the storage element type identification circuit 57b is output to the bidirectional buffer 55. At the same time, the OE signal is guided to the bidirectional buffer 55, the bidirectional buffer 55 is switched to the output mode, and the fixed data signal is output to the camera body 20 via the data input / output terminal 50a. Thereby, the control system of the camera body 20 is switched and set to a state corresponding to the fixed data.

When recording image data of a subject image captured by the camera body 20 and input data such as information data and residual capacity data relating to the image data, first, an address signal, a data signal, and a WE signal are transmitted from the camera body 20 as address signals. The data is input via an input terminal 50a, a data input / output terminal 50b, and a write timing signal input terminal 50d. Then, the address signal and the WE signal are input to the semiconductor memory element group 52 and the CS generation circuit 54 via the buffer 51 and the buffer 59.
On the other hand, the data signal is input to the bidirectional multiplexer 56. The bidirectional multiplexer 56 outputs the input data signal to the semiconductor memory element group 52. At the same time, the CS generator
54, a CS signal is obtained from the input signal, and the CS signal is output to the semiconductor memory element group 52. As a result, the input data is recorded in a desired semiconductor memory element of the semiconductor memory element group 52 in response to the add signal and the CS signal.

When reading the input data recorded as described above, first, the address signal and the OE signal are guided from the camera body 20 to the address signal input terminal 50a and the read timing signal input terminal 50c of the connector 50. OE signal is buffer 5
The signal is input to the bidirectional multiplexer 56 via 8, and the bidirectional multiplexer 56 is set to the read mode. At the same time, the address signal and the OE signal are sent to the semiconductor memory element group 52 and the CS generation circuit 54. Here, the CS generation circuit 54
Calculates a CS signal according to the input address signal and OE signal, and outputs the CS signal to the semiconductor memory element group 52.
At the same time, the OE signal is output to the bidirectional buffer 55, and the bidirectional buffer 55 is switched to the output mode and set. Thereby, the storage information data of the semiconductor storage element group 52 is such that the data signal responding to the address signal is a bidirectional buffer 55,
Guided to the camera body 20 via the data input / output terminal 50b,
Data reading is performed.

As described above, the recording medium includes a storage element capacity identification circuit.
Fixed data from 57a and the storage element type identification circuit 57b,
The storage information data of the semiconductor storage element group 52 can be selectively transmitted to the camera main body 20 via the bidirectional multiplexer 56 so that transmission to the camera main body 20 can be performed using the same data line. With this configuration, it is not necessary to provide separate data lines for transmitting fixed data from the storage element identification means and storage information data from the semiconductor storage element group to the camera body 20 as in the related art.
The number of data lines for transmitting and receiving data to and from is reduced. According to this, the number of connection terminals of the connector 50 for performing electrical connection with the camera body 20 can be reduced,
Since the load at the time of attachment / detachment to / from the camera body 20 is reduced, the reliability of the attachment / detachment operation is improved as much as possible.

In the above embodiment, the description has been given of the case where the configuration is based on the address bus system. However, the present invention is not limited to this, and can be applied to the I / O bus system as shown in FIG. That is, the connector 50 is provided with a status signal input terminal 50e, a data output terminal 50b, a read timing signal input terminal 50c, and a write timing signal input terminal 50d.

A status decoder 61 is connected to the status signal input terminal 50e via a buffer 60. A timing control circuit 62 is connected to the output terminal of the status
Are connected to each other. A read timing signal input terminal 50c and a write timing signal input terminal 50d are connected to the second and third input terminals of the timing control circuit 62 via buffers 58 and 59. An address generation circuit is provided at the output terminal of the timing control circuit 62.
63 is connected. The address signal output terminal and the CS signal output terminal of the address generation circuit 63 are connected to the semiconductor memory element group 52.

Bidirectional buffer 5 connected to data input / output terminal 50b
5 has a signal input terminal connected to the output terminal of the buffer 58, and the other input / output terminal connected to a bidirectional multiplexer 56.
Is connected to one of the input / output terminals. Bidirectional multiplexer
A semiconductor memory element group 52 is connected to the other input / output end of the storage element 56, and its input end is connected to a fixed data generation storage element capacity identification circuit 57a and a storage element type identification circuit 57b in substantially the same manner as in the address bus system. Output terminals are connected. The output terminal of the bidirectional buffer 55 is connected to the address detection circuit 64 and the address generation circuit 63. Address detection circuit
64 is connected to the output terminal of the buffer 58, and the output terminal is connected to the bidirectional multiplexer 56.

In the above configuration, when mounted on the camera body 20, first, the initial address data and the OE signal are input from the camera body 20 to the data input / output terminal 50b and the read timing signal input terminal 50c. The initial address signal is input to the address detection circuit 64 and the bidirectional multiplexer 56 via the bidirectional buffer 55. Then, the address detection circuit 64
Generates a fixed data output signal and outputs it to the bidirectional multiplexer 56. At the same time, the OE signal is input to the bidirectional multiplexer 56 and the bidirectional buffer 55, and sets the bidirectional multiplexer 56 and the bidirectional buffer 55 to the output mode. In response, a bidirectional multiplexer 56
The fixed data signal input from the storage element capacity identification circuit 57a and the storage element type identification circuit 57b is
5 to the camera body 20 via the data input / output terminal 50b.
To send to. Thereby, the control system of the camera body 20 is switched and set to a state corresponding to the fixed data from the semiconductor memory element group 52.

When recording image data of a subject image photographed by the camera body 20 and input data such as information data and residual capacity data related to the image data, first, an initial address signal, a status signal, and a WE signal are transmitted from the camera body 20 as data. It is input to the input / output terminal 50b, the status signal input terminal 50e, and the write timing signal input terminal 50d. Of these, the initial address is input to the address detection circuit 64, the address generation circuit 63, and the bidirectional multiplexer 56 via the bidirectional buffer 55. At the same time, the status signal is input to the status decoder 61 via the buffer 60. The status decoder 61 decodes the input status signal and outputs it to the timing control circuit 62.
The timing control circuit 62 outputs the WE signal to the buffer 59.
, And generates a signal corresponding to the status signal, and outputs the signal to the address generating circuit 63 and the semiconductor memory element group 52. Then, the address generation circuit 63 generates an address signal corresponding to the input control signal from the timing control circuit 62 and a chip select (CS) signal, and outputs them to the semiconductor memory element group 52.
As a result, the data input to the bidirectional multiplexer 56 is recorded in a desired semiconductor memory element of the semiconductor memory element group 52 in response to the initial address signal and the CS signal. At this time, the address value is incremented in the address generating circuit 63 every time one-byte data is written, for example.

When reading the input data recorded as described above, first, the initial address signal, the status signal, and the OE signal from the camera body 20 are transmitted via the data input / output terminal 50b, the status signal input terminal 50e, and the read timing signal input terminal 50c. Is entered. Among these, the initial address signal is input to the address detection circuit 64, the address generation circuit 63, and the bidirectional multiplexer 56. At the same time, the status signal is input to the status decoder 61 via the buffer 60. After decoding the status signal, the status decoder 61 outputs the status signal to the timing control circuit 62. The timing control circuit 62 receives the OE signal via the buffer 58, generates a signal corresponding to the input status signal, and outputs the signal to the address generation circuit 63. Then, the address generation circuit 63 generates an address signal and a CS signal corresponding to the input control signal from the timing control circuit 62, and outputs the generated signal to the semiconductor memory element group 52. As a result, the data responding to the initial address signal is guided to the camera body 20 via the bidirectional multiplexer 56, the bidirectional buffer 55 and the data input / output terminal 50b, and the data read out of the storage information data of the semiconductor memory element group 52 is performed. Done.
At this time, the address value is incremented each time the address generating circuit 63 reads, for example, 1-byte data.

In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, a recording medium that can be easily attached to and detached from the camera body with a simple configuration and that is easy to use can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a recording medium according to one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIGS. 3 and 4 are electronic apparatuses to which the present invention is applied. FIGS. 5 and 6 are block diagrams showing a conventional recording medium. 50… Connector, 50a… Alay signal input terminal, 50b…
... Data input / output terminal, 50c ... Read timing signal input terminal, 50d ... Write timing signal input terminal, 50e ...
... Status signal input terminal, 51,58,59,60 ... Buffer, 52 ... Semiconductor storage element group, 53,64 ... Address detection circuit, 54 ... CS generation circuit, 55 ... Bidirectional buffer, 56 ...
... bidirectional multiplexer, 57a ... storage element capacity identification circuit, 57b ... storage element type identification circuit, 61 ... status decoder, 62 ... timing control circuit, 63 ...
Address generation circuit.

Continuation of the front page (56) References JP-A-2-118990 (JP, A) JP-A-2-113785 (JP, A) JP-A-1-2588091 (JP, A) JP-A-63-169886 (JP) , A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 5/907

Claims (1)

(57) [Claims] 1. A recording medium mounted on a camera body and having a semiconductor memory device for recording a subject image photographed by the camera body as digital data, the data being used for transmitting and receiving the digital data to and from the camera body. Line, storage means for recording the digital data input via the data line in a semiconductor storage element, storage element identification means for generating information on the semiconductor storage element as predetermined fixed data, and Selecting means for selecting one of the fixed data from the storage element identification means and the digital data recorded in the semiconductor storage element based on the transferred address and sending the selected data to the camera body via the data line. A recording medium characterized by comprising: