JPH02219396A - Side lock prevention circuit - Google Patents

Side lock prevention circuit

Info

Publication number
JPH02219396A
JPH02219396A JP1039947A JP3994789A JPH02219396A JP H02219396 A JPH02219396 A JP H02219396A JP 1039947 A JP1039947 A JP 1039947A JP 3994789 A JP3994789 A JP 3994789A JP H02219396 A JPH02219396 A JP H02219396A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
vco
horizontal synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1039947A
Other languages
Japanese (ja)
Inventor
Masao Okumura
奥村 昌夫
Yuzo Yasuda
安田 裕造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1039947A priority Critical patent/JPH02219396A/en
Publication of JPH02219396A publication Critical patent/JPH02219396A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent excess control from being applied to a VCO and to execute oscillation by a preceding control voltage by providing a horizontal synchronizing signal detection circuit and prohibiting it in correspondence to a detection output that the output signal of a frequency identification circuit is added to the VCO. CONSTITUTION:From a state that a desired carrier chrominance signal is obtained by the oscillation output signal of a stable VCO 4, a VTR is switched to a special reproducing state. When special reproducing is executed, the lack of a horizontal synchronizing signal or the fluctuation of a period is generated. A horizontal synchronizing signal detection circuit 17, to which the horizontal synchronizing signal is impressed from a terminal 6, detects that the horizontal synchronizing signal does not arrive in the normal period. Then, a switch 18 is opened in correspondence to the detection output. Thus, it is prohibited that an abnormal control signal is added from a frequency identification circuit 14 to the VCO 4. When the horizontal synchronizing signal is fluctuated, the operation of a phase comparator circuit 13 is stopped and an output terminal is opened. Then, an LPF 15 still holds the voltage before the fluctuation. Accordingly, the VCO 4 can be oscillated by the stable frequency before the fluctuation.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、カラー映像信号の再生機能を有する家庭用の
VTR(ビデオテープレコーダ)に用いられるサイドロ
ック防止回路に関するもので、特に色信号を周波数変換
する為に用いられるvCO(電圧制御型発振器)の発振
を特殊再生時に安定化することが出来るサイドロック防
止回路に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a sidelock prevention circuit used in a home VTR (video tape recorder) having a color video signal playback function, and particularly relates to a sidelock prevention circuit used in a home VTR (video tape recorder) having a color video signal playback function. The present invention relates to a sidelock prevention circuit that can stabilize the oscillation of a vCO (voltage controlled oscillator) used for frequency conversion during special reproduction.

(ロ)従来の技術 家庭用VTRでは、再生時搬送色信号中のバースト信号
を抽出し、抽出したバースト信号と発振器の発振出力信
号とを位相比較し、その位相差に応じて周波数変換を行
なう為のvCOの発振を制御している。前記バースト信
号は、間欠して到来する為、前記■COに対する制御も
間欠になる。
(b) Conventional technology In a home VTR, a burst signal is extracted from the carrier color signal during playback, the extracted burst signal and the oscillation output signal of the oscillator are compared in phase, and frequency conversion is performed according to the phase difference. It controls the oscillation of vCO for Since the burst signal arrives intermittently, control over the CO is also intermittently.

すると、前記vCOの発振周波数は本来の値からずれ、
異常な周波数に誤ってロックしてしまうことが知られて
いる。そこで、例えば特開昭55−147892号公報
に示される如く、前記VCOの発振出力信号を水平同期
信号に基づき周波数識別回路で計数し、その計数値に応
じて前記vCOの発振を制御する所謂サイドロック防止
回路を配置する方法が行なわれている。そうすることに
よって、vCOは常に帰還信号によって制御されること
になり、正常なロック状態を継続することが出来る。
Then, the oscillation frequency of the vCO deviates from its original value,
It has been known to accidentally lock onto abnormal frequencies. Therefore, as shown in Japanese Patent Application Laid-open No. 55-147892, for example, a so-called side system is used in which the oscillation output signal of the VCO is counted by a frequency discrimination circuit based on the horizontal synchronization signal, and the oscillation of the VCO is controlled according to the counted value. Methods of arranging anti-lock circuits have been used. By doing so, vCO is always controlled by the feedback signal, and a normal lock state can be maintained.

(ハ)発明が解決しようとする課題 しかしながら、前述の方法ではVTRの特殊再生時など
で水平同期信号の欠落が生ずると周波数識別回路が誤動
作を起こし、vCOの発振周波数が正常であっても異常
であると判別し、前記■COの発振周波数を乱してしま
うという問題があった。
(c) Problems to be Solved by the Invention However, in the above method, if a horizontal synchronization signal is missing during special playback of a VTR, the frequency identification circuit will malfunction, and even if the oscillation frequency of the vCO is normal, it will become abnormal. There was a problem that the oscillation frequency of the above-mentioned CO would be disturbed.

(ニ)課題を解決するための手段 本発明は、上述の点に鑑み成されたもので、発振器の発
振出力信号とバースト信号との位相比較により発振が制
御される電圧制御型発振器と、前記電圧制御型発振器の
発振周波数を基準信号に基づき識別し該識別出力に応じ
て前記電圧制御型発振器の発振を制御する周波数識別回
路を少なくとも有するサイドロック防止回路において、
前記水平同期信号の状態を検出する水平同期信号検出回
路を設け、該水平同期信号検出回路の検出出力に応じて
前記周波数識別回路の出力信号が前記電圧制御型発振器
に加わるのを禁止したことを特徴とする。
(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a voltage controlled oscillator whose oscillation is controlled by phase comparison between an oscillation output signal of the oscillator and a burst signal; A sidelock prevention circuit having at least a frequency identification circuit that identifies an oscillation frequency of a voltage controlled oscillator based on a reference signal and controls oscillation of the voltage controlled oscillator according to the identification output,
A horizontal synchronization signal detection circuit for detecting the state of the horizontal synchronization signal is provided, and the output signal of the frequency identification circuit is prohibited from being applied to the voltage controlled oscillator in accordance with the detection output of the horizontal synchronization signal detection circuit. Features.

(ホ)作用 本発明に依れば、水平同期信号の欠落などの状態を検出
し、その検出出力に応じて周波数識別回路の識別出力が
vCOに印加されるのを禁止しているので、前記■CO
には余分な制御が加わらず、直前の制御電圧によって発
振することが出来る。
(E) Effect According to the present invention, a condition such as a missing horizontal synchronizing signal is detected, and the identification output of the frequency identification circuit is prohibited from being applied to vCO according to the detected output. ■CO
No extra control is applied to the oscillation, and oscillation can be performed using the previous control voltage.

(へ)実施例 第1図は、本発明をNTSC方式のVTRの再主回路に
用いた場合の一実施例を示す回路図で、(1)は入力端
子(2)からの低域変換された629KHzの搬送色信
号を抽出するローパスフィルタ、(3)は搬送色信号周
波数escで発振する発振器、〈4〉は160f++(
foは水平同期信号周波数)で発振するVCO,(5)
は前記V CO(4)の16 OfHの発振出力信号を
端子(6)からの水平同期信号に応じてに分周すると共
に、90度づつ位相シフトする4φ位相シフト回路、(
7)は前記44位相シフト回路(5)からの4Of、の
信号を前記発振器(3)からのf、。の信号に応じて周
波数変換するサブコンバータ、(8)は前記サブコンバ
ータ(7)の出力信号から4.21MHzの成分のみを
通過させるバンドパスフィルタ、(9)は前記ローパス
フィルタ(1)からの629KHzの搬送色信号を前記
バンドパスフィルタ(8)の出力信号に応じて周波数変
換すルメインコンバータ、(10)は前記メインコンバ
ータ(9)の出力信号から3.58MHzの成分のみを
通過させ出力端子(11)に導出するバンドパスフィル
タ、(12)は前記出力端子(11)に導出された搬送
色信号が印加され、その信号中のバースト信号のみが端
子(6)からの水平同期信号に応じて抽出されるバース
ト抽出回路、(13)は前記バースト抽出回路(12)
から得られるバースト信号と前記発振器(3)の発振出
力信号との位相比較を行なう位相比較回路、(14)は
前記V CO(4)の発振出力信号を端子(6)からの
水平同期信号に応じて計数し、周波数の識別を行なう周
波数識別回路、(15)は前記位相比較回路(13)の
出力信号と前記周波数識別回路(14)の出力信号とを
加算し、その加算出力をローパスフィルタ(16)を介
して前記V CO(4)に印加する加算回路、及び(1
7)は端子(6)からの水平同期信号の欠落などの状態
変化を前記発振器(3)の発振出力信号に応じて検出し
、スイッチ(18)を切換える水平同期信号検出回路で
ある。
(v) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention in the main circuit of an NTSC VTR. (3) is an oscillator that oscillates at carrier color signal frequency esc, and <4> is 160f++ (
fo is a VCO that oscillates at the horizontal synchronization signal frequency (5)
is a 4φ phase shift circuit that divides the frequency of the 16 OfH oscillation output signal of the VCO (4) according to the horizontal synchronization signal from the terminal (6) and shifts the phase by 90 degrees, (
7) converts the 4Of signal from the 44 phase shift circuit (5) into the f signal from the oscillator (3). (8) is a band-pass filter that passes only the 4.21 MHz component from the output signal of the sub-converter (7), and (9) is a band-pass filter that converts the frequency according to the signal from the low-pass filter (1). A main converter converts the frequency of a 629 KHz carrier color signal according to the output signal of the band pass filter (8), and a main converter (10) passes only the 3.58 MHz component from the output signal of the main converter (9) and outputs it. A bandpass filter (12) is connected to a terminal (11) to which the carrier color signal derived from the output terminal (11) is applied, and only the burst signal in the signal is applied to the horizontal synchronization signal from the terminal (6). A burst extraction circuit (13) is extracted according to the burst extraction circuit (12).
A phase comparison circuit (14) performs a phase comparison between the burst signal obtained from the oscillator and the oscillation output signal of the oscillator (3), and a phase comparison circuit (14) converts the oscillation output signal of the VCO (4) into a horizontal synchronization signal from the terminal (6). A frequency identification circuit (15) adds the output signal of the phase comparison circuit (13) and the output signal of the frequency identification circuit (14), and passes the added output to a low-pass filter. (16) to the V CO (4), and (1
Reference numeral 7) is a horizontal synchronizing signal detection circuit that detects a state change such as a loss of the horizontal synchronizing signal from the terminal (6) according to the oscillation output signal of the oscillator (3) and switches the switch (18).

まずVTRの通常モードでの再生について説明する。入
力端子(2)からの再生信号中の低域変換された6 2
9 KHzの搬送色信号は、ローパスフィルタ(1)を
介して抽出され、メインコンバータ(9)に印加される
。一方、メインコンバータ(9)にはバンドパスフィル
タ(8)から4.21MHzの信号が印加されるので、
前記搬送色信号の周波数変換が行なわれる。周波数変換
された前記搬送色信号は、バンドパスフィルタ(10)
に印加され、3.58 MHzの搬送色信号のみが出力
端子(11)に導出される。前記搬送色信号は、バース
ト抽出回路(12)に印加され、端子(6)からの水平
同期信号に基づいてバースト信男のみが抽出される。抽
出されたバースト信号は、発振器(3〉の発振出力信号
と位相比較回路(13)でバースト期間中、位相比較さ
れる。一方、V CO(4)の発振出力信号は、周波数
識別回路(14)でその周波数が端子(6)からの水平
同期信号に基づいて識別され、所定範囲外のとき、誤差
出力がスイッチ(18)を介して加算回路(15)に印
加される。加算回路(15)では2つの入力信号の加算
が行なわれ、その加算結果がローパスフィルタ(16〉
を介してV CO(4)に印加され、VCO(4)の発
振が安定に制御される。
First, reproduction in the normal mode of the VTR will be explained. Low-frequency converted 6 2 of the reproduced signal from the input terminal (2)
The 9 KHz carrier color signal is extracted via a low pass filter (1) and applied to the main converter (9). On the other hand, since a 4.21MHz signal is applied from the bandpass filter (8) to the main converter (9),
Frequency conversion of the carrier color signal is performed. The frequency-converted carrier color signal is passed through a bandpass filter (10).
, and only the 3.58 MHz carrier color signal is led out to the output terminal (11). The carrier color signal is applied to a burst extraction circuit (12), and only the burst signal is extracted based on the horizontal synchronization signal from the terminal (6). The phase of the extracted burst signal is compared with the oscillation output signal of the oscillator (3) by the phase comparison circuit (13) during the burst period. On the other hand, the oscillation output signal of the VCO (4) is compared with the oscillation output signal of the oscillator (3) by the frequency discrimination circuit (14). ) is identified based on the horizontal synchronization signal from the terminal (6), and when it is outside the predetermined range, the error output is applied to the adder circuit (15) via the switch (18). ), the two input signals are added, and the addition result is sent to the low-pass filter (16).
It is applied to VCO (4) via VCO (4), and the oscillation of VCO (4) is stably controlled.

その為、安定な前記V CO(4>の発振出力信号を4
φシフト回路(5)、サブコンバータ(7)及びバンド
パスフィルタ(8)を介してメインコンバータ(9)に
印加すれば、所望の搬送色信号を得ることが出来る。
Therefore, the stable oscillation output signal of the V CO (4>
By applying the signal to the main converter (9) via the φ shift circuit (5), sub-converter (7) and band-pass filter (8), a desired carrier color signal can be obtained.

この状態から、VTRを特殊再生状態に切換えたとする
。特殊再生を行なうと水平同期信号の欠落や周期の変動
が起こる。すると、端子(6)からの水平同期信号が印
加される水平同期信号検出回路(17)が、正常な周期
で水平同期信号が到来していないことを検出し、その検
出出力に応じてスイッチ(18)を開く。その為、周波
数識別回路(14)からの異常な制御信号がV CO(
16)に加わることが禁止される。
Assume that the VTR is switched from this state to the special playback state. When special playback is performed, the horizontal synchronization signal may be missing or the period may fluctuate. Then, the horizontal synchronization signal detection circuit (17) to which the horizontal synchronization signal from the terminal (6) is applied detects that the horizontal synchronization signal does not arrive at a normal cycle, and switches the switch ( 18) Open. Therefore, an abnormal control signal from the frequency identification circuit (14) is transmitted to V CO (
16) is prohibited.

又、水平同期信号が変動すると、位相比較回路り13〉
の動作が停止されるので、その出力端は開放状態となり
、ローパスフィルタ(16)は、変動前の電圧を保持し
たままとなる。
Also, when the horizontal synchronization signal fluctuates, the phase comparator circuit 13
Since its operation is stopped, its output terminal becomes open, and the low-pass filter (16) continues to hold the voltage before fluctuation.

従って、V CO(4)は、変動前の安定した周波数で
の発振が可能となる。
Therefore, the VCO (4) can oscillate at a stable frequency before fluctuations.

第2図は、第1図の水平同期信号検出回路(17)の具
体回路例を示すもので、(19)は発振器(3)からの
3.58MHzの信号をクロック信号として計数し、該
クロック信号をN個計数すると出力信号を発生すると共
に、端子(6〉からの水平同期信号に応じてリセットさ
れるN進カウンタ、(20〉は前記N進カウンタ(19
)の出力信号が端子(21)からの特殊再生を示す制御
信号で導通が制御されるアンドゲート、及び(22)は
端子(6)からの水平同期信号及び前記アンドゲート(
20)の出力信号に応じて反転するフリップフロップで
ある。前記クロック信号f’sc周波数は3.58MH
zで、リセット信号f。
FIG. 2 shows a specific circuit example of the horizontal synchronization signal detection circuit (17) in FIG. When N signals are counted, an output signal is generated, and an N-ary counter (20) is reset in response to a horizontal synchronizing signal from a terminal (6>).
) is an AND gate whose conduction is controlled by a control signal indicating special reproduction from the terminal (21), and (22) is a horizontal synchronization signal from the terminal (6) and the AND gate (
20) is a flip-flop that is inverted in accordance with the output signal of 20). The clock signal f'sc frequency is 3.58MH
z and the reset signal f.

の周波数は15.734KHzであるので、N進カウン
タ(19〉の計数値Nは、N > f sc/ f’ 
o:227 。
Since the frequency of is 15.734KHz, the count value N of the N-ary counter (19) is N > f sc/
o:227.

5と設定される。その為、Nを例えば230に設定する
。今、端子(6)から正規の周期の水平同期信号が到来
したとする。すると、前記N進カウンタ(19)は22
7.5カウント毎にリセットされるので、出力信号を発
生しない。その為、アンドゲート(20)の出力信号は
r L 、レベルのままでありブリップフロップ(22
)はリセット状態で出力端子(23)はr L Jレベ
ルとなる。次に特殊再生を行ない、前記水平同期信号の
欠落が生じたとする。
It is set as 5. Therefore, N is set to 230, for example. Assume now that a horizontal synchronizing signal with a regular period arrives from terminal (6). Then, the N-ary counter (19) becomes 22
Since it is reset every 7.5 counts, no output signal is generated. Therefore, the output signal of the AND gate (20) remains at r L level and the output signal of the flip-flop (22
) is in the reset state and the output terminal (23) is at the rLJ level. Next, assume that special playback is performed and the horizontal synchronization signal is missing.

すると、N進カウンタ(19)は、クロック信号の計数
を227.5カウント後も続け、230カウントでrH
,レベルの出力信号をアンドゲート(20)に印加する
。アンドゲート(20)の他方の入力には端子(21)
から得られる制御信号が印加されているので、その出力
は’HJレベルとなり、フリッププロップ(22〉をセ
ットする。その為、出力端子(23)には水平同期信号
の欠落を示すrH,レベルの出力を得る乙とが出来る。
Then, the N-ary counter (19) continues counting the clock signal even after 227.5 counts, and at 230 counts, rH
, is applied to the AND gate (20). The other input of the AND gate (20) has a terminal (21)
Since the control signal obtained from the horizontal synchronization signal is applied, its output becomes 'HJ level, and the flip-flop (22) is set. Therefore, the output terminal (23) has rH, which indicates the lack of horizontal synchronization signal, and the level of It is possible to obtain output.

尚、第2図の例においては、特殊再生時のみ水平同期信
号検出回路(17)を動作させる為、アンドゲート(2
0)を設けたが、通常再生の場合にも動作させたい場合
にはN進カウンタ(19)の出力を直接フリップフロッ
プ(22)に印加させても良い。
In the example shown in Figure 2, in order to operate the horizontal synchronizing signal detection circuit (17) only during special playback, the AND gate (2
0), but if it is desired to operate it also in normal playback, the output of the N-ary counter (19) may be applied directly to the flip-flop (22).

(ト)発明の効果 以上述べた如く、本発明に依ればvCOの発振周波数を
制御する為の周波数識別回路を備えたVTRを再生する
のに際し、水平同期信号の状態変動を検出し、その検出
出力に応じて前記周波数識別口路の動作を禁止している
ので、前記VCOは異常な制御電圧を受+−+なくなり
、変動前の所定の周波数で発振することが出来る。その
為、特殊再生時においても安定に搬送色信号を周波数変
換することが出来る。
(G) Effects of the Invention As described above, according to the present invention, when reproducing a VTR equipped with a frequency identification circuit for controlling the oscillation frequency of the vCO, a change in the state of the horizontal synchronizing signal is detected. Since the operation of the frequency discrimination path is prohibited according to the detected output, the VCO no longer receives an abnormal control voltage and can oscillate at a predetermined frequency before fluctuation. Therefore, the frequency of the carrier color signal can be stably converted even during special reproduction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す回路図、及び第2図
は第1図の水平同期信号検出回路(17)の具体回路例
を示す回路図である。 (3)・・・発振器、 (4)・・・VCO,(13)
・・・位相比較回路、 (14)・・・周波数識別回路
、 (17)・・・水平同期信号検出回路、 (18)
・・・スイッチ。
FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a specific circuit example of the horizontal synchronization signal detection circuit (17) of FIG. 1. (3)...Oscillator, (4)...VCO, (13)
...Phase comparison circuit, (14) ...Frequency discrimination circuit, (17) ...Horizontal synchronization signal detection circuit, (18)
···switch.

Claims (2)

【特許請求の範囲】[Claims] (1)発振器の発振出力信号とバースト信号との位相比
較により発振が制御される電圧制御型発振器と、 前記電圧制御型発振器の発振周波数を基準信号に基づき
識別し該識別出力に応じて前記電圧制御型発振器の発振
を制御する周波数識別回路を少なくとも有するサイドロ
ック防止回路において、前記水平同期信号の状態を検出
する水平同期信号検出回路を設け、該水平同期信号検出
回路の検出出力に応じて前記周波数識別回路の出力信号
が前記電圧制御型発振器に加わるのを禁止したことを特
徴とするサイドロック防止回路。
(1) A voltage-controlled oscillator whose oscillation is controlled by phase comparison between an oscillation output signal of the oscillator and a burst signal, and a voltage-controlled oscillator that identifies the oscillation frequency of the voltage-controlled oscillator based on a reference signal and adjusts the voltage according to the identified output. In a sidelock prevention circuit having at least a frequency identification circuit for controlling oscillation of a controlled oscillator, a horizontal synchronization signal detection circuit for detecting the state of the horizontal synchronization signal is provided, and the sidelock prevention circuit includes a horizontal synchronization signal detection circuit for detecting the state of the horizontal synchronization signal, and A side lock prevention circuit characterized in that the output signal of the frequency identification circuit is prohibited from being applied to the voltage controlled oscillator.
(2)前記水平同期信号検出回路は、所定周波数の信号
をクロックパルスとし、水平同期信号に応じてリセット
されるカウンタと、 該カウンタの出力信号と前記水平同期信号に応じて反転
するフリップフロップと から成り、前記フリップフロップの出力に応じて水平同
期信号の状態を検出することを特徴とする請求項第1項
記載のサイドロック防止回路。
(2) The horizontal synchronization signal detection circuit uses a signal of a predetermined frequency as a clock pulse, and includes a counter that is reset according to the horizontal synchronization signal, and a flip-flop that is inverted according to the output signal of the counter and the horizontal synchronization signal. 2. The sidelock prevention circuit according to claim 1, wherein the sidelock prevention circuit detects the state of a horizontal synchronizing signal according to the output of the flip-flop.
JP1039947A 1989-02-20 1989-02-20 Side lock prevention circuit Pending JPH02219396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1039947A JPH02219396A (en) 1989-02-20 1989-02-20 Side lock prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1039947A JPH02219396A (en) 1989-02-20 1989-02-20 Side lock prevention circuit

Publications (1)

Publication Number Publication Date
JPH02219396A true JPH02219396A (en) 1990-08-31

Family

ID=12567153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1039947A Pending JPH02219396A (en) 1989-02-20 1989-02-20 Side lock prevention circuit

Country Status (1)

Country Link
JP (1) JPH02219396A (en)

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