JPH02219214A - Formation of soi film - Google Patents
Formation of soi filmInfo
- Publication number
- JPH02219214A JPH02219214A JP4127689A JP4127689A JPH02219214A JP H02219214 A JPH02219214 A JP H02219214A JP 4127689 A JP4127689 A JP 4127689A JP 4127689 A JP4127689 A JP 4127689A JP H02219214 A JPH02219214 A JP H02219214A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- exposed surface
- amorphous silicon
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title description 10
- 239000010408 film Substances 0.000 claims abstract description 56
- 239000010409 thin film Substances 0.000 claims abstract description 53
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000007790 solid phase Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims description 4
- 229910052754 neon Inorganic materials 0.000 claims description 4
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 239000012212 insulator Substances 0.000 abstract 1
- 239000013081 microcrystal Substances 0.000 abstract 1
- 238000000348 solid-phase epitaxy Methods 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、単結晶シリコン基板とに絶縁膜を形成し、さ
らにこの絶縁膜上に単結晶シリコン膜を成長させてＳＯ
Ｉ Ｃ５ｉｌｉｃｏｎ Ｏｎ Ｉｎ５ｕｌａｔｏｒ）膜
を形成するＳＯＩ膜の形成方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention involves forming an insulating film on a single-crystal silicon substrate, and further growing a single-crystal silicon film on this insulating film.
The present invention relates to a method for forming an SOI film for forming an IC5 silicon on injector film.
一般に、ＳＯＩ膜は、集積回路の高速化、高密度化を図
れるだけでなく、ソフトエラーやラッチアップを防ぐこ
とが可能であり、信頼性の向上を図れるという優れた特
徴を有するため、集積回路。In general, SOI films have excellent features such as not only increasing the speed and density of integrated circuits, but also preventing soft errors and latch-ups, and improving reliability. .
特に３次元回路素子の材料として注目され、近年盛んに
研究開発が進められている。It has attracted particular attention as a material for three-dimensional circuit elements, and has been actively researched and developed in recent years.
ところで、このようなＳＯＩ膜を形成する技術として、
例えば結晶性絶縁膜上に単結晶シリコンを気相エピタキ
シャル成長させる方法やレーザアニルによる再結晶化法
或いは固相エピタキシャル成長（以下ＳＰＥという）法
などがあり、このうちＳＰＥ法は、比較的低温でＳＯＩ
膜の形成が可能であるため、３次元回路素子の形成技術
として研究が行われている。By the way, as a technique for forming such an SOI film,
For example, there are methods such as vapor phase epitaxial growth of single crystal silicon on a crystalline insulating film, recrystallization method using laser annealing, and solid phase epitaxial growth (hereinafter referred to as SPE).
Since it is possible to form a film, research is being conducted as a technology for forming three-dimensional circuit elements.
そして、このＳＰＥ法によりＳＯＸ膜を形成する方法を
簡単に説明すると、単結晶シリコン基板（以下Ｓｉ基板
という）上に絶縁膜として例えば酸化シリコン［５１０
２）膜を形成し、このＳ ｉｏ２膜の一部を除去してＳ
ｉ基板に露出面を形成し、５ｉＯｚ膜上及びこの露出面
上に非晶質シリコン（以下ａ−５ｉという）薄膜を形成
したのち、約６００℃でアニールし、露出面上では縦方
向の５ＰＥ（以下Ｖ−５ＰＥという）。To briefly explain the method of forming a SOX film by this SPE method, an insulating film is formed on a single crystal silicon substrate (hereinafter referred to as a Si substrate) using, for example, silicon oxide [510
2) Form a film and remove a part of this S io2 film to
After forming an exposed surface on the i-substrate and forming an amorphous silicon (hereinafter referred to as a-5i) thin film on the 5iOz film and this exposed surface, it is annealed at about 600°C, and 5PE is formed in the vertical direction on the exposed surface. (hereinafter referred to as V-5PE).
Ｓ ｉ０２膜上では横方向の５ＰＥ（以下Ｌ−３ＰＥと
いう）により、ａ−３ｉ薄膜を単結晶化し、ＳＯＸ膜を
形成するものである。On the Si02 film, the a-3i thin film is single crystallized by lateral 5PE (hereinafter referred to as L-3PE) to form a SOX film.
しかし、この場合、Ｖ−５ＰＥがＳｉ基板の露出面をシ
ートとして進行し、このときＳ ｉｏｚ膜とＳｉ基板の
露出面との段差が大きいため、この段差部分で残留応力
が発生し、Ｓ ｉＯｚとｓｌ’の界面に歪が生じ、Ｌ−
３ＰＥのファセットが形成されて成長が妨げられ、十分
なＬ−８ＰＥ距離が得られないという不都合が生じる。However, in this case, V-5PE advances as a sheet on the exposed surface of the Si substrate, and at this time, since there is a large step difference between the SiOz film and the exposed surface of the Si substrate, residual stress is generated at this step portion, and the SiOz Strain occurs at the interface between and sl', and L-
The formation of 3PE facets impedes growth, resulting in the inconvenience that a sufficient L-8PE distance cannot be obtained.
そこで従来、このような不都合を解消する手法として、
８１基板の露出面上に単結晶Ｓｉのシートを予め形成す
る方法が提案されており、この方法（こよるＳＯＸ膜の
形成は第４図に示す手順によってなされる。Conventionally, as a method to resolve this inconvenience,
A method has been proposed in which a sheet of single-crystal Si is previously formed on the exposed surface of a 81 substrate, and this method (formation of the SOX film is performed by the procedure shown in FIG. 4).
即ち、第４図（ａ）に示すように、５１基板ｉｌｌ上に
３１０２膜（２）をパターン形成し、Ｓｉ基板ｆ１＋の
露出面（３）を形成し、同図（ｂ）に示すように、５１
０２膜（２）上及び露出面（３）上にａ−５ｉ薄膜（４
）を形成し、同図（Ｃ）に示すように、１〜１．５時間
程度のアニールを行い、露出面（３）上のａ−８ｉ薄膜
（４）をＶ−３ｐＦ、により単結晶化してシート部（５
）を形成したのち、同図（ｄ） ｉこ示すようにａ−５
１薄膜（４）を選択エツチングにより除去する。That is, as shown in FIG. 4(a), a 3102 film (2) is patterned on the 51 substrate ill to form the exposed surface (3) of the Si substrate f1+, and as shown in FIG. , 51
02 film (2) and the exposed surface (3).
), and as shown in the same figure (C), annealing was performed for about 1 to 1.5 hours, and the a-8i thin film (4) on the exposed surface (3) was made into a single crystal at V-3 pF. and the seat part (5
), then form a-5 as shown in Figure (d) i.
1 thin film (4) is removed by selective etching.
つぎに、第４図（ｅ）に示すように、Ｓ ｉＯｚ膜（２
）上及びシート部（５）上にａ−５ｉ薄膜（６）を形成
し、同図（ｆ）に示すように、このａ−５ｌ薄膜（６）
に活性不純物であるリンＣＰ） ｋイオン注入したのち
、同図（ｇ）に示すように、アニールを行ってａ−３１
薄膜（６）をＬ−８ＰＥにより単結晶化し、単結晶Ｓ１
薄膜（以下Ｃ−５ｌ薄膜という） （６）’を形成し、
ＳＯＸ膜を形成する。Next, as shown in FIG. 4(e), a SiOz film (2
) and on the sheet part (5), and as shown in FIG.
After implanting phosphorus (CP)k ions, which are active impurities, into a-31, annealing is performed as shown in Figure (g).
The thin film (6) was single-crystalized using L-8PE to form a single crystal S1.
forming a thin film (hereinafter referred to as C-5l thin film) (6)';
Form a SOX film.
このように、Ｓｉ基板（１）の露出面（３）上に予め単
結晶Ｓｉのシート部（５）を形成することによって、５
ｉＯｚ膜（２）が数μｍと厚い場合であっても、Ｖ−８
ＰＥ工程で従来のような残留応力が発生することがなく
、Ｌ−５ＰＥのファセットの形成も抑えられ、Ｌ−５Ｐ
Ｅ距離の拡大を図ることができ、大面積のｃ−５ｉ薄膜
（６）′を得ることが可能となる。In this way, by forming the single crystal Si sheet portion (5) in advance on the exposed surface (3) of the Si substrate (1), the 5
Even if the iOz film (2) is several μm thick, V-8
There is no residual stress generated in the PE process, and the formation of facets on L-5PE is suppressed.
The E distance can be increased, and a c-5i thin film (6)' with a large area can be obtained.
従来の場合、Ｓｉ基板（１〕の露出面＋３１上のａ−５
ｉ薄膜（４）をＶ−５ＰＨにより単結晶化してシート部
（５）を形成するため、シート部（５）のＳ ｉＯｚ膜
（２）の段差部上に凸状の盛り上がりが生じ、この盛り
上がりによってＳｏｌ膜の平坦性が損われ、積層構造の
３次元回路素子を作製する上で大きな支障となり、良好
な素子を作製することができないという問題点がある。In the conventional case, a-5 on the exposed surface +31 of the Si substrate (1)
Since the i-thin film (4) is single-crystalized using V-5PH to form the sheet portion (5), a convex bulge is formed on the stepped portion of the SiOz film (2) in the sheet portion (5). This impairs the flatness of the Sol film, which becomes a major hindrance in producing a three-dimensional circuit element with a laminated structure, and there is a problem that a good element cannot be produced.
本発明は、前記の点に留意してなされ、平坦性の優れた
５０１膜を形成できるようにし、良好な３次元回路素子
の作製を可能にすることを目的とする。The present invention has been made with the above points in mind, and an object of the present invention is to make it possible to form a 501 film with excellent flatness and to make it possible to manufacture a good three-dimensional circuit element.
前記目的を達成するために、本発明のＳＯＸ膜の形成方
法では、単結晶シリコン基板とに絶縁膜を形成し、前記
絶縁膜の一部を除去して前記基板に露出面を形成し、前
記絶縁膜上及び前記露出面上に第１の非晶質シリコン薄
膜を形成し、前記第１の非晶質シリコン薄膜の表層部に
アルゴン、ネオン、酸素、窒素などの不活性不純物をイ
オン注入したのち、前記露出面上の前記第１の非晶質シ
リコン薄膜を固相エピタキシャル成長法をこより単結晶
化し、前記露出面上に単結晶シリコンのシート部を形成
し、選択エツチングにより前記シート部を残して前記第
１の非晶質シリコン薄膜を除去し、前記絶縁膜上及び前
記シート部上に％２の非晶質シリコン薄膜を形成し、前
記第２の非晶質シリコン薄膜にリンをイオン注入したの
ち、前記第２の非晶質シリコン薄膜を固相エピタキシャ
ル成長法により単結晶化することを特徴としている。In order to achieve the above object, in the method for forming an SOX film of the present invention, an insulating film is formed on a single crystal silicon substrate, a part of the insulating film is removed to form an exposed surface on the substrate, and the A first amorphous silicon thin film was formed on the insulating film and the exposed surface, and inert impurities such as argon, neon, oxygen, and nitrogen were ion-implanted into the surface layer of the first amorphous silicon thin film. Thereafter, the first amorphous silicon thin film on the exposed surface is made into a single crystal by solid phase epitaxial growth, a sheet portion of single crystal silicon is formed on the exposed surface, and the sheet portion is left by selective etching. %2 amorphous silicon thin film is formed on the insulating film and the sheet portion, and ion implantation of phosphorus into the second amorphous silicon thin film is performed. After that, the second amorphous silicon thin film is made into a single crystal by solid phase epitaxial growth.
以上のような構成において、第１の非晶質シリコン薄膜
の表層部にアルゴン、ネオン、酸素、窒素などの不活性
不純物をイオン注入したのち、露出面上の第１の非晶質
シリコン薄膜をＶ−３ＰＥにより単結晶化してシート部
を形成したため、シト部に従来のような盛り上がりの生
じることが防止され、平坦性の優れたＳＯＩ膜が形成さ
れる。In the above structure, after inert impurities such as argon, neon, oxygen, nitrogen, etc. are ion-implanted into the surface layer of the first amorphous silicon thin film, the first amorphous silicon thin film on the exposed surface is implanted. Since the sheet portion is formed by single crystallization using V-3PE, the formation of a bulge in the sheet portion as in the conventional case is prevented, and an SOI film with excellent flatness is formed.
ところで、非晶質シリコンに不活性不純物をイオン注入
すると、例えばＪｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ
Ｐｈｙｓｉｃｓ 、 Ｖｏｌ ・４３ 、 Ｎｏ −１
０，０ｃｔｏｒｂｅｒ １９７７、Ｐ４２４１−４２４
６において、非晶質シリコンのアニールの際、再結晶化
率の抑制効果が得られることが報告され、Ｊｏｕｒｎａ
ｌ ｏｆ Ｖａｃｕｕｍ ５ｃｉｅｎｃｅ Ｔｅｃｈｎ
ｏｌｏｇｙ 、 １５１５）。By the way, when inert impurities are ion-implanted into amorphous silicon, for example, Journal of Applied
Physics, Vol.43, No-1
0,0ctorber 1977, P4241-424
6, it was reported that the recrystallization rate could be suppressed during annealing of amorphous silicon, and Journal
l of Vacuum 5science Techn
ology, 1515).
５ｅｐｔ、１０ｃｔ、 １９７８ 、 Ｐ１６５６−１
６６１では、不活性不純物のイオン注入によって、ａ−
３ｌの注入領域中に気泡の存在が認められ、６００°Ｃ
のアニールを行っても、注入領域中では約２００大のＳ
ｉの微結晶粒の堆積が見られるだけで、再結晶化が強く
抑制されることが報告されている。5ept, 10ct, 1978, P1656-1
In 661, a-
The presence of air bubbles was observed in the injection area of 3 liters, and the temperature at 600°C
Even after annealing, about 200 S
It has been reported that recrystallization is strongly suppressed when only the accumulation of microcrystalline grains of i is observed.
これらの結果から、不活性不純物のイオン注入によって
、第１の非晶質シリコン薄膜の表層部が微結晶化し、そ
の後アニールによって単結晶化しても、露出面上の第１
の非晶質シリコン薄膜の上方への単結晶化の進行が微結
晶の表層部によって抑えられるため、露出面上の単結晶
シリコンのシト部の盛り上がりの防止が可能となる。From these results, even if the surface layer of the first amorphous silicon thin film is microcrystalized by ion implantation of inert impurities and then made into a single crystal by annealing, the first amorphous silicon thin film on the exposed surface is
Since the progress of single crystallization upward of the amorphous silicon thin film is suppressed by the microcrystalline surface layer, it is possible to prevent the swell of the single crystal silicon on the exposed surface.
実施例についてｉ１図ないし第３図を参照して説明する
。An embodiment will be described with reference to FIGS. i1 to 3.
まず、第１図（ａ）に示すように、第４図の場合と同様
に、（１００） Ｓｌ基板（７）上に、ウェット法によ
り絶縁膜としての厚さ１μｍのＳ ｉｏｚ膜（８）を形
成し、これを（１００）方向にパターニングし、溝（９
）を形成して３１基板（７）の露出面（１０）を形成す
る。First, as shown in FIG. 1(a), as in the case of FIG. 4, a 1 μm thick SiOZ film (8) as an insulating film is deposited on a (100) Sl substrate (7) by a wet method. is formed and patterned in the (100) direction to form a groove (9
) to form the exposed surface (10) of the 31 substrate (7).
つぎに、５ Ｘ １Ｏ−７Ｔｏｒｒの高真空中でｓｉ基
板（７）ヲ８００°Ｃに加熱し、１５０３ＣＣＭ、分圧
５５ｍＴｏ ｒ ｒのＡｒガスを通流し、３１基板（７
）に−５０Ｖの直流バイアスをかけ、１ ａ、５６ Ｍ
Ｈｚ ｓ ７０’Ｗの高周波を印加しテＡｒイオンを生
成し、ＡｒイオンのスパッタリングによりＳｉ基板ｉ７
） 、 ５ｉ０２膜（８）の表面を５分間クリーニング
し、その後Ａｒガス、高周波、直流バイアスを止め、Ｓ
ｉ基板（７）を５５０°Ｃまで降温し、５ｉＨ４（モノ
シラン）ガスを２００ＳＣＣＭの流量で流し、第１図（
１））に示すように、５ｉ０２膜（８）上及び露出面皿
上に第１の非晶質シリコン薄膜（以下第１のａ−３ｉ薄
膜という）（１１）を堆積形成する。Next, the Si substrate (7) was heated to 800°C in a high vacuum of 5 x 10-7 Torr, and Ar gas of 1503 CCM and partial pressure of 55 mTorr was passed through it to form 31 substrates (7).
) with a DC bias of -50 V, 1 a, 56 M
A high frequency of Hz s 70'W is applied to generate TeAr ions, and the Si substrate i7 is sputtered by Ar ions.
), the surface of the 5i02 film (8) was cleaned for 5 minutes, then Ar gas, high frequency, and DC bias were stopped, and S
The temperature of the i-substrate (7) was lowered to 550°C, and 5iH4 (monosilane) gas was flowed at a flow rate of 200SCCM.
As shown in 1)), a first amorphous silicon thin film (hereinafter referred to as the first a-3i thin film) (11) is deposited on the 5i02 film (8) and the exposed surface plate.
なお、Ｓ ｉＨ４ガスの分圧を６”ｒｏｒｒとし、堆積
速度を２００人／ｍｉｎで、１時間の堆積を行い、厚さ
１．２μｍの第１のａ−５ｉ薄膜（１すを形成する。Incidentally, the partial pressure of SiH4 gas was set to 6''rorr, and the deposition was performed for 1 hour at a deposition rate of 200 people/min to form the first a-5i thin film (1 layer) with a thickness of 1.2 μm.
そして、第１図（ｃ）に示すように、第１のａ−５ｉ薄
膜（１りの表層部にＡｒのイオン注入を行い、このとき
のイオン注入条件は、
ところで、Ａｒイオンの注入深さは第２図に示すようを
こなり、ピーク濃度はほぼ３×１０２０（ｃｌｎ−３）
であり、第１のａ−３ｉ薄膜（ＩＩ）の表面から約３５
０ＯＡの深さまでほぼ均一に注入されることがわかる。Then, as shown in FIG. 1(c), Ar ions were implanted into the surface layer of the first a-5i thin film (1), and the ion implantation conditions at this time were as follows: is as shown in Figure 2, and the peak concentration is approximately 3 x 1020 (cln-3).
and about 35 mm from the surface of the first a-3i thin film (II)
It can be seen that the implantation is almost uniform to a depth of 0OA.
つぎに、Ａｒイオンの注入後、Ｎ２雰囲気中において約
６００°Ｃで２時間のアニールを行い、第１図（ｄ）に
示すように、露出面（１０）上の第１のａ−８ｉ薄膜（
１１）をＶ−８ＰＨにより単結晶化し、露出面（ＩＯ）
上に単結晶Ｓｉのシート部（１２）を形成する。Next, after implanting Ar ions, annealing is performed at approximately 600°C for 2 hours in a N2 atmosphere, and as shown in FIG. 1(d), the first a-8i thin film on the exposed surface (10) is (
11) was single-crystalized using V-8PH, and the exposed surface (IO)
A sheet portion (12) of single crystal Si is formed on top.
このとき、アニール時間とＶ−８ＰＥ距離との関係は第
３図（こ示すようになり、２時間のアニールで０．９μ
ｍのＶ−３ＰＥ距離が得られる。At this time, the relationship between the annealing time and the V-8PE distance is shown in Figure 3 (shown here).
A V-3PE distance of m is obtained.
さらに、Ｖ−５ＰＥの終了後、酢酸 フッ酸 硝酸、水
−１６０： ７０ ： ４．５ 、１０の割合のエツチ
ング液ヲ用い、約１０分間のエツチングにより、第１図
（ｅ）に示すように、Ｓ ｉｏ２膜（８）上の第１のａ
−５ｉ薄膜（１１）及びＡｒイオン注注入−を除去し、
充分に洗浄したのち、同図（ａ）のＡｒイオンのスパッ
タクリーニングと同じ条件でクリーニングを行い、その
後同図（ｆ）に示すように、５５０°Ｃの基板温度で８
１０２膜（８）上及びシト部（１２）上に厚さ３０００
’ｈの第２の非晶質シリコン薄膜（以下第２のａ−８
ｉ薄膜という） （＋３）を形成する。Furthermore, after V-5PE was completed, etching was performed for about 10 minutes using an etching solution of acetic acid, hydrofluoric acid, nitric acid, and water in a ratio of 160:70:4.5 and 10, as shown in Figure 1(e). , the first a on the S io2 film (8)
-Remove the 5i thin film (11) and Ar ion implantation,
After thorough cleaning, cleaning was performed under the same conditions as the Ar ion sputter cleaning shown in (a) of the same figure, and then, as shown in (f) of the same figure, the substrate temperature was 850°C.
102 thickness on the membrane (8) and on the seat part (12)
'h second amorphous silicon thin film (hereinafter referred to as second a-8
(referred to as i thin film) (+3) is formed.
つぎに、第１図（ｇ）に示すように、第２のと５１薄膜
（１３）に活性不純物であるＰをイオン注入し、こので
あり、その後６００℃でアニールを行い、同図（ｈ）に
示すように、第２のａ−８ｉ薄膜θ３）をＬ−８ＰＨに
より単結晶化して単結晶Ｓ１薄膜（以下ｃ−３ｉ薄膜と
いう） （１４＋を形成し、ｓｏｉ膜を形成する。Next, as shown in FIG. 1(g), ions of P, which is an active impurity, are implanted into the second thin film (13), and then annealing is performed at 600°C. ), the second a-8i thin film θ3) is single crystallized by L-8PH to form a single crystal S1 thin film (hereinafter referred to as c-3i thin film) (14+) to form a soi film.
このように、第１のａ−３ｉ薄膜（１１）の表層部に不
活性不純物をイオン注入することをこより、＠１のａ−
ｓｉ薄膜（１１）の表層部が微結晶化し、この表層部に
よってＶ−３ＰＨの進行を抑えることができるため、そ
の後露出面（１０）上の第１のａ−８ｉ薄膜（１りをＶ
−３ＰＥにより単結晶化してシート部（１２）を形成し
ても、シト部（１２）に従来のような盛り上がりが生じ
ることを防止でき、従来より平坦性の優れたＳＯＩ膜を
形成することができ、２層以上の積層構造の良好な３次
元回路素子の作製が可能になる。In this way, by ion-implanting inert impurities into the surface layer of the first a-3i thin film (11), the a-3i
The surface layer of the Si thin film (11) becomes microcrystalline, and this surface layer can suppress the progression of V-3PH.
-Even if the sheet portion (12) is formed by single crystallization using 3PE, it is possible to prevent the formation of a bulge in the sheet portion (12) as in the conventional method, and it is possible to form an SOI film with better flatness than in the past. This makes it possible to fabricate a three-dimensional circuit element with a good laminated structure of two or more layers.
また、露出面（１０ｊ上に予め平坦なシート部（１２）
を形成するため、従来の場合と同様、残留応力の発生を
ＦＪ止でき、Ｌ−３ＰＥのファセットの形成を抑制でき
、Ｌ−５ＰＥ距離の拡大を図ることが可能となり、例え
ば１μｍの厚さのＳ ｉｏ２膜（８）上に形成したＣ−
３ｉ薄膜（１４）のＬ−３ＰＥ距離として、従来と同程
度の２０μｍを達成することができ、大面積のｃ−５ｉ
薄膜（Ｉ４）の形成が可能となる。In addition, a flat sheet portion (12) is provided on the exposed surface (10j).
As in the conventional case, it is possible to prevent the generation of residual stress in the FJ, suppress the formation of L-3PE facets, and increase the L-5PE distance. C- formed on the Sio2 film (8)
The L-3PE distance of the 3i thin film (14) can be achieved at 20 μm, which is similar to the conventional method, and the large area c-5i
Formation of a thin film (I4) becomes possible.
本発明は、以北説明したように構成されているので、以
下に記載する効果を奏する。Since the present invention is configured as described above, it produces the effects described below.
第１の非晶質シリコン薄膜の表層部にアルゴン。Argon is applied to the surface layer of the first amorphous silicon thin film.
ネオン、酸素、窒素などの不活性不純物をイオン注入し
たのち、露出面上の第１の非晶質シリコン薄膜をＶ−５
ＰＥにより単結晶化してシート部を形成したため、シー
ト部（こ従来のような盛りとがりが生じることを防止で
き、平坦性の優れたＳｏｌ膜を形成することができ、２
層以上の積層構造の良好な３次元回路素子を作製するこ
とが可能となる。After ion-implanting inert impurities such as neon, oxygen, and nitrogen, the first amorphous silicon thin film on the exposed surface was heated to V-5.
Since the sheet portion is formed by single crystallization using PE, it is possible to prevent the formation of a bulge as in the conventional sheet portion, and it is possible to form a Sol film with excellent flatness.
It becomes possible to produce a three-dimensional circuit element with a good laminated structure of layers or more.
第１図ないし％３図は本発明のＳＯＩ膜の形成方法の１
実施例を示し、第１図（ａ）〜（ｈ）は形成工程を示す
断面図、第２図は注入深さとＡｒ＋濃度との関係図、第
３図はアニール時間とＶ−５ＰＥ距離との関係図、第４
図（ａ）〜（ｇ）は従来例の形成工程を示す断面図であ
る。
（７）−・５１基板、＋８） −Ｓ Ｉ０２膜、（１０
）・露出面、（ｌｌ）−第１のａ−８ｉ薄膜、（１２１
シート部、（＋３）−第２のａ−５ｉ薄膜、（１４）・
・・ｃ−５ｉ薄膜。Figures 1 to 3 show a method of forming an SOI film according to the present invention.
Examples are shown, and FIGS. 1(a) to (h) are cross-sectional views showing the formation process, FIG. 2 is a relationship between implantation depth and Ar+ concentration, and FIG. 3 is a relationship between annealing time and V-5PE distance. Relationship diagram, 4th
Figures (a) to (g) are cross-sectional views showing the forming process of a conventional example. (7) -・51 substrate, +8) -S I02 film, (10
)・Exposed surface, (ll)-first a-8i thin film, (121
Sheet part, (+3)-second a-5i thin film, (14)・
...c-5i thin film.
Claims (1)
縁膜の一部を除去して前記基板に露出面を形成し、前記
絶縁膜上及び前記露出面上に第１の非晶質シリコン薄膜
を形成し、前記第１の非晶質シリコン薄膜の表層部にア
ルゴン、ネオン、酸素、窒素などの不活性不純物をイオ
ン注入したのち、前記露出面上の前記第１の非晶質シリ
コン薄膜を固相エピタキシャル成長法により単結晶化し
、前記露出面上に単結晶シリコンのシート部を形成し、
選択エッチングにより前記シート部を残して前記第１の
非晶質シリコン薄膜を除去し、前記絶縁膜上及び前記シ
ート部上に第２の非晶質シリコン薄膜を形成し、前記第
２の非晶質シリコン薄膜にリンをイオン注入したのち、
前記第２の非晶質シリコン薄膜を固相エピタキシャル成
長法により単結晶化することを特徴とするＳＯＩ膜の形
成方法。(1) An insulating film is formed on a single crystal silicon substrate, a part of the insulating film is removed to form an exposed surface on the substrate, and a first amorphous layer is formed on the insulating film and the exposed surface. After forming a silicon thin film and implanting ions of inert impurities such as argon, neon, oxygen, and nitrogen into the surface layer of the first amorphous silicon thin film, the first amorphous silicon on the exposed surface is Single crystallizing the thin film by a solid phase epitaxial growth method, forming a sheet portion of single crystal silicon on the exposed surface,
The first amorphous silicon thin film is removed by selective etching leaving the sheet portion, a second amorphous silicon thin film is formed on the insulating film and the sheet portion, and the second amorphous silicon thin film is removed by selective etching. After ion-implanting phosphorus into a thin silicon film,
A method for forming an SOI film, characterized in that the second amorphous silicon thin film is made into a single crystal by solid phase epitaxial growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1041276A JP2762097B2 (en) | 1989-02-20 | 1989-02-20 | Method for forming SOI film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1041276A JP2762097B2 (en) | 1989-02-20 | 1989-02-20 | Method for forming SOI film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02219214A true JPH02219214A (en) | 1990-08-31 |
| JP2762097B2 JP2762097B2 (en) | 1998-06-04 |
Family
ID=12603922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1041276A Expired - Fee Related JP2762097B2 (en) | 1989-02-20 | 1989-02-20 | Method for forming SOI film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762097B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60152018A (en) * | 1984-01-20 | 1985-08-10 | Agency Of Ind Science & Technol | Manufacture of semiconductor thin film crystal layer |
| JPS6158879A (en) * | 1984-08-29 | 1986-03-26 | Nec Corp | Preparation of silicon thin film crystal |
| JPS62239520A (en) * | 1986-04-11 | 1987-10-20 | Nec Corp | Formation of soi film |
-
1989
- 1989-02-20 JP JP1041276A patent/JP2762097B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60152018A (en) * | 1984-01-20 | 1985-08-10 | Agency Of Ind Science & Technol | Manufacture of semiconductor thin film crystal layer |
| JPS6158879A (en) * | 1984-08-29 | 1986-03-26 | Nec Corp | Preparation of silicon thin film crystal |
| JPS62239520A (en) * | 1986-04-11 | 1987-10-20 | Nec Corp | Formation of soi film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762097B2 (en) | 1998-06-04 |
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