JPH02215173A - Switching element and manufacture thereof - Google Patents

Switching element and manufacture thereof

Info

Publication number
JPH02215173A
JPH02215173A JP1035113A JP3511389A JPH02215173A JP H02215173 A JPH02215173 A JP H02215173A JP 1035113 A JP1035113 A JP 1035113A JP 3511389 A JP3511389 A JP 3511389A JP H02215173 A JPH02215173 A JP H02215173A
Authority
JP
Japan
Prior art keywords
organic insulating
electrodes
electrode
switching element
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1035113A
Other languages
Japanese (ja)
Inventor
Yuuko Morikawa
森川 有子
Kunihiro Sakai
酒井 邦裕
Kiyoshi Takimoto
瀧本 清
Osamu Takamatsu
修 高松
Harunori Kawada
河田 春紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1035113A priority Critical patent/JPH02215173A/en
Publication of JPH02215173A publication Critical patent/JPH02215173A/en
Pending legal-status Critical Current

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  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve a switching element in repetition stability and to micronize an electrode by a method wherein an organic insulating thin film is provided between a pair of electrodes, a second organic insulating layer is provided between, the electrodes and the thin film to limit a conductive area between the electrodes, and a memorizing property is given to the switching characteristic of an switching element. CONSTITUTION:After the surface of a glass board 1 is cleaned enough, a lower electrode 2 of Au is provided to the center of the surface providing Cr as an undercoat layer, a monomolecular accumulated layer is deposited on the surface of the board 1 including the lower electrode 2. Then, an electrode step protective layer 4 is formed thereon and the part of it corresponding to the electrode 2 is removed, and an upper electrode 5 is made to coat the whole face as being in contact with the monomolecular accumulated layer 3. In a switching element structured as above, when a voltage is applied between a lower and an upper electrode, a memorizing property is given to a current-voltage characteristic, whereby not only the switching element can be made stable in switching characteristic but also the electrodes can be made micronized and high in density.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は有機絶縁層を有するMlN素子に関する。また
、該上部及び下部電極をリングラフイー技術を用いて形
成したメモリー性を有するMIN構造スイッチング素子
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an MIN device having an organic insulating layer. The present invention also relates to a MIN structure switching element having memory properties, in which the upper and lower electrodes are formed using ring graphie technology.

[従来の技術] 最近有機分子の機能性を電子デバイスなどに応用しよう
とする分子エレクトロニクスに対する関心が高まってお
り、分子電子デバイスの構築技術の一つとみられるラン
グミュア−プロジェット膜(LB膜)についての研究が
活発化してきている。
[Prior art] Recently, interest in molecular electronics, which seeks to apply the functionality of organic molecules to electronic devices, has been increasing. Research is becoming more active.

LB膜は有機分子を規則正しく1分子層ずつ積層したも
ので、膜厚の制御は分子長の単位で行なうことができ、
−様で均質な超薄膜を形成できることからこれを絶縁膜
として使う多くの試みが行なわれてきた0例えば、(G
、 L、 Larkins et al↑bin 5o
lid films 99.1983)金属・絶縁体・
金属(1M)構造のトンネル接合素子[G、 L、 L
arkingetal著rエレクトロニックス・レター
ズ」(Electronics Letters)の「
シン・ソリッド゛フィルムズ」(↑hiXISolid
 Films)第88巻(1983年)]や金属・絶縁
体・半導体(NIS)構造の発光素子[G、 G、 R
oberts et al著「エレクトo = −7ク
ス・レターズJ (Elsctronjcs Lett
ers)第20巻、489頁(1984年)]あるいは
スイッチング素子[N、 J、↑homas et a
l著「エレクトロニクス・レターズJ (Electr
onics Letters)第20巻。
LB films are made by stacking organic molecules one molecular layer at a time, and the film thickness can be controlled in units of molecular length.
- Many attempts have been made to use this as an insulating film because it can form homogeneous ultra-thin films.
, L. Larkins et al↑bin 5o
lid films 99.1983) Metals/Insulators/
Tunnel junction device with metal (1M) structure [G, L, L
"Electronics Letters" by Arkingetal
Thin Solid Films” (↑hiXISolid
Films) Volume 88 (1983)] and metal-insulator-semiconductor (NIS) structure light emitting devices [G, G, R
Elsctronjcs Letts J by Oberts et al.
ers) Vol. 20, p. 489 (1984)] or switching elements [N, J, ↑Homas et a
``Electronics Letters J'' by Electr.
onics Letters) Volume 20.

83B頁(1984年)]がある。83B (1984)].

【発明が解決しようとする課題] 上記一連の研究によって素子特性の検討がされているが
未だ素子ごとの特性のバラツキ、経時変化など再現性と
安定性の欠如は未解決の問題として残っている。
[Problem to be solved by the invention] Although device characteristics have been investigated through the series of studies mentioned above, variations in characteristics between devices and lack of reproducibility and stability, such as changes over time, remain unresolved problems. .

また、従来、上記の如き検討に用いられた電極は、マス
ク蒸着により形成されてきた。そのマスク蒸着法により
電極を形成した場合、電極面積。
Furthermore, conventionally, the electrodes used in the above studies have been formed by mask vapor deposition. If the electrode is formed using the mask evaporation method, the electrode area.

形状は任意に選択できず限定されたものとなり、集積回
路の作成等において問題となっていた。他方電極面積形
状を任意に選択することが可能ならばその素子特性ある
いは素子の駆動法の向上が見込まれる。
The shape cannot be arbitrarily selected and is limited, which poses a problem in the production of integrated circuits. On the other hand, if the electrode area shape can be arbitrarily selected, it is expected that the device characteristics or the driving method of the device will be improved.

【課題を解決するための手段及び作用]上記問題点を解
決するため、本発明者等は鋭意研究の結果本発明を完成
した。すなわち、本発明は、一対の電極間に有機絶縁性
薄膜を有し、かつ、該電極の段差部分と有機絶縁性薄膜
の間に第2の有機絶縁性薄膜を設け、該電極間の通電領
域を制限し、スイッチング特性に対してメモリー性を有
することを特徴としたスイッチング素子及び係る素子の
作成方法である。
[Means and effects for solving the problems] In order to solve the above problems, the present inventors completed the present invention as a result of intensive research. That is, the present invention has an organic insulating thin film between a pair of electrodes, and a second organic insulating thin film is provided between the stepped portion of the electrode and the organic insulating thin film, and the current-carrying area between the electrodes is The present invention provides a switching element and a method for manufacturing such an element, which are characterized in that the switching characteristics are limited and the switching characteristics have a memory property.

以下、本発明の詳細な説明する。The present invention will be explained in detail below.

本発明の第1の有機絶縁層の形成に関しては、具体的に
は蒸着法やクラスターイオンビーム法等の適用も可能で
あるが、制御性、容易性そして再現性から公知の従来技
術の中ではLB法が極めて好適である。
Regarding the formation of the first organic insulating layer of the present invention, specifically, it is possible to apply a vapor deposition method, a cluster ion beam method, etc.; The LB method is highly preferred.

一般に有機材料のほとんどは絶縁性もしくは半絶縁性を
示すが、本発明に好適な耐熱性、耐溶剤性に優れた有機
材料は次の高分子化合物である。
Generally, most organic materials exhibit insulating or semi-insulating properties, but organic materials with excellent heat resistance and solvent resistance suitable for the present invention are the following polymer compounds.

例えばポリアミック酸、ポリアミック酸塩、ポリアミッ
ク酸エステルを環化して得られるポリイミドであり、一
般式(1)で表される繰り返し単位を有する重量平均分
子量2万〜300万のものを環化しイミド化したもので
ある。
For example, polyimides obtained by cyclizing polyamic acids, polyamic acid salts, and polyamic acid esters, which have a repeating unit represented by the general formula (1) and have a weight average molecular weight of 20,000 to 3 million, are cyclized and imidized. It is something.

一般式(1) 式中R1は少くとも6ケの炭素を含有する4価の基であ
り、具体例としては例えば などが挙げられる。
General formula (1) In the formula, R1 is a tetravalent group containing at least 6 carbon atoms, and specific examples include the following.

またR2は少くとも2ケの炭素を含有する2価の基であ
り具体例として例えば などが挙げられる。
Further, R2 is a divalent group containing at least two carbon atoms, and specific examples include the following.

またR3は少くとも6ケの炭素を有する1価の基である
か、あるいは少くとも6ケの炭素を有する4級アンモニ
ウム塩であり、一般式(2)で示された構造のものであ
る。
Further, R3 is a monovalent group having at least 6 carbon atoms, or a quaternary ammonium salt having at least 6 carbon atoms, and has the structure shown in general formula (2).

一般式(2) %式%) また、係る基板は、金属、ガラス、セラ′ミックス材料
等耐熱性、耐溶剤性に優れていれば、いずれでもよい。
General formula (2) % formula %) Further, the substrate may be any metal, glass, ceramic material, etc. as long as it has excellent heat resistance and solvent resistance.

次に本発明のスイッチング素子においては、素子の特性
を安定させるために、電極段差部分に第2の絶縁層とし
て、有機絶縁性保wII!lを設ける。係る第2の有機
絶縁性保護膜の形成に関しては、ネガ型有機レジスト材
料を用いることも可能であるが、分子内に重合部を有し
、さらに疎水性部位及び親木性部位を併有する分子を単
分子膜又は単分子累積膜に形成し、係る単分子累積膜上
に引き続き色素材料を単分子膜又は単分子累積膜に形成
し、従来公知の潜像形成方法(例えば、特公昭82−1
41538 )を用いて、所望の有機絶縁性保護膜を得
ることが可能である0分子内に重合部を有する両親媒性
分子としては、下記の如き一般式(1)、(2)、(3
)で示される分子が挙げられる。
Next, in the switching element of the present invention, in order to stabilize the characteristics of the element, a second insulating layer is formed on the electrode step portion to maintain organic insulation wII! Provide l. Regarding the formation of the second organic insulating protective film, it is possible to use a negative organic resist material, but it is also possible to use a negative-type organic resist material, but it is also possible to use a molecule that has a polymerization part in the molecule and also has a hydrophobic part and a lignophilic part. is formed into a monomolecular film or a monomolecular cumulative film, and subsequently a dye material is formed into a monomolecular film or a monomolecular cumulative film on the monomolecular cumulative film, using a conventional latent image forming method (for example, Japanese Patent Publication No. 1
As amphiphilic molecules having a polymerization moiety in the molecule, it is possible to obtain a desired organic insulating protective film using the following general formulas (1), (2), and (3).
) are listed.

R+−(−CH2←X−R2(1) 但し、X = COO,C0NH,000゜R1コCH
3−、CH2−CH−。
R+-(-CH2←X-R2(1) However, X = COO, C0NH, 000°R1coCH
3-, CH2-CH-.

R2xH,−CH−CH2,−CCCHs)mCH2−
−CH2Cl−CH2゜ 10≦n≦25 )1+CHz)−Qa+ C−Cs −(−CH2)−
X−R2(2)但し、x = coo、 coxu、 
oco。
R2xH, -CH-CH2, -CCCHs)mCH2-
-CH2Cl-CH2゜10≦n≦25 )1+CHz)-Qa+ C-Cs -(-CH2)-
X-R2 (2) However, x = coo, coxu,
oco.

R2=H,−CH閤CH2、−C(CH3)−(Ib 
R2=H, -CH閤CH2, -C(CH3)-(Ib
.

−GHz CH−CHt * 0≦m、n、10≦m+n≦25 p嘗 但し、 R+xH,CH3゜ 一5i(C1h)q(CiHs)r mxo 〜3 nxO〜10 q+r 冨 3 また、係る第2の有機絶縁膜の膜厚は500A〜l終履
であり好ましくは100OA〜3000Aである。
-GHz CH-CHt * 0≦m, n, 10≦m+n≦25 p However, R+xH, CH3゜-5i (C1h) q (CiHs) r mxo ~3 nxO~10 q+r The thickness of the organic insulating film is between 500A and 100A, preferably between 100A and 3000A.

一方、本発明のスイッチング素子において、電極はリソ
グラフィー技術を用いて形成する。係るリソグラフィー
技術は、リフトオフプロセス。
On the other hand, in the switching element of the present invention, the electrodes are formed using lithography technology. The lithography technique involved is a lift-off process.

フォトエツチングプロセスなど、従来公知の技術で充分
である。電極材料としては、高い伝導性を有するもので
あればよく5例えばAu、 Pt、 Ag。
Conventionally known techniques such as photoetching processes are sufficient. The electrode material may be any material that has high conductivity5, such as Au, Pt, and Ag.

Pd、 Aj?、 I!I、 Sn、 Pbなどの金属
や、これらの合金といった数多くの材料の適用が考えら
れる。また、電極の巾は10μ層〜Is■の範囲で形成
することができる0本発明において、リングラフィ技術
により微細な電極を形成するため、スイッチング速度を
高速にすることができる。
Pd, Aj? , I! Numerous materials such as metals such as I, Sn, and Pb, and alloys thereof can be considered. Further, the width of the electrode can be formed in the range of 10 μm to Is2. In the present invention, since the fine electrode is formed by phosphorography technology, the switching speed can be increased.

さらに、係るリソグラフィー技術は第2の有機絶縁層の
形成においても適用が可能である。
Furthermore, such lithography technique can also be applied to the formation of the second organic insulating layer.

[実施例] 以下実施例により詳細な説明を行なう。[Example] A detailed explanation will be given below using examples.

実施例1 以下に示す手順で第1図に示す構造を有する素子の作成
をおこなった。洗浄したガラス基板に前処理として酢酸
ブチルを用いて超音波処理、ベーキングを行なう、係る
基板にヘキサメチルジシラザン(HMDS)をスピンナ
ー塗布し、ベーキングを行なった後、ネガ型レジスト材
料(商標名RD−2000%−10)をスピンナー塗布
し、プリベークを行なう。
Example 1 A device having the structure shown in FIG. 1 was produced by the following procedure. The cleaned glass substrate is subjected to ultrasonic treatment and baking using butyl acetate as a pretreatment. Hexamethyldisilazane (HMDS) is applied to the substrate using a spinner, and after baking, a negative resist material (trade name RD) is applied. -2000%-10) was applied with a spinner and prebaked.

この時膜厚は0.7 gmになるようにした。続いて、
露光、現像、ポストベークを行ない、所望のレジストパ
ターンを作成した。
At this time, the film thickness was set to 0.7 gm. continue,
Exposure, development, and post-baking were performed to create a desired resist pattern.

係る基板上に下引層としてCrを真空蒸着法により、厚
さ100A堆積させ、更にAuを同法により堆積(膜厚
1100 A) した、係る基板をア七トン超音波処理
、ジメチルホルムアミド(DNF)超音波処理、純水洗
浄、ベーキングを行ない、リフトオフによる幅10鉢1
の下地電極を形成した。
On such a substrate, Cr was deposited as an undercoat layer to a thickness of 100 A using a vacuum evaporation method, and Au was further deposited using the same method (thickness: 1100 A).The substrate was subjected to a seven-ton ultrasonic treatment and dimethylformamide (DNF). ) Ultrasonic treatment, pure water cleaning, baking, and lift-off to create 10 width pots 1
A base electrode was formed.

係る基板をHMDSの飽和蒸気中に一昼夜放置して疎水
処理を行なった。係る基板上にLB法を用いてポリイミ
ド単分子膜の20層累積膜(膜厚80A)を形成し、絶
縁性とした。
The substrate was left in saturated HMDS vapor for a day and night to perform hydrophobic treatment. A 20-layer cumulative film (thickness: 80A) of a polyimide monolayer was formed on the substrate using the LB method to make it insulating.

以下ポリイミド単分子累積膜の作成方法の詳細を記す。The details of the method for producing the polyimide monomolecular cumulative film are described below.

(4)式に示すポリアミック酸をN 、N−ジメチルア
セトアミド溶媒に溶解させた(単量体換算濃度I X 
10−3M)後、別途調整したM、N−ジメチルオクタ
デシルアミンの周溶媒によるI X 10−3M溶液と
をl : 2 (V/V)に混合して(5)式に示すポ
リアミック酸オクタデシルアミン塩溶液を調製した。
The polyamic acid shown in formula (4) was dissolved in N,N-dimethylacetamide solvent (monomer equivalent concentration I
10-3M), then mixed with a separately prepared IX 10-3M solution of M,N-dimethyloctadecylamine in a surrounding solvent at a ratio of 1:2 (V/V) to obtain octadecylamine polyamic acid represented by formula (5). A salt solution was prepared.

(CH2) 17 CH3 係る溶液を水温20℃の純水から成る水相上に展開し、
水面上に単分子膜を形成した。溶媒除去後、表面圧を2
5mN/mに迄高めた0表面圧を一定に保ち乍ら、上述
下地電極付き基板を水面を横切る方向に速度55ash
/sinで静かに浸漬した後、続いて5鳳層/鳳inで
静かに引き上げて2暦のY型単分子累積膜を作成した。
(CH2) 17 CH3 The solution was developed on an aqueous phase consisting of pure water at a water temperature of 20°C,
A monomolecular film was formed on the water surface. After removing the solvent, reduce the surface pressure to 2
While keeping the zero surface pressure raised to 5 mN/m constant, the substrate with the base electrode was moved at a speed of 55 ash in the direction across the water surface.
After gently dipping in /sin, it was then gently pulled up in 5 layers/sin to create a Y-shaped monomolecular cumulative film of 2 layers.

係る操作を繰り返して20層のポリアミック酸オクタデ
シルアミン塩の単分子累積膜を形成した。
Such operations were repeated to form a 20-layer monomolecular cumulative film of polyamic acid octadecylamine salt.

次に係る基板を300℃で10分間の熱処理を行ない、
ポリアミック酸オクタデシルアミン塩をイミド化しく式
(8)) %式% イミド単分子累積膜を得た。
Next, heat treatment is performed on the substrate at 300°C for 10 minutes,
By imidizing polyamic acid octadecylamine salt, a monomolecular imide cumulative film was obtained.

係る基板上に(7)式に示されるジアセチレン化合物 C目H23−CII C−Car C−(CH2)8−
COOH(7)をLH法により累積した。
On such a substrate, a diacetylene compound represented by formula (7) H23-CII C-Car C-(CH2)8-
COOH (7) was accumulated by the LH method.

以下係るジアセチレン化合物の単分子累積膜の作成方法
を詳細に示す。
The method for producing a monomolecular cumulative film of a diacetylene compound will be described in detail below.

係るジアセチレン化合物をクロロホルムにlX10−3
Mの濃度で溶かした溶液を水温20℃、4×10−4 
M MnC1’zを含む水相(pH8,8)上に展開し
、水面上に単分子膜を形成した。溶媒蒸発除去後、表面
圧を20mN/mまで高めた0表面圧を一定に保ちなが
ら、上述下部電極付き基板を水面を横切る方向に速度1
0mm/sinで静かに浸漬し、続いて同じく速度10
−m/winで静かに引き上げ、2層のY型単分子累積
膜を作成した。係る操作を繰り返して50層のジアセチ
レン化合物の単分子累積膜を形成した。
The diacetylene compound was dissolved in chloroform at 1×10−3
A solution containing M at a concentration of 4 x 10-4 at a water temperature of 20°C
It was developed on an aqueous phase (pH 8,8) containing M MnC1'z to form a monomolecular film on the water surface. After the solvent was evaporated and removed, the substrate with the lower electrode was moved at a speed of 1 in the direction across the water surface while keeping the surface pressure constant and the surface pressure increased to 20 mN/m.
Gently immerse at 0 mm/sin, then at the same speed of 10
-m/win to create a two-layer Y-type monomolecular cumulative film. This operation was repeated to form a monomolecular cumulative film of 50 layers of a diacetylene compound.

続いて、スクアリリュムビスー〇−オクチルアズレン(
SOAZ)の単分子累積膜を係る基板上に形成する。以
下5OAZ単分子累積膜の作成方法を詳細に示す。
Next, squarylumbisu〇-octyl azulene (
A monomolecular cumulative film of SOAZ) is formed on the substrate. The method for producing the 5OAZ monomolecular cumulative film will be described in detail below.

5OAZを濃度lX10〜3Mで溶かしたクロロホルム
溶液を水温20℃の純水からなる水相上に展開し、水面
上に単分子膜を形成した。溶媒除去後、表面圧を20m
N/層まで高め、更にこれを一定に保ちながら、前記基
板を水面を横切る方向に速度5層m/wi!Iで静かに
浸漬したのち、続いて5層m/sinで静かに引き上げ
て2暦のY型単分子累積膜を作成した。
A chloroform solution in which 5OAZ was dissolved at a concentration of 1.times.10 to 3 M was spread on an aqueous phase consisting of pure water at a water temperature of 20.degree. C. to form a monomolecular film on the water surface. After removing the solvent, reduce the surface pressure to 20m
N/layer, and while keeping this constant, move the substrate across the water surface at a speed of 5 layers m/wi! After being gently immersed in I and then gently pulled up in 5 layers m/sin, a Y-type monomolecular cumulative film of 2 layers was created.

係る操作を繰り返して6層の5OAZ単分子累積膜を形
成した。
This operation was repeated to form a 6-layer 5OAZ monomolecular cumulative film.

係る基板上に830nmの波長の半導体レーザー(レー
ザービーム径1μ層、照射時間200ns/ 1ドツト
、出力3層V)を所望のマスクパターンを介して照射し
、潜像を形成した。
A latent image was formed on the substrate by irradiating a semiconductor laser with a wavelength of 830 nm (laser beam diameter 1 μ layer, irradiation time 200 ns/1 dot, output 3 layers V) through a desired mask pattern.

次に係る基板上に254n■の波長の紫外線を均一かつ
十分に照射し、係るジアセチレン化合物の所望のパター
ンを重合させる。係る基板をエタノール溶液に浸漬し、
半導体レーザーを照射した開口部及び5OAZ単分子累
積膜をはく離する。
Next, the substrate is uniformly and sufficiently irradiated with ultraviolet rays having a wavelength of 254 nm to polymerize the desired pattern of the diacetylene compound. Immersing such a substrate in an ethanol solution,
The opening irradiated with the semiconductor laser and the 5OAZ monomolecular cumulative film are peeled off.

係る基板上に真空蒸着法によってAi)を膜厚10GO
A堆積させる0次にポジ型レジスト材料(商標名OMR
−83)を膜厚1.2層讃となるようにスピンナー塗布
し、露光、潜像、ボストベークを行なう、その後、H3
PO4:HNO3:C1hCOOH:1hO= 18 
: 1 :2:lの溶液でAi)を所望のパターンにエ
ツチングする。係る基板をアセトン超音波処理、DMF
超音波処理、純水洗浄によりレジストをはく離し、ベー
キングを行なって上部電極を作成した。係る電極の巾は
lOO12した。
Ai) was deposited on the substrate with a thickness of 10GO by vacuum evaporation method.
0-order positive resist material (trade name: OMR) to be deposited
-83) with a spinner to a film thickness of 1.2 layers, perform exposure, latent image, and post bake, then H3
PO4:HNO3:C1hCOOH:1hO=18
: Etch Ai) into the desired pattern with a 1:2:l solution. Such a substrate was subjected to acetone ultrasonic treatment, DMF
The resist was removed by ultrasonication and washing with pure water, and baking was performed to create an upper electrode. The width of such an electrode was lOO12.

以上の様にして作成した試料の上下電極間に電圧を印加
した時の電流電圧特性(1−V特性)を測定した所、そ
の他の試料ではこれまで知られていないメモリー性のス
イッチング特性を観測した。
When we measured the current-voltage characteristics (1-V characteristics) when voltage was applied between the upper and lower electrodes of the sample prepared as described above, we observed memory switching characteristics that were previously unknown in other samples. did.

(第2図)さらに、第3図に示すような安定なON状!
s(抵抗値数十Ω)とOFF状S(抵抗値MΩ以上)を
つくることができ、ON→OFFへのスイッチングは一
定のシキイ値電圧(1〜2v程度/20層)を示し、O
FF→ONへのスイッチングは一2〜5v程度で起こり
、またスイッチング速度はpsecオーダーで0N10
FF比(ON状態とOFF状態の抵抗値の比)が5桁以
上であった。スイッチングのシキイ値電圧は絶縁層の暦
数が増すと高くなる傾向を示した。その結果、4層及び
6層試料ではスイッチング特性は不安定で、また300
層試料ではスイッチングが起こりにくなった。ここでエ
リジンメトリー法によるポリイミド単分子累積膜の1層
当りの膜厚は数Aであった。また、波高値±8V、交番
電界周波数2Hzの三角波を連続的に印加し続けた時1
発熱による電極破壊が起こるまでの繰り返し回数をもっ
て繰返し安定性の評価を行った処、繰返し回数は5 X
 100回であった。
(Fig. 2) Furthermore, the stable ON state as shown in Fig. 3!
S (resistance value of several tens of Ω) and OFF state S (resistance value of MΩ or more) can be created, and switching from ON to OFF shows a constant threshold voltage (about 1 to 2 V/20 layers), and O
Switching from FF to ON occurs at about -2 to 5V, and the switching speed is 0N10 in psec order.
The FF ratio (ratio of resistance values in ON state and OFF state) was 5 digits or more. The switching threshold voltage showed a tendency to increase as the number of insulating layers increased. As a result, the switching characteristics were unstable for the 4-layer and 6-layer samples, and
Switching no longer occurs in the layer sample. Here, the film thickness per layer of the polyimide monomolecular cumulative film measured by the erisinmetry method was several amps. In addition, when a triangular wave with a peak value of ±8 V and an alternating electric field frequency of 2 Hz is continuously applied, 1
The repetition stability was evaluated based on the number of repetitions until the electrode broke due to heat generation, and the number of repetitions was 5
It was 100 times.

実施例2 実施例1と同様にして、リフトオフプロセスにより下部
電極を形成し、更に、 LB法により20層のポリイミ
ド単分子累積膜を作成する。
Example 2 In the same manner as in Example 1, a lower electrode was formed by a lift-off process, and a 20-layer monomolecular polyimide cumulative film was further formed by the LB method.

係る基板上に実施例1と同様にフォトエツチングプロセ
スにより所望の上部電極を形成した。また、電極の巾は
20μ腸とした。
A desired upper electrode was formed on the substrate by the same photoetching process as in Example 1. Furthermore, the width of the electrode was 20 μm.

係る基板上に(8)式に示されるポリイソブチルメタク
リレート(PIBM)を CH3 ■ CH2 CH3−CI−C)13 LB法により累積した。
Polyisobutyl methacrylate (PIBM) represented by the formula (8) was accumulated on the substrate by the CH3 2 CH2 CH3-CI-C)13 LB method.

以下、PIBNの単分子累積膜の作成方法を詳細に示す
Hereinafter, a method for producing a monomolecular cumulative film of PIBN will be described in detail.

ベンゼン:n−ヘキサン=10:1の混合溶媒を用い、
PIBM(7) I X 10−3M (7)溶液を調
整した。これを、水温20℃の水相上に展開し、表面圧
を12腸N/層まで高め、水面上に単分子膜を形成した
0表面圧を一定に保ちながら、上述下部電極付き基板を
水面を横切る方向に速度10mm1層にnで静かに浸漬
し、続いて同じく速度10層腸/腸inで静かに引き上
げ2層のY型単分子累積膜を形成した。係る操作を繰り
返して、50層のPIBM単分子累積膜を形成した。続
いて、実施例1と同様に係る基板上に6層の5OAZ単
分子累積膜を形成し、さらに実施例1と同様に所望のパ
ターンを形成し、電極段差部分の保護膜とする。
Using a mixed solvent of benzene: n-hexane = 10:1,
A PIBM(7) IX 10-3M (7) solution was prepared. This was developed on a water phase with a water temperature of 20°C, the surface pressure was increased to 12 N/layer, and a monomolecular film was formed on the water surface.While maintaining a constant zero surface pressure, the substrate with the lower electrode was placed on the water surface. The membrane was gently immersed in one layer at a speed of 10 mm in the transverse direction, and then gently pulled up at the same speed of 10 layers intestine/intestine to form a two-layer Y-shaped monomolecular cumulative film. This operation was repeated to form a 50-layer PIBM monomolecular cumulative film. Subsequently, a six-layer 5OAZ monomolecular cumulative film is formed on the substrate in the same manner as in Example 1, and a desired pattern is further formed in the same manner as in Example 1 to serve as a protective film for the electrode step portion.

係る基板上にARを真空蒸着法により膜厚3000A堆
積させ、実施例1と同様にリソグラフィー技術を用いて
Alをパターニングし所望の上部電極の引き出し電極と
する。
On this substrate, AR is deposited to a thickness of 3000 Å by vacuum evaporation, and as in Example 1, the Al is patterned using lithography technology to form a desired lead-out electrode of the upper electrode.

以上の様にして作成した試料のI−V特性を実施例1と
同様に測定した処、実施例1と同様なメモリー性のスイ
ッチング特性を観測した。スイッチング速度はp8ec
オーダーであった。また、 0NlOFF比は5桁以上
あり繰り返し回数は4 X 107回であった。
When the IV characteristics of the sample prepared as described above were measured in the same manner as in Example 1, the same memory switching characteristics as in Example 1 were observed. Switching speed is p8ec
It was an order. Furthermore, the 0NlOFF ratio was more than 5 digits, and the number of repetitions was 4 x 107 times.

実施例3 実施例1と同様にして、リフトオフプロセスを用いて、
電極巾20μ層の下部電極を形成したのち。
Example 3 Similar to Example 1, using a lift-off process,
After forming a lower electrode layer with an electrode width of 20 μm.

LB法により20層のポリイミド単分子累積膜を作成す
る。
A 20-layer polyimide monomolecular cumulative film is created by the LB method.

係る基板上にネガ型レジスト材料(商標名0DOR−1
20)を膜厚100 A 、 20OA 、 500 
A 、 100OA 。
A negative resist material (trade name 0DOR-1) is applied on such a substrate.
20) Film thickness: 100A, 20OA, 500A
A, 100OA.

3000A、 5000A、 1終s、2ILmとなる
ようにそれぞれ、スピンナー塗布し、露光、現像、ポス
トベークを行ない、所望のパターンを得る。
Coating is performed using a spinner to obtain 3000A, 5000A, 1S, and 2ILm, respectively, and the desired pattern is obtained by performing exposure, development, and post-baking.

実施例1と同様にして、係る基板上にAlを膜厚100
0A堆積させる0次にポジ型レジスト材料(商標名^Z
 1370)をスピンナー塗布し、膜厚を1.2#Lm
とする。これを霧光、現像、ポストベークする。
In the same manner as in Example 1, a film of Al was deposited on the substrate to a thickness of 100 mm.
0-order positive resist material deposited at 0A (trade name ^Z
1370) with a spinner to a film thickness of 1.2 #Lm.
shall be. This is subjected to fog light, development, and post-bake.

その後H3P0*:HNO3:CH3GOOH:HzO
= 18: 1 : 2 : 1の溶液でARをエツチ
ングし所望のパターンを得る。係る基板にア七トン超音
波処理、DNF超音波処理、純水洗浄を行ないレジス)
 (A2137G)のはく離を行ない所望の上部電極を
作成した。係る電極の巾は20層層とした。
Then H3P0*:HNO3:CH3GOOH:HzO
Etch the AR with a solution of = 18:1:2:1 to obtain the desired pattern. The substrate was subjected to A7T ultrasonic treatment, DNF ultrasonic treatment, and purified water cleaning.
(A2137G) was peeled off to create a desired upper electrode. The width of the electrode was 20 layers.

以上の様にして作成した試料のI−V特性を実施例1と
同様に測定した処、実施例1と同様なメモリー性のスイ
ッチング特性を観測した。スイッチング速度はp!et
cオーダーであった。また、0N10FF比は5桁以上
あり、繰り返し回数は4 X 107回であった。
When the IV characteristics of the sample prepared as described above were measured in the same manner as in Example 1, the same memory switching characteristics as in Example 1 were observed. The switching speed is p! et
It was C order. Further, the 0N10FF ratio was over 5 digits, and the number of repetitions was 4 x 107 times.

電極段差部分の絶縁膜の膜厚が50OAより薄い場合、
絶縁膜の絶縁性は充分に確保できず、2終■になると上
部電極の段切れが起こり易かった。
If the thickness of the insulating film at the electrode step part is thinner than 50OA,
The insulating properties of the insulating film could not be sufficiently ensured, and the upper electrode was likely to break off at the end of 2.

比較例1 実施例1と同様にして、下地電極を形成し、20層のポ
リイミド単分子累積膜を形成する。
Comparative Example 1 A base electrode is formed in the same manner as in Example 1, and a 20-layer polyimide monomolecular cumulative film is formed.

係る基板上に5i02を真空蒸着法を用いて厚さ300
0A堆積した0次にポジ型レジスト材料(商標名^Z 
1370)をスピンナー塗布し、膜厚を1.2μlとす
る。これをプリベークしたのち、露光、現像。
5i02 was deposited on the substrate to a thickness of 300 mm using a vacuum evaporation method.
0A deposited zero-order positive resist material (trade name ^Z
1370) using a spinner to a film thickness of 1.2 μl. After pre-baking this, it was exposed and developed.

ポストベークを行う、その後HF: NH4F = l
 : 7の溶液でエツチングを行ない5i02をパター
ニングし、電極段差部分を保護する。係る基板をアセト
ン超音波島理、DNF超音波翅理、純水洗浄によりレジ
ストをはく離し、ベーキングを行なう。
Post-bake, then HF: NH4F = l
: Perform etching with the solution No. 7 to pattern 5i02 and protect the electrode step portion. The resist is removed from the substrate by acetone ultrasonic cleaning, DNF ultrasonic cleaning, and pure water cleaning, and then baking is performed.

係る基板上に実施例1と同様にして上部電極を作成する
。また電極の大きさは20終層口とした。
An upper electrode is formed on the substrate in the same manner as in Example 1. The size of the electrode was 20 mm.

係る試料のI−V特性を実施例1と同様に測定したとこ
ろ、実施例1と同様のメモリー性のスイッチング特性が
観測された。しかし上記実施例に比べ繰り返し安定性が
低く、2X107回であった。
When the IV characteristics of such a sample were measured in the same manner as in Example 1, memory switching characteristics similar to those in Example 1 were observed. However, the repetition stability was lower than in the above example, being 2×10 7 times.

比較例2 実施例1と同様にして素子を作成した。この時、電極巾
を150pmおよび11とした。係る電極巾は突来のマ
スク蒸着で形成されている大きさである。
Comparative Example 2 A device was produced in the same manner as in Example 1. At this time, the electrode widths were set to 150 pm and 11 pm. Such an electrode width is the size that is formed by conventional mask deposition.

係る素子の電流電圧特性を測定したところ、実施例1と
同様のメモリー−性を有したスイッチング特性が得られ
たが、スイッチング速度は各々30nsecおよび70
0nsecであった。
When the current-voltage characteristics of such an element were measured, switching characteristics with memory properties similar to those of Example 1 were obtained, but the switching speeds were 30 nsec and 70 nsec, respectively.
It was 0 nsec.

[発明の効果] 本発明は以下に記載する効果を有する。[Effect of the invention] The present invention has the effects described below.

■ LB膜を累積したのち、下部電極の段差部分を蒸着
ダメージのない有機絶縁膜によって保護することにより
、MIIII素子のスイッチング特性の繰り返し安定性
を向上させることができた。
(2) After the LB film was accumulated, the step portion of the lower electrode was protected with an organic insulating film that was not damaged by vapor deposition, thereby improving the repeat stability of the switching characteristics of the MIII device.

■ 耐熱性、耐溶剤性に優れた高分子化合物をLB法に
よって累積し、絶縁層としたMIN素子の電極形成方法
にリソグラフィー技術を用いることにより、電極の微細
化、高密度化が可能となった。
■ By using lithography technology to form the electrodes of MIN devices, which are made by accumulating polymer compounds with excellent heat resistance and solvent resistance using the LB method and using them as insulating layers, it is possible to miniaturize and increase the density of the electrodes. Ta.

■ 耐熱性、耐溶剤性に優れた高分子化合物をLB法に
よって累積し、絶縁層としたMIN素子の電極形成方法
に、リソグラフィー技術を用いて電極を微細にすること
により、スイッチング速度の高速化が可能となった。
■ The switching speed has been increased by making the electrodes finer using lithography technology in the electrode formation method for MIN devices, which is an insulating layer made by accumulating polymeric compounds with excellent heat resistance and solvent resistance using the LB method. became possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のMIM素子の具体例の構成概略図であ
る。また第2図と第3図は係る素子において得られた電
気的特性(1−V特性)を示す特性図で、第3図は係る
素子において確認されたON状態及びOFF状態の電気
的特性図を示すものである。 1:基板        2:下部電極3:単分子累積
膜(LB膜)
FIG. 1 is a schematic diagram of the configuration of a specific example of the MIM element of the present invention. In addition, Figs. 2 and 3 are characteristic diagrams showing the electrical characteristics (1-V characteristics) obtained in such an element, and Fig. 3 is an electrical characteristic diagram of ON state and OFF state confirmed in such an element. This shows that. 1: Substrate 2: Lower electrode 3: Monomolecular cumulative film (LB film)

Claims (8)

【特許請求の範囲】[Claims] (1)一対の電極間に有機絶縁性薄膜を有し、かつ、該
電極と該有機絶縁性薄膜の間に有機絶縁性保護膜からな
る第2の絶縁層を設け、該電極間の通電領域を制限し、
スイッチング特性に対してメモリー性を有することを特
徴としたスイッチング素子。
(1) An organic insulating thin film is provided between a pair of electrodes, and a second insulating layer made of an organic insulating protective film is provided between the electrodes and the organic insulating thin film, and a current-carrying area between the electrodes is provided. limit,
A switching element characterized by having memory properties in its switching characteristics.
(2)前記、一対の電極に挟持された有機絶縁性薄膜の
厚さが20Å以上1000Å以下である請求項1記載の
スイッチング素子。
(2) The switching element according to claim 1, wherein the thickness of the organic insulating thin film sandwiched between the pair of electrodes is 20 Å or more and 1000 Å or less.
(3)前記、一対の電極に挟持された有機絶縁性薄膜が
、ポリイミドより成る請求項1記載のスイッチング素子
(3) The switching element according to claim 1, wherein the organic insulating thin film sandwiched between the pair of electrodes is made of polyimide.
(4)請求項1記載のスイッチング素子の作成方法であ
って、リソグラフィー技術を用いて電極を微細化するこ
とを特徴とする素子作成方法。
(4) A method for manufacturing a switching element according to claim 1, characterized in that the electrodes are miniaturized using lithography technology.
(5)前記、有機絶縁性薄膜上に形成した、第2の有機
絶縁性保護膜をリソグラフィー法によりエッチングして
、前記通電領域を形成し、さらに上部電極を作成するこ
とを特徴とした請求項4記載の素子作成方法。
(5) The second organic insulating protective film formed on the organic insulating thin film is etched by a lithography method to form the current-carrying region and further to create an upper electrode. 4. The device manufacturing method described in 4.
(6)前記、有機絶縁性薄膜上に、上部電極を形成した
後、リソグラフィー法により該上部電極をエッチングし
て微細化し、さらに絶縁層で全面を被覆した後、該上部
電極とコンタクトするための開口部をエッチングして取
り出し電極を形成することを特徴とした請求項4記載の
素子作成方法。
(6) After forming the upper electrode on the organic insulating thin film, etching the upper electrode using a lithography method to make it finer and covering the entire surface with an insulating layer, forming a layer for contacting the upper electrode. 5. The device manufacturing method according to claim 4, wherein the opening is etched to form the extraction electrode.
(7)前記有機絶縁性保護膜が重合性両親媒性化合物と
、色素材料が積層された単分子累積膜に赤外線を照射し
て潜像を形成する工程と潜像が形成された層に紫外線を
照射して該潜像を顕像化する工程により形成されること
を特徴とする請求項4記載の素子作成方法。
(7) A process in which the organic insulating protective film forms a latent image by irradiating infrared rays on a monomolecular cumulative film in which a polymerizable amphiphilic compound and a dye material are laminated; 5. The method for producing an element according to claim 4, wherein the latent image is formed by irradiating the latent image with a visible light.
(8)前記有機絶縁性保護膜がネガ型有機レジスト材料
により形成されることを特徴とする請求項4記載の素子
作成方法。
(8) The device manufacturing method according to claim 4, wherein the organic insulating protective film is formed of a negative type organic resist material.
JP1035113A 1989-02-16 1989-02-16 Switching element and manufacture thereof Pending JPH02215173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1035113A JPH02215173A (en) 1989-02-16 1989-02-16 Switching element and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02215173A true JPH02215173A (en) 1990-08-28

Family

ID=12432878

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326936B1 (en) 1997-07-22 2001-12-04 Thin Film Electronics Asa Electrode means, comprising polymer materials, with or without functional elements and an electrode device formed of said means
WO2002078056A3 (en) * 2001-03-22 2003-02-13 Hewlett Packard Co Passivation layer for molecular electronic device fabrication
JP2005521237A (en) * 2001-06-28 2005-07-14 ヒューレット・パッカード・カンパニー Production of molecular electronic circuits by imprinting

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326936B1 (en) 1997-07-22 2001-12-04 Thin Film Electronics Asa Electrode means, comprising polymer materials, with or without functional elements and an electrode device formed of said means
WO2002078056A3 (en) * 2001-03-22 2003-02-13 Hewlett Packard Co Passivation layer for molecular electronic device fabrication
US6835575B2 (en) 2001-03-22 2004-12-28 Hewlett-Packard Development Company, L.P. Passivation layer for molecular electronic device fabrication
JP2005521237A (en) * 2001-06-28 2005-07-14 ヒューレット・パッカード・カンパニー Production of molecular electronic circuits by imprinting

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