JPH0221379A - Space filter device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of a space filter device by reading the 3 rows X 3 columns picture data successively out of a picture memory for each row or column. CONSTITUTION:A picture memory 1 has the capacity larger than the capacity of the picture element value to be processed by at least one line. Then the picture element value written previously via the area of the 2nd line is read out of the memory 1, and the picture element value processed by a digital filter 2 is written into the memory 1 via the area of the 1st line. At the same time, the 3 rows X 3 columns picture element value is read out of the memory 1. Therefore the filter 2 can take the picture element value as well as the vertical and horizontal picture element values out of the delay circuits 3-6 set at 6 stages and can process these picture element values. Thus the circuit constitution is simplified for a space filter device.

Description

[Detailed description of the invention] The present invention relates to a spatial filter device used for such applications.

BACKGROUND ART FIG. 4 shows a schematic configuration of a conventional spatial filter device,
5 shows a detailed configuration of the digital filter 17 in FIG. 4, and FIGS. 6(a) and 6(b) show the image memory 16 and 18 in FIG. 4 whose addresses are expressed by a two-dimensional matrix, respectively. Indicates memory contents.

In FIG. 4, 16 is an image memory for storing unprocessed image data, 17 is a digital filter that improves the spatial distribution of light intensity of the image data stored in the image memo IJ 16, and 18 is a digital filter. This is an image memory for storing image data processed by 17.

In FIG. 5, 19 is an n-stage delay circuit (nD) that delays the signal read out from the image memory 16, and 20 is
A one-stage delay circuit (I
D), 21 is a one-stage delay circuit (ID) that delays the signal from the delay circuit 20, and 22 is an n-stage delay circuit (nD) that delays the signal from the delay circuit 21.

23 is a multiplication circuit (xa) that multiplies the signal read from the image memo IJ 16 by a coefficient a; 24 is a delay circuit 19
a multiplication circuit (Xa), 25, which multiplies the signal from the coefficient a by a coefficient a;
is a multiplication circuit (X(1-48)) that multiplies the signal from the delay circuit 20 by the coefficient (1-4a), and 26 is the delay circuit 2
A multiplication circuit (Xa) that multiplies the signal from 1 by a coefficient a, 2
7 is a multiplication circuit (X a) that multiplies the signal from the delay circuit 22 by a coefficient a.

28 is an adder circuit that adds the signals from the multiplier circuits 23 and 24; 29 is an adder circuit that adds the signals from the multiplier circuits 25 and 28;
An addition circuit 30 adds signals from the multiplication circuit 26
An adder circuit 31 adds the signal from the multiplier circuit 27 and the signal from the adder circuit 30 .

In FIG. 6, the image memories 16 and 18 are respectively (
It has an area of n+2)
Let the processed pixel value stored in YII be YII.

Next, the operation of the above conventional example will be explained.

In FIG. 4, the pixel values stored in the image memory are at addresses (0,0) to (0,n), (1,O) to (1,n
), (2, O) ~ (21n), ... (i, o) ~
It is read out row by row in the order of (i, n) and input to the delay circuit 19 and multiplication circuit 23 of the digital filter 17.

Here, for example, when the pixel value yo +I)I is input to the digital filter 17, the delay circuits 19, 20, 21
．． 22 are the pixel values yI(''+1), yll, y, respectively.
Outputs I(1-1), 3'(1-1)I.

Therefore, each multiplier 23 to 27
The respective coefficients are multiplied by the adders 28 to 28.
31, the adder 31 calculates the pixel value Y11 Yu = a Y<1++ )l + a'! ＋ ＜
r++ >+ (1-48) YII +ayI(I-1)+ay(I-I)I is output, and this pixel value Y11 is the address (i, j
).

Therefore, as shown in FIG. 5(b), the pixel value yIJ
is converted into a pixel value Y++ using the upper, lower, left, and right pixel values.

Problems to be Solved by the Invention However, in the above-mentioned conventional spatial filter device, the image data stored in the image memory 16 is sequentially read out row by row to extract the relevant pixel value and the pixel values on the top, bottom, left, and right sides. Corresponding to the number of areas n+2, the digital filter 17 has 2n+2 stages of delay circuits 19-
22, and therefore the circuit configuration becomes complicated.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a spatial filter device with a simple circuit configuration.

Means for Solving the Problems In order to achieve the above object, the present invention sequentially reads out 3 rows x 3 columns of image data stored in an image memory row by row or column by column. .

Effect of the Invention With the above configuration, the present invention can obtain the image data and the upper, lower, left, and right image data using 3 rows x 3 columns of image data using a total of 6 stages of delay circuits, which simplifies the circuit configuration compared to the conventional example. It can be done.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram showing one embodiment of the spatial filter device according to the present invention, FIG. 2 is a block diagram showing the digital filter of FIG. 1, and FIGS. FIG. 2 is an explanatory diagram showing the stored contents of the image memory shown in FIG. 1;

In FIG. 1, reference numeral 1 denotes an image memory having a storage area of (n+2)×(m+3), that is, the image memory 1 has a capacity larger by one line than the conventional image memory 18.

As shown in FIG. 3(a), this image memory 1 contains i
Pixel value y (1-1) at address (i, j) in row j column
I is stored, and compared to the conventional example, each pixel value is stored in the storage area of the next row, and the addresses (0, 0) to (
0, n+1), no pixel value is stored.

1a generates an address for sequentially reading out the pixel values of 3 rows x 3 columns of pixel values stored in the image memory 1 column by column, and also reads out the pixel values processed by the digital filter 2 at 1a of the image memory 1. This is an address generator that generates addresses to be written sequentially starting from the line.

In the digital filter 2 shown in FIG. 2, 3 delays the signal read out from the image memory 1.

4 is a one-stage delay circuit (ID) that delays the signal from delay circuit 3; 5 is a one-stage delay circuit (ID) that delays the signal from delay circuit 4; ), 6
is a two-stage delay circuit (
2D).

7 is a multiplication circuit (xa) that multiplies the signal read from the image memory 1 by a coefficient a; 8 is a multiplication circuit (Xa) that multiplies the signal from the delay circuit 3 by a coefficient a; 9 is a delay circuit Multiplying circuit C that multiplies the signal from 4 by the coefficient (1-4a)
X (1-48)), 10 is a multiplication circuit (Xa) that multiplies the signal from the delay circuit 5 by a coefficient a, and 11 is a multiplication circuit (Xa) that multiplies the signal from the delay circuit 6 by a coefficient a. be.

12 is an adder circuit that adds the signals from multiplier circuits 7 and 8; 13 is an adder circuit that adds the signal from multiplier circuit 9 and the signal from adder circuit 12; 14 is an adder circuit that adds the signal from multiplier circuit 10; Addition circuit 1 for adding signals from circuit 13
5 is an adder circuit that adds the signal from the multiplier circuit 11 and the signal from the adder circuit 14.

Next, the operation of the above embodiment will be explained.

In FIG. 1, an address generator 1a generates an address (1
,0)~(3,0), (1,1)~(3゜1),
(1,2) to (3,2) are generated sequentially, and similarly, addresses (i LJ 1)l (iIJ-1), (
i+1. j-1), (i-1, j)+ (i.

j), (i+1.j)+ (it,j+1),
(i.

j+1), (i+1.j+1) is generated.

Here, for example, when the pixel value yI(I+1) is input to the digital filter 2, the delay circuits 3 to 6 respectively input the pixel value y(I+l)j, yII, yB+-+)
Output.

Therefore, these input pixel values are multiplied by the respective coefficients by the multipliers 7 to 11, and the adders 12 to 1
5, the adder 15 calculates the pixel value Y+ + YIr = a YI <+ + 10a 'lo + similar to the conventional example.
I) 1+ (1-48) YIr + a Y (1-1) I+a YI<+ -1+ is output, and this pixel value Y++ is the address of image memory 1 (l
, j).

Therefore, as shown in FIG. 3(b), the pixel value V++
is converted into a pixel value Y1 using the upper, lower, left, and right pixel values.

That is, in the above embodiment, since no pixel values are written in the first row of the image memory 1 before processing, pixel values in the first row after processing can be written. Note that no pixel values are written to the last row of the image memory 1 after processing.

Therefore, according to the above embodiment, the image memory 1 has a capacity that is at least one line larger than the capacity of the pixel values to be processed, and the pixel values written in advance from the second line area are read out. Since the pixel values processed by the digital filter 2 are written from the first line area,
Unlike the conventional example, two image memories are not required.

Also, since the pixel values of 3 rows x 3 columns of pixel values stored in the image memory 1 are read out, the digital filter 2 uses six stages of delay circuits 3 to 6 to synchronize the pixel values and the upper, lower, left, and right pixel values. It can be taken out and processed.

Note that the address generator 1a was configured to generate addresses so as to sequentially read out the pixel values of 3 rows x 3 columns of pixel values stored in the image memory 1 column by column, but instead The configuration may be such that an address for reading is generated, and either the row start or column order for reading may be used.

As described in detail, in the present invention, image data of 3 rows x 3 columns of image data stored in an image memory is read out sequentially row by row or column by column. image data can be obtained using a total of six stages of delay circuits, so the circuit configuration can be simplified compared to the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing one embodiment of the spatial filter device according to the present invention, FIG. 2 is a block diagram showing the digital filter of FIG. 1, and FIGS. 1
4 is a schematic block diagram showing a conventional spatial filter device. FIG. 5 is a block diagram showing the digital filter of FIG. 4.
Figures (a) and (b) are explanatory diagrams showing the stored contents of the image memory in Figure 4. DESCRIPTION OF SYMBOLS 1... Image memory, 1a... Address generator (reading means), 2... Digital filter, 3-6...
・Delay circuit, 7 to 11...Multiplication circuit, 12 to 15...
・Addition circuit. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (2)

[Claims] (1) Means for sequentially reading 3 rows x 3 columns of image data stored in an image memory row by row or column by column, and converting the image data sequentially read by the reading means into upper, lower, left, and right image data. A spatial filter device having a digital filter for processing. (2) The image memory has a capacity that is at least one line larger than the capacity of the image data to be processed, and the image data written in advance from the second line area is read out by the reading means and the digital filter 2. The spatial filter device according to claim 1, wherein the image data processed by is written from the first line area.