JP3316266B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for obtaining a moment of inertia used for extracting features such as an area, a center of gravity, and a principal axis angle of an object photographed by an image pickup apparatus such as a video camera. It is about.

[0002]

2. Description of the Related Art Conventionally, in assembling or inspecting a factory, an object is photographed with a video camera, and features such as an area, a center of gravity, and a principal axis angle of the object are extracted based on the taken image. Has been done. In order to extract these features, the 0th moment, the 1st moment,
Next moment and synergistic moment need to be determined.

[0003] An image is arranged in a two-dimensional array, and a coordinate axis is defined as a horizontal x-axis and a vertical direction as a y-axis.
Is the image intensity of I (x, y), the zero-order moment M
_00, the primary moment M _10, M _01, 2-order moment M _20,
M ₀₂ and the synergistic moment M ₁₁ are represented by the following equations.

[0004]

M ₀₀ = Σ _{x, y} I (x, y) M ₁₀ = Σ _{x, y} x · I (x, y) M ₀₁ = Σ _{x, y} y · I (x, y) M ₂₀ = Σ _{x, y} x ² 2I (x, y) M ₀₂ = Σ _{x, y} y ²・ I (x, y) M ₁₁ = Σ _{x, y} x ・ y ・ I (x, y)

[0005] From these total six moments, a weighted area Area, the coordinates of the center of gravity (G _x, G _y ), and the principal axis angle α are determined by the following equations in consideration of the gray scale. However, the number of gradations of the image is W.

[0006]

[Number 2] _{Area = M 00 / W G x} = M 10 / Area G y = M 01 / Area tan2α = 2I xy / (I y -I x) I x = {M 20 / (Area · W)} - _{G x I y = {M 02} / (Area · W)} - G y I xy = 2 _{[{M 11 / (Area · W} )} - G x G y ]

When the above-mentioned six moment calculations are performed by a general-purpose microprocessor, it takes an enormous amount of processing time. Therefore, in order to shorten the processing time, a chip dedicated to moment calculation (Moment Generator Chip) has been developed (see "A Robot Ping-Pong Player", Russel L. Ande
rson, MIT Press 1988. See pages 42-48).

[0008]

However, in the apparatus using the above-mentioned dedicated chip for moment calculation, since the above-mentioned six moments are calculated by separate chips, a total of six dedicated chips are required. There is a problem that the cost is high and the scale of the apparatus is large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus capable of shortening the processing time for calculating a moment without increasing the size and cost of the apparatus.

[0010]

An image processing apparatus according to the present invention has an image memory for two-dimensionally storing image data of an object, a first arithmetic unit having an accumulative product-sum operation function, and a first operation unit having an accumulative addition function. An arithmetic circuit comprising two arithmetic units and a third arithmetic unit having a cumulative addition function in the sub-scanning direction of the image memory;
By reading out image data from a result memory for storing the operation result of the operation circuit and the image memory and inputting the image data to the operation circuit, the first operation unit outputs an image density of each pixel included in the line for each line in the main scanning direction. And the sum of the product of the product and the corresponding line number in the sub-scanning direction is calculated. The second calculator calculates the sum of the image densities of all the pixels included in the line for each line in the main scanning direction. A first transfer mode execution means for causing a calculator to calculate the sum of image densities of all pixels included in each line in the sub-scanning direction and storing the calculation results in a result memory;
The operation result of the second operation unit or the third operation unit obtained by the transfer mode execution means is read from the result memory and input to the operation circuit, whereby one of the two first moments is calculated by the first operation unit. The second operation unit calculates the zero-order moment, and stores the operation results in a result memory. The second transfer mode execution unit and the first operation unit obtained by the first transfer mode execution unit calculate the result. By reading the data from the memory and inputting it to the arithmetic circuit, the first arithmetic unit calculates the synergistic moment, the second arithmetic unit calculates the other of the two primary moments, and stores the calculation results in the result memory. A third transfer mode executing means for calculating two second moments based on data stored in the result memory. Characterized in that it comprises a.

The first arithmetic unit includes, for example, a multiplier and a first adder. Each time data is input to the arithmetic circuit, the count value is incremented by one, and image data for one main scan is stored in the image memory. A device that accumulates the result of integrating the output of the counter that is reset each time the data is input to the arithmetic circuit and the data input to the arithmetic circuit is used.

As the second arithmetic unit, for example, one provided with a second adder and cumulatively adding data inputted to the arithmetic circuit is used.

The third arithmetic unit includes, for example, a third adder and a line memory that holds the output of the third adder for one or more scans in the main scanning direction of the image memory. The one that accumulatively adds the image data from the memory and the previous addition result of the line in the sub-scanning direction corresponding to the input image data and held in the line memory is used.

[0014]

First, image data is read from the image memory and input to the arithmetic circuit. Thus, the P ₁₀ and 7 in the sub-scanning direction of the product sum of the line number (Fig. 6 and the corresponding image density of each pixel included in the line to each line in the main scanning direction by the first computing unit P ₀₁ ) is calculated.
Further, the second computing unit calculates, for each line in the main scanning direction, the sum of image densities of all pixels included in the line (P in FIG. 6).
(Y) or P (x) in FIG. 7 is calculated. Further, the sum of the image densities of all the pixels included in the line (P (x) in FIG. 6 or P (y) in FIG. 7) is calculated for each line in the sub-scanning direction by the third calculator. These operation results are stored in the result memory.

The operation result (P (y) or P (x)) of the second operation unit or the third operation unit obtained by the first transfer mode execution means is read from the result memory and input to the operation circuit. . Accordingly, one of the two first moments (M ₀₁ or M ₁₀ ) is calculated by the first calculator. Further, the 0th order moment (M ₀₀ ) is obtained by the second computing unit.
Is calculated. These operation results are stored in the result memory.

[0016] The first computing unit of the operation results obtained by the first transfer mode executing means (P ₁₀ or P ₀₁₎ is input to the in arithmetic circuits read from the result memory. As a result, the synergistic moment (M ₁₁ ) is calculated by the first calculator. The other (M ₁₀ or M ₀₁₎ is computed of the two first-order moment by the second computing unit. These operation results are stored in the result memory.

In this manner, two second moments (M ₂₀ and M ₀₂ ) are calculated based on the data stored in the result memory. In this manner, the six moments M ₀₀ , M ₁₀ , M ₀₁ , M ₁₁ , M ₂₀ , and M ₀₂ , which are the basis of the calculation of the feature amount of the object, such as the area, the center of gravity, and the main shaft angle.
Is obtained.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an image processing device for extracting image features used in a high-speed positioning device or a robot vision.

In FIG. 1, the image processing apparatus includes a general-purpose CPU (central processing unit) 1 for controlling the entire system. The image memory 2 stores data of an image captured by the video camera 5. Image calculation unit 3
Performs various operations for moment calculation, and is a characteristic part of the present invention. Video input / output unit 4
A / D converts analog data from the video camera 5 and takes it into the image memory 2, or reads out the contents of the image memory 2, performs D / A conversion, and outputs it to the monitor 6.

Access to the image memory 2 from the CPU 1 and communication of commands between the devices are basically performed via the general-purpose bus 7. An image-only bus 8 is provided for communicating a large amount of image data at high speed.

Each of the image memories 2 is provided with an image memory control unit (not shown) for controlling the input and output of data to and from the image memory 2, and the image data is input to and output from the image dedicated bus 8 at high speed. It is supposed to be.

FIG. 3 shows a transfer control signal and image data when image data is transferred from the image memory using the image dedicated bus 8.

The clock GCLK is a clock for transferring image data using the dedicated image bus 8, and transfers image data DATA in synchronization with GCLK. The in-transfer signal * BUSY is a signal indicating that the image data is being transferred, and has an active level "L" during the image data transfer. The horizontal synchronizing signal * HS is a signal indicating the head of each horizontal line in the image memory 2, and becomes active level "L" at the head of each horizontal line. The signal * VLD during the valid period is a signal indicating the valid period of the data, and is at the active level "L" during the valid period of the data.

The last line transfer signal * LV is a signal indicating that the image data of the last line of the image memory 2 is being transferred, and has an active level during the transfer period of the image data of the last line of the image memory 2. It becomes "L". The signal LINE2 is a signal indicating transfer of the second and subsequent lines of the image memory 2.

These transfer control signals * BUSY, * H
S, * VLD, * LV, and LINE2 are output from the image memory control unit of the image memory 2 when the image data is transferred via the image dedicated bus 8.

FIG. 2 shows the configuration of the image calculation unit of FIG.

The pre-processing unit 11 stores image data (DATA) sent from the image memory 2 via the image dedicated bus 8.
, Pre-processing such as filter processing and LUT (look-up table) processing. The I / O register 15 stores C
According to the setting of PU1, the signal MODE indicating the transfer type and the transfer start signal * STAR indicating the start of the transfer of the image data.
Output T. The selector 12 switches and outputs the output (the image data from the image memory 2) of the preprocessing unit 11 and the data from the result memory 17 based on the signal MODE.

The output of the selector 12 is supplied to the first computing unit 20,
The signals are sent to the second computing unit 30 and the third computing unit 40, respectively.

First arithmetic unit (ALU1: product-sum arithmetic unit) 20
Are, in this embodiment, P ₁₀ (y), M ₀₁ and M
_It performs ₁₁ operations, and is composed of a multiplier 21 and an adder 22. The multiplier 21 multiplies the output of the selector 12 (the image data from the image memory 2 or the image data from the result memory 17) by the output value of the counter 13. The counter 13 counts up in synchronization with the clock GCLK, and is reset when the horizontal synchronization signal * HS becomes L level. Adder 22
Performs addition of the output of the multiplier 5 and the data to which the output of the adder 6 is fed back. The first computing unit 20 is reset when the horizontal synchronization signal * HS becomes L level.

Second arithmetic unit (ALU2: accumulator) 30
, In this example, P in FIG. 6 (y), M ₀₀ and M ₁₀
And an adder 31 and a latch circuit 32
It is composed of In the adder 31, the selector 12
(Image data from the image memory 2 or image data from the result memory 17) and data fed back from the output of the adder 31 are cumulatively added. The output of the adder 31 is delayed by one clock by the latch circuit 32. The second computing unit 30 is reset when the horizontal synchronization signal * HS becomes L level.

Third arithmetic unit (ALU3: cumulative adder) 40
Performs the operation of P (x) in FIG. 6 in this embodiment. The adder 41, the line memory 42, and the latch circuit 4
And 3. The line memory 42 is a memory element capable of delaying the number of horizontal pixels of the image memory 2 or more, and receives the output data of the adder 41 as an input. Output data of the line memory 42 is latched by the latch circuit 43 and output in synchronization with the clock GCLK. Adder 4
At 1, the cumulative addition of the output of the selector 12 (the image data from the image memory 2 or the image data from the result memory 17) and the output data of the latch circuit 43 is performed. The third arithmetic unit (ALU2: cumulative adder) 40 is capable of cumulative addition in the vertical direction of the image memory, and has a transfer start signal * S
It is reset when TART goes low.

In the result memory 17, as shown in FIG.
The calculation results of the calculators 20, 30, and 40 shown in FIG. 6, that is, P ₁₀ (y), P
(Y), P (x) , 0 -order moment M _00, 1-order moment M _10, M _01, region E1 for storing a synergistic moment M ₁₁
To E7 are provided. Then, each operation result is stored in the corresponding area of the result memory 17. When the operation results are stored in the result memory 17 from each of the computing units 20, 30, and 40, the address of the area corresponding to each operation result is output from the result memory control unit 16. Result memory 17
When the image data is transferred from the memory controller 16 to the selector 12, the address of the image data to be read
Output from Further, for the result memory 17, C
PU1 is accessible via general-purpose bus 7.

When image data is transferred from the result memory 17 to the selector 12, transfer control signals * BUSY, * VLD, * HS, etc. are output from the result memory control unit 16,
The data transfer of the result memory 17 is controlled.

The ALU control unit 14 is based on the transfer control signals * LINE2, * LV output from the image memory control unit, the transfer control signal * HS output from the image memory control unit or the result memory control unit 16, and the like. Signals * OE1, * OE2, * OE3 for controlling the timing of outputting data from the three computing units 20, 30, 40 are output. The signal * OE1 is a signal for controlling the output timing of the first computing unit 20, and the signal * OE2 is a signal for controlling the output timing of the second computing unit 30.
Is a signal for controlling the output timing of the signal * OE3.
Is a signal for controlling the output timing of the third computing unit 40.

In the above configuration, the calculation of each moment is performed as follows. That is, first, the image data from the image memory 2 is transferred to the image calculation unit 3 via the image data dedicated bus 8 (first transfer). In the first computing unit 20 of the image computing unit 3, based on the transmitted image data, as shown in FIG. 7, P ₁₀ (y) = Σ _x
The calculation of x · I (x, y) is performed, and the calculation result is stored in the area E1 of the result memory 17. The second computing unit 30
In, on the basis of the image data transmitted, as shown in FIG. 8, the calculation of _{P (y) = Σ x I} (x, y) is performed,
The operation result is stored in the area E2 of the result memory 17. Further, in the third computing unit 40, based on the transmitted image data, as shown in FIG. 9, P (x) = Σ _y I (x,
The calculation of y) is performed, and the calculation result is stored in the area E3 of the result memory 17. In other words, in the first transfer, the arithmetic units 20, 30, and 40 perform the arithmetic shown in column A of FIG.

Next, the data P (y) stored in the area E2 among the operation results stored in the result memory 17 are sequentially read out and sent to the selector 12 (second transfer). In the first computing unit 20, the transmitted data P
Based on (y), the following equation gives the first moment M ₀₁
Is performed, and the calculation result is stored in the area E4 of the result memory 17.

[0038]

[Equation 3] M ₀₁ = Σ _y y · P (y)

[0039] The second operation unit 30, based on data sent P (y), by the following equation, 0-order calculation moment M ₀₀ is performed, the calculation result is the result memory 1
7 is stored in the area E5. That is, in the second transfer, the arithmetic units 20 and 30 perform the arithmetic shown in the column B of FIG.

[0040]

M ₀₀ = ４ _y P (y)

Next, the data P ₁₀ (y) stored in the area E 1 among the calculation results stored in the result memory 17 are sequentially read and sent to the selector 12 (third transfer). In the first computing unit 20, the transmitted data P ₁₀
Based on (y), the following equation gives the synergistic moment M ₁₁
Is performed, and the calculation result is stored in the area E6 of the result memory 17.

[0042]

[Number 5] _{M 11 = Σ y y · P} 10 (y)

[0043] The second operation unit 30, based on the sent coming data P ₁₀ (y), by the following equation, calculation of the first moment M ₁₀ is performed, the calculation result is a result of the memory 17 It is stored in area E7. That is, in the third transfer, the arithmetic units 20 and 30 perform the arithmetic shown in the column C of FIG.

[0044]

## EQU6 ## M ₁₀ = Σ _y P ₁₀ (y)

As described above, by the three transfers, P
_{10 (y), P (y} ), P (x), M 00, M 10, M 01, M
When ₁₁ is stored in the result sought memory 17, as follows, by CPU 1, the second moment M _20, M _02, shown in column D of FIG. 6 it is determined. That is, the second moment M ₂₀ is calculated by the calculation result P (x) obtained in the first transfer.
Is obtained by the following equation based on

[0046]

## EQU7 ## M ₂₀ = Σ _x x ² · P (x)

The second moment M ₀₂ is obtained by the following equation based on the operation result P (y) obtained in the first transfer.

[0048]

[Equation 8] M ₀₂ = Σ _y y ² · P (y)

Thereafter, from the three transfers and the respective moments calculated by the CPU 1, the CPU 1 extracts the features of the area, the center of gravity, and the principal axis angle of the object using the above formula (2). In the second transfer, P (x) stored in the result memory 17 is calculated by
It is also possible to calculate M ₀₁ and M ₀₀ by inputting them to 30. Further, the transfer order of the second transfer and the third transfer may be interchanged.

FIG. 4 shows the signals of the respective sections of the image calculation section at the time of the first transfer. Here, for convenience of explanation, it is assumed that image data having a size of 6 rows × 6 digits is transmitted from the image memory 2.

Transfer start signal * indicating start of transfer of image data from image memory 2 by setting of I / O register 15
START is output, and thereafter, the transfer control signals * BUSY, * HS, * VLD are output from the image memory control unit.

The third computing unit 40 is reset at the falling timing of the transfer start signal * START. Also,
At the falling timing of the horizontal synchronization signal * HS, the counter 13, the first computing unit 20, and the second computing unit 30 are reset.

At the time of the first transfer, the signal MOD
E is a signal for selecting image data from the image memory 2. Therefore, the data DATA output from the selector 12 is the image data from the image memory 2. The image data output from the selector 12 is sent to each of the arithmetic units 20, 30, and 40 in synchronization with the clock GCLK while the signal * VLD is at the L level during the valid period. Counter 1
3, the signal * VLD is L during the valid period.
During the level period, the signal is sent to the first computing unit 20 in synchronization with the clock GCLK.

The line memory 42 of the third computing unit 40 outputs 0 for the first line, and outputs the output of the adder 41 for the data of the previous line held in the line memory 42 from the second line. The data is output in synchronization with the clock GCLK via the latch circuit 43. The output signal of the latch circuit 43 is represented as FDATA.

[0055] The first operation unit 20, sent to the cumulative sum of products between the image data DATA and CUNT have (Σ _{x x} · I
(X, y)) is performed, and when the signal * OE1 becomes L level, an operation result is output. In the second computing unit 30, the cumulative addition (Σ _x I (x,
y)) is performed, and when the signal * OE2 becomes L level, an operation result is output. In the third arithmetic unit 20, it sent cumulative addition of the image data DATA and the data FDATA has _{(Σ y I (x, y} )) is performed, and the signal * OE3 arithmetic operation result is output becomes L level.

The signal * OE1 indicates that the horizontal synchronization signal * HS is low.
When the signal * HS1 delayed by one clock with respect to the horizontal synchronizing signal * HS is at the H level and the signal LINE2 is at the H level, the signal becomes the active level "L" for a predetermined period.
That is, each time the data transfer to each line is completed, the active level becomes “L” for a predetermined period. In synchronization with this, the write signal * WE output from the result memory control unit 16 to the result memory 17 becomes active level "L". Therefore, every time the transfer of one line of image data is completed, the calculation result by the first calculator 20 is stored in the result memory 17.

The signal * OE2 is output one clock later than the signal * OE1. In synchronization with this, the write signal * W output from the result memory control unit 11 to the result memory 17
E becomes the active level “L”. Therefore, the transfer of the image data for one line is completed, and the first computing unit 20
Is stored in the result memory 17 by
The calculation result by the second calculator 30 is stored in the result memory 17.

The signal * OE3 and the write signal * WE for the signal * OE3 are output in synchronization with the clock GCLK while the last line transfer signal * LV is at the active level "L". That is, the signal * OE3 and the write signal * WE corresponding to the signal * OE3 are output the number of times corresponding to the number of pixels in one line each time image data of the last line is input. Therefore, when transferring the last line, the third computing unit 40
Each time the calculation for each digit is completed, the calculation result is stored in the result memory 17.

In the second transfer, the result memory 1
7 transfers the data P (y). In the third transfer, data P ₁₀ (y) is stored in the result memory 17.
Is transferred. At the time of the second and third transfers, the signal MODE is a signal for selecting data from the result memory 17. Therefore, the data DATA output from the selector 12 becomes the data from the result memory 17.

At the time of the second and third transfers, the transfer control signals * BUSY, * HS, * VLD
In addition, a signal (not shown) corresponding to the above LINE2 is output from the result memory control unit 16, and the transfer control signals * BUSY, * HS, * VLD, * LV, L from the image memory control unit.
INE2 is not output. Also, since the signal * LV during the last line transfer is not output, the signal * OE3 does not become the active level "L". Also, data for one line is transferred. Therefore, at the time of the second and third transfer, * OE1, * OE2, * OE3 and *
The timing of the WE is the timing of the portion T in FIG.

However, at the time of the second and third transfers, the signal * BUSY,
The signal HS and the signal HS1 are as shown by broken lines.
Therefore, in this case, the signal * OE1 is created as follows. That is, a signal * BUSY1 (not shown) obtained by delaying the signal * BUSY by two clocks is created, and the signal * BUSY is generated.
A signal HS ′ (not shown) similar to the signal HS at the time of the first transfer is created by USY1 and the signal * BUSY. Further, the signal HS ′ is delayed by one clock period, and the signal HS ′ similar to the signal HS1 in the first transfer is transferred.
1 '(not shown) is created. And the signal * HS 'is L
Level, the signal * HS1 'is at the H level, and the signal LINE
When the signal similar to 2 is at the H level, the signal * OE1 is set to the active level "L" for a predetermined period. Also in this case, the signal * OE2 is set to the active level "L" one clock later than the signal * OE1.

Although the above description has been given of the case where the main scanning direction of the image memory 2 is the x-axis direction, the present invention can be applied to the case where the main scanning direction of the image memory 2 is the y-axis direction. . FIG. 10 shows the operation contents of the arithmetic units 20, 30, and 40 in this case.

[0063]

Effects of the Invention According to the present invention, by using three arithmetic units, by transferring three data from the storage device of the image memory or result memory, zero-order moment M _00, 2 one primary moment M ₁₀ , M ₀₁ and the synergistic moment M ₁₁
Are obtained at high speed, and the projection operation results (Σ _x I (x, y) and Σ) required for calculating the second moments M ₂₀ and M ₀₂ are obtained.
_yI (x, y)) is also obtained at high speed. Therefore, the processing time for calculating the moment can be reduced without increasing the size and cost of the apparatus.

[Brief description of the drawings]

FIG. 1 is an electric block diagram illustrating a configuration of an image processing apparatus.

FIG. 2 is an electric block diagram illustrating a configuration of an image calculation unit in FIG. 1;

FIG. 3 is a timing chart showing a transfer control signal and image data when image data is transferred from an image memory.

FIG. 4 is a timing chart showing signals of respective units in FIG. 2 in the first transfer.

FIG. 5 is a schematic diagram showing each calculation result storage area in a result memory;

FIG. 6 is a schematic diagram illustrating the operation contents of each operation unit and the operation contents of a CPU;

FIG. 7 is a schematic diagram showing the contents of a calculation performed by a first calculator in the first transfer;

FIG. 8 is a schematic diagram showing the content of a calculation performed by a second calculator in the first transfer.

FIG. 9 is a schematic diagram showing the content of a calculation performed by a third calculator in the first transfer.

FIG. 10 is a diagram illustrating the calculation contents of each operation unit and the CPU when the main scanning direction of the image memory is the y-axis direction;
FIG. 6 is a schematic diagram showing the content of the calculation by the.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Image memory 3 Image processing unit 12 Selector 13 Counter 14 ALU control unit 15 I / O register 16 Result memory control unit 17 Result memory 20 First computing unit 21 Multiplier 22 Adder 30 Second computing unit 31 Adder 32 Latch circuit 40 Third computing unit 41 Adder 42 Line memory 43 Latch circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-168332 (JP, A) JP-A-4-216179 (JP, A) JP-A-63-123175 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) G06T ⁷ /00-7/60 G06T 1/00 G01B 11/00-11/30

Claims (2)

(57) [Claims] An image memory for two-dimensionally storing image data of an object, a first arithmetic unit having an accumulative product-sum operation function, a second arithmetic unit having an accumulative addition function, and accumulation of the image memory in the sub-scanning direction. An arithmetic circuit having a third arithmetic unit having an addition function; a result memory for storing the arithmetic result of the arithmetic circuit; image data read from the image memory and input to the arithmetic circuit; Is calculated for each line, the sum of the product of the image density of each pixel included in the line and the corresponding line number in the sub-scanning direction is calculated, and the second computing unit includes the sum of the products in each line in the main scanning direction. The sum of the image densities of all the pixels
A first transfer mode executing means for causing a third calculator to calculate the sum of image densities of all pixels included in each line in the sub-scanning direction and storing the calculation results in a result memory; The operation result of the second operation unit or the third operation unit obtained by the execution means is read from the result memory and input to the operation circuit, whereby the first operation unit
One of the first moments is calculated, the second calculator calculates the zeroth moment, and the calculation results are stored in a result memory by a second transfer mode execution means and a first transfer mode execution means. The operation result of the first operation unit is read out from the result memory and input to the operation circuit, so that the first operation unit calculates the synergistic moment and the second operation unit calculates the other of the two primary moments. An image processing apparatus comprising: third transfer mode executing means for storing the results of these calculations in a result memory; and calculating means for calculating two second moments based on data stored in the result memory. . A first arithmetic unit including a multiplier and a first adder, which increments the count value by one each time data is input to the arithmetic circuit, and calculates one scan of image data from an image memory; The output of the counter, which is reset each time the signal is input to the circuit, and the result of integrating the data input to the operation circuit are cumulatively added. The second operation unit includes a second adder. The third arithmetic unit includes a third adder and a line memory that holds the output of the third adder for at least one scan in the main scanning direction of the image memory. 2. The method according to claim 1, wherein the image data input from the image memory to the arithmetic circuit and the addition result of the line in the sub-scanning direction corresponding to the input image data stored in the line memory are accumulated. Image processing equipment .