JPH02210837A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To enable the dimension not exceeding the resolving power of an exposure device to be assured by a method wherein the pattern width formed by a conventional lithographic process and etching process is reduced by an etching away process from the sidewalls of the pattern. CONSTITUTION:An element isolation region 2 and a gate oxide film 3 are formed on an Si substrate, furthermore, after depositing CVD polycrystalline Si, a gate electrode 4 is formed by a photolithographic process and a dryetching process and after forming source.drain regions 5, an SiO2 film 6 is formed. At this time, the etching rate of the SiO2 film 6 on the sidewalls of the vertically rising gate electrode 4 to HF etchant being higher that that of the SiO2 film on the other positions, after etching away the SiO2 film 6 only on the gate sidewalls using BHF, only the sidewalls of the gate electrode 4 are etched away using the etchant of poly-Si mainly composed of HF and HNO3. Through these procedures, the dimension of the gate electrode 4 can be cut down.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

Conventionally, when forming a pattern with predetermined dimensions, the photoresist itself was patterned with predetermined dimensions in a photoresist process, and the dimensions were transferred to other films as accurately as possible. A conventional example of this is ``Introduction to VLSI Technology'' by Naoki Shibata et al., published by Heibonsha, 1986. On the other hand, as elements become finer, their dimensions become less than 0.5p, approaching the resolution of current optical exposure apparatuses.

[Problem to be solved by the invention]

However, it is clear that miniaturization will continue to advance in order to improve device characteristics, and it will become necessary to form patterns with dimensions that are lower than the resolution of the optical exposure apparatus.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device that forms finer patterns.

[Means to solve the problem]

In order to achieve the above object, (1) in the semiconductor device manufacturing method according to the present invention, after a pattern is formed by a photolithography process and an etching process, the etching rate of the protective film deposited on the side surface of the pattern is lower than that of the protective film deposited on the top surface of the pattern. A protective film is deposited by a film forming method faster than the etching speed of the protective film, and only the side protective film is etched with an etching solution for the protective film, and then only the side wall of the pattern is etched with an etching solution that etches only the pattern. It is something.

〔Example〕

An embodiment of the present invention will be described in detail with reference to the drawings.

In this example, a MOS field effect transistor (MOSF) is used.
The method for forming a gate electrode pattern (ET) will be described as an example, but the same applies to other pattern forming methods.

FIG. 1(a) shows the cross-sectional structure of the MOSFET after the gate electrode is formed. An outline of this manufacturing procedure is shown below.
First, element isolation regions 2 are formed on a Si substrate 1 using the LOGO3 isolation method. Next, gate oxide film 3 is formed by a thermal oxidation method. Furthermore, after depositing CvD polycrystalline Si as a material for the gate electrode 4.

Gate electrode 4 is formed by a photolithography process and a dry etching process. This dimension is on the order of O.s with the current light exposure technology. Thereafter, the source/drain regions 5 are formed by ion implantation.
As shown in b), approximately 2
000 8102 membranes 6 are formed.

A feature of the Sin film 6 formed by the ECR plasma CVD method is that the HF etching speed of the 5in2 film 6 existing on the vertical sidewall of the gate electrode 4 is faster than that of the Sin film in other parts. This speed difference is 1
: About 10 times or more compared to 68HF. Utilizing this characteristic, only the Sin film 6 on the gate sidewall is removed by etching with BHF as shown in FIG. 1(c). After that, 8F
As shown in FIG. 1(d), only the side walls of the gate electrode 4 are etched using a poly-Si etching solution containing INO3 as the main components. As a result, the gate electrode 4
It becomes possible to reduce the dimensions of. Next, SiO□
After removing the film 6, a source/drain region is formed by ion implantation into the low concentration region between the gate electrode 4 and the source/drain region 5.
Source/drain region 7 with a lower concentration than the drain region 5
form. Next, as shown in FIG. 1(e), the SiO□ film 8
After approximately 5,000 layers were formed by the CVD method, contact holes were formed, and source/drain AQ electrodes 9 were formed through the contact holes.

Complete the manufacturing of semiconductor devices.

[Effects of the Invention J As explained above, according to the present invention, the width of a pattern formed by a normal photolithography process and an etching process can be reduced by etching its sidewalls. By using this, it becomes possible to form dimensions that are lower than the resolution of the exposure apparatus.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention in the order of steps. 1... Si substrate 2... Element isolation region 3... Gate oxide film 4... Gate electrode 5.
7... Source/drain region

Claims (1)

[Claims] (1) After forming a pattern through a photolithography process and an etching process, a protective film is deposited using a film formation method in which the etching rate of the protective film deposited on the side surfaces of the pattern is faster than the etching rate of the protective film deposited on the top surface of the pattern. A method for manufacturing a semiconductor device, comprising: etching only the side protective film with an etching solution for the protective film, and then etching only the sidewall of the pattern with an etching solution that etches only the pattern.