JPH02210532A - Code processor for complement of two - Google Patents

Abstract

PURPOSE:To decrease the number of full adders and increasing the computing speed for addition of complements of 2 without increasing the circuit area by providing an inverter to invert the carry signal received from a lower rank of an adder to which an MSB of an input signal is inputted as well as the addition output of the adder. CONSTITUTION:The logical arithmetic of a code bit process is checked and the polarities of A0 - A3 and B0 - B3 of the input data are operated via a circuit equal to a full adder. Thus code bits of the output signals and the (MSB - 1)-th bit addition output are obtained via the full adders 11 - 14 equal to the number of input data. In other words, an inverter 15 is set between adders 13 and 14 together with an inverter 16 added to the addition output of the adder 14. As a result, a processor for complement code of 2 can be obtained with the circuits 11 - 14 equal to the number of input bits in case the processor is produced with a semiconductor integrated circuit. Thus it is possible to reduce the circuit area and to increase the computing speed.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a code processing device for two's complement addition.

(Prior art) Conventionally, when handling binary data, various notations such as integer, 1's complement, Gray code, etc. are used to represent the data depending on the situation, but when performing addition and subtraction, positive value,
Two's complement notation is often used to take advantage of the advantage of being able to perform addition and subtraction without having to be aware of negative values.

FIG. 2 shows an example of a conventional complement code processing device.

In FIG. 2, 21 to 25 are full adders, Ao to A3 and B. to B3 are 4-bit binary input data, and M S B (A3 and B3) of the input data is a sign bit. So to S4 are 5-bit output signals, and the MSB (S4) of the output signals is a sign bit. FIG. 3 shows a conventional code bit processing device. In FIG. 3, 31 is a full adder (1);
32 is a full adder (2), A and B5 are input signal M
SB is the sign bit, S MSB-1 is the data of the addition result, S is the MSB of the output and the sign bit, C3 is the carry human signal from the lower adder, C5 is the full adder (1,) 31
This is the output carry signal of the full adder (2) 32 and becomes the carry input signal of the full adder (2) 32.

Next, the operation shown in FIG. 3 is expressed in truth table 1. As is clear from the truth table in Table 1, S is the sign bit of a two's complement number.

Table 1 (Problems to be Solved by the Invention) However, in the conventional code bit processing method described above, the number of full adders required is equal to the number of output bits (number of input bits + 1) as shown in Figure 2. , and it takes the same number of carry signal transmission times as the number of output stages of the full adders. In other words, the only way to increase the calculation speed of addition using conventional circuit systems is to increase the speed of each carry process, and methods such as the carry rick-ahead method have the problem of complicating the circuit and increasing the circuit area. Ta. In addition, a full adder (2
) 32 with a circuit dedicated to code processing, the A5
．． B5. The logical formula for processing S, for the input of C, is 5s=(A, -B5+A, ・B,)C5+A, -B, ・
If it is C9 and is realized with a C-MOS circuit, at least about 20 transistors are required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a two's complement code processing device which has a simple circuit, therefore, a small circuit area and a high processing speed.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a two's complement code processing device that reconsiders the logical operation of code bit processing, that is, S , =A, ·B, +( A, +B,)C.

In addition, the carry output C6 of the full adder is calculated by focusing on the arithmetic expression 'C,=A,・B5+(A,+B,)C:1, and manipulating the polarity of the input data using the same circuit as the full adder. Accordingly, the sign bit of the output signal and the addition output of S□R-x are obtained using the same number of full adder circuits as the input data.

(Function) Therefore, according to the present invention, when realizing a two's complement code processing device using a semiconductor integrated circuit, an adder circuit is created by connecting cell patterns of full adders. Since it can be realized with a few minutes of total adder circuits, it has the effect of reducing the circuit area and increasing the calculation processing speed.

(Embodiment) FIG. 1 shows four diagrams of a semiconductor integrated circuit according to an embodiment of the present invention.
This shows a bit full adder. In Figure 1,
11 to 14 are full adders, 15 to 19 are inverters, Ao to A3 and B. or B3 is the input signal,
So to B4 are addition output signals.

Next, the operation of the above embodiment will be explained. Figure 1 (A)
Input signal A. -A3 and B. -B3 are input to full adders 11-14, respectively.

Each full adder can obtain a positive-polarity carry signal to the next stage and an addition output in response to two positive-polarity input signals and a positive-polarity carry input signal. That is, the following operations are performed in the full adder.

Go=A-B+C1(A+B) S,=(A-B+A-B)C,+(A-B+A-B)C
.

However, A and B are inputs, C is a carry input, and co.

So is carry output and addition output, respectively.

Here, an inverter 15 is provided between the full adders 13 and 14,
By adding the inverter 16 to the addition output of the full adder 14, the following calculation will be performed. That is, S, = A-B + C1 (A-B), where S is a two's complement sign operation, and S. is MS
It is equal to the addition processing result of the B-1st bit.

As described above, according to this embodiment, by providing an inverter that inverts the carry signal from the lower order of the adder into which the MSB of the input signal is input and the addition output of the adder, two positive polarity signals are provided. Complement code processing results and addition output can be obtained.

FIG. 1(B) shows another embodiment of the present invention, in which the MSB (A3.B,) of two input signals is input to inverters 17 and 1.
In this embodiment, the polarity is inverted by the inverter 8 and the carry output signal (S4) to the higher order of the full adder is inverted by the inverter 19. Figures 1(A) and 1(B) have equivalent functions.

(Effects of the Invention) As is clear from the above embodiment, the present invention reduces the number of full adders so that two
This has the effect of increasing the computation speed of complement addition of .

[Brief explanation of the drawing]

FIG. 1 shows a two's complement code processing device according to an embodiment of the present invention, FIG. 2 shows a conventional two's complement code processing device, and FIG. 3 shows a conventional code bit processing device. 11 to 14.21 to 25.3],, 32...
- Full adder, 15 to 19... Inverter, Ao to A4. Bo to B4 - input signal, So to S4 - output signal, cl - carry manual signal from lower order, C9 - carry output signal. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure (A) Figure

Claims (2)

[Claims] (1) A signal processing circuit capable of obtaining a carry output signal and an addition output signal to the higher order for each 1-bit input signal of the addend signal, the summand signal, and the carry signal from the lower order, By using signals obtained by making the addend signal and the summand signal opposite in polarity as input signals of the signal processing circuit, the carry signal to the higher order is made into a two's complement inverted sign output signal, and the addition output A two's complement code processing device characterized in that a signal is an addend result. (2) A signal processing circuit capable of obtaining an upper carry output signal and an addition output signal for each 1-bit input signal of an addend signal, an augend signal, and a carry signal from a lower order; By using a signal obtained by inverting the polarity of the carry signal from the lower order as a carry input signal, the carry signal to the upper order becomes a two's complement sign output signal, and the addition output signal becomes an inverted addend. A two's complement code processing device characterized in that the result is a two's complement code processing device.