JPH02209773A - Semiconductor nonvolatile mos memory - Google Patents

Abstract

PURPOSE:To prevent erroneous reading of data and an increase in power consumption by forming an impurity diffused layer of two elements which are one having large electric field concentration and the other having small electric field concentration to be used as a drain at the time of reading. CONSTITUTION:An impurity diffused layer 13 of a terminal C side of two impurity diffused layers is formed in a LDD structure. That is, the layer 13 of the terminal C side is formed of a 2-layer structure of an N<-> type layer 15 having low N-type impurity concentration at its gate side and n a N<+> type layer 16 having high N-type impurity, connected to the N<-> type layer. An impurity diffused layer 14 of a terminal B side is formed only of a normal N<+> type layer having high impurity concentration. In case of reading after negative charge is stored (written) at a floating gate 2, the layer 13 is used as a drain, and a positive voltage for reading is applied to the terminal C. In this case, since the impurity concentration of the layer 15 is low, a concentration of the electric field near the drain can be alleviated. Thus, it can prevent carrier for causing a leakage current. Therefore, the leakage current can largely be reduced.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention generates carriers when writing data,
Data is read by accumulating this carrier.
Semiconductor nonvolatile MOS type memory.

[Conventional technology]

A floating gate capable of storing charges or a potential well consisting of a trap level is created in the gate insulating film of a conventional semiconductor nonvolatile MOS type memory MOSFET to store positive or negative carriers. M.O.S.
The threshold voltage (A) of the FET changes depending on the polarity and polarity of accumulated carriers, and detection of read or storage state depends on the conduction state between the source and drain.

This kind of semiconductor non-volatile MOS type memory (FAMOS)
In the memory, as shown in the cross-sectional diagram of FIG.
A gate insulating film 4 is embedded in the surface of the P-type Si substrate 1 . Floating gate 2 made of polycrystalline silicon
A two-layer gate 10 consisting of a control gate 3 and a drain 5. is formed around the two-layer gate 10, and a drain 5. Source 6 and AI
A wiring 7 is formed. A, B, and C are control gates 3. Terminals connected to the source 6 and drain 5 are shown.

When "writing" to the FAMOS memory, a positive program potential is applied to the control gate 3 and drain 5. At this time, a channel is formed between the drain 5 and the source 6 and a current flows, but at this time the electrons are accelerated and ionized by collision (avalanche breakdown). Only the high-energy electrons (hot carriers) generated at this time are drawn into the floating gate 2 via the gate insulating film If and accumulated.
Floating gate 2 is negatively charged.

Further, during erasing, normally in the FAMO 3, the electrons in the floating gate are turned into carriers by irradiation with ultraviolet rays, and the electrons are released to the substrate or the control gate via SiO□.

Next, when a positive voltage of about 5V is applied to the control gate 3 for "readout", the electric field it creates on the substrate is canceled out by the electric field formed by the electrons in the floating gate 2, so the drain No current flows.

That is, the threshold voltage increases and the control gate 3 remains non-conductive when it is applied to the control gate 3 for about 5 seconds.

The gate (control gate) voltage-drain current characteristics before and after data writing are as shown in FIG. 3 (1).

[Problem that the invention seeks to solve]

However, for example, IEEE Electron
Device Letters vol. 2. N02
11, pp. 579-581 (1988), in the above-mentioned FAMOS memory, the drain is formed of N+ in which impurities are diffused at a high concentration, so that the electric field is concentrated near the drain. As a result, carriers are generated due to the Zener tunnel effect, and these carriers undergo tunnel transition toward the drain, causing conduction between the source and the drain and generating leakage current. In particular, the leakage current (drain current) becomes large after writing, and when the gate voltage is OV as shown in FIG. 3(1), this leakage current becomes 10-''A.

Therefore, especially when the leakage current is larger than the threshold value, the output to the control gate is 0°.

Even though it is not the time of reading, if the above leakage current exists, the drain-source becomes conductive, so the read value 1''' is always output.
Misreading dwells.

Furthermore, even when the leakage current is smaller than the threshold value, the presence of this leakage current causes an increase in power consumption when viewed as a whole of the LSI.

In order to solve these problems, the present invention aims to provide a semiconductor nonvolatile MO3O3 child memory that can prevent errors in data reading and increases in power consumption.

[Means to solve the problem]

In order to achieve the above object, the present invention comprises a carrier storage means capable of writing data by accumulating generated carrier charges, and an impurity diffusion layer forming a drain and a source, respectively, the carrier storage means The semiconductor non-volatile MO3O triple memory reads written data through conduction or non-conduction between the source and drain, which changes depending on the presence or absence of carrier accumulation in the semiconductor memory. , used as a drain during readout. It is characterized by comprising an impurity diffusion layer with low electric field concentration.

(Function) In the semiconductor nonvolatile MO3O triplet memory according to the present invention, the impurity diffusion layer is composed of an impurity diffusion layer with a large electric field concentration and an impurity diffusion layer with a small electric field concentration.

When reading data written in this semiconductor nonvolatile MO3O triple memory storage means, the one of the impurity diffusion layers with a smaller electric field concentration is used as a drain.

When reading data, the concentration of the electric field near the impurity diffusion layer is small, so generation of carriers that cause leakage current can be prevented. Therefore, leakage current, especially leakage current after data writing, can be significantly reduced, making it possible to prevent errors in data reading and increases in power consumption.

〔Example〕

Next, a FAMOS memory according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing the cross-sectional structure of this embodiment.

In FIG. 1, the FAMOS memory has a two-layer gate 10 structure consisting of a control gate 3 and a floating gate 2, similar to the conventional FAMOS memory explained in FIG. Alternatively, carrier charge storage means for storing positive or negative carriers generated during erasing is formed.

In this embodiment, of the two impurity diffusion layers, the impurity diffusion layer 13 on the C terminal side has an LDD structure. That is, C
The impurity diffusion layer I3 on the terminal side was connected to the N- layer 15 having a low N-senju obtuse concentration on the Day 1 side.

It has a two-layer structure of N° layer 16 with a high concentration of N Senju blunt objects.

On the other hand, the impurity diffusion layer 14 on the B terminal side consists only of a normal N layer in which impurities are present at a high concentration.

When reading after accumulating (writing) negative charges in the floating gate 2, the impurity diffusion layer 13 is used as a drain, and a positive voltage for reading is applied to the C terminal. At this time, since the impurity concentration of the N- layer 15 is low, concentration of the electric field near the drain can be alleviated, so generation of carriers that cause leakage current can be prevented. Therefore, as shown in the gate voltage-drain current characteristic diagram in FIG. 3(2), the leakage current can be significantly reduced (compared with FIG. 3(1)).

In the FAMO3 shown in FIG. 1 above, after negative charges are accumulated in the floating gate 2 (after writing), when the gate voltage is 0, the leakage current becomes IQ-14, and the high concentration impurity diffusion layer is Compared to the conventional example (FIG. 3 (1)) used as a read drain, leakage current can be reduced to 1/10'.

In the conventional FAMO 3 shown in FIG. 4 in the "0°" state where no voltage for reading is applied to the control gate 3 after fortune-telling, a positive voltage is applied to the drain and the source region is grounded and a leakage current occurs as shown in FIG. 3(1), which causes an increase in power consumption.

On the other hand, in the FAMOS memory according to this embodiment, the control gate 3 is in the '0°' state (the gate voltage is OV).
) leakage current is kept to an extremely low level, so an increase in power consumption can be prevented. Furthermore, due to the reduction of leakage current, the readout output on the source side (C terminal) is always 0°.
Therefore, erroneous reading of data can be prevented.

On the other hand, when writing data, the N'' layer 14 on the BOm side with high concentration of impurity diffused is used as a drain.When writing data, a voltage of about +25V is applied between the drain region and the control gate 3. Then, pot electrons generated by the avalanche breakdown phenomenon occurring at that time are accumulated in the floating gate 2. Therefore, in order to generate pot electrons, it is necessary to use the impurity diffusion layer 14 with a large electric field concentration as a drain/drain.

Therefore, the N layer 14 on the C terminal side, which is an impurity diffusion layer that does not have the L, DD structure, was used as the drain. Further, during erasing, a negative voltage is applied to the control gate 3 using the impurity diffusion layer 14 with high electric field concentration as a source.

By the way, if the impurity diffusion layer 13 of the LDD structure is used as a drain region during writing, the electric field concentration is small, so the amount of hot electrons generated is small, so the writing time becomes long, and in the worst case, data cannot be written. This also applies when the impurity diffusion layer 13 is used as a source during erasing.

Therefore, in the case of writing (erasing), the impurity diffusion layer 14 on the B terminal side is used as the drain (source), and in the case of reading, the impurity diffusion layer 13 with small electric field concentration is used as the drain, so that writing, erasing, and reading can be performed. Reading errors and increases in power consumption can be prevented without deteriorating performance.

IEDM Technical Digest
(IECM Technical Dine Varnish) p7
18-72L 1987), by setting the electric field concentration in the impurity diffusion layer to a value not more than the value indicated by the following (])2 and using this impurity diffusion layer as a drain during reading, it is possible to significantly reduce leakage current.

1, 2 +ToxX 1.9 MV/crr
l---(1) (In formula (1), ToX indicates the gate oxide film thickness, and cm indicates the gate length.) 1. The rain and source are alternately used during writing, erasing, and reading. In order to convert to It is possible to

Next, a method for manufacturing the FAMOS memory shown in FIG. 1 will be described.

Figure 2 shows the FA created in the manufacturing process.
FIG. 2 is a cross-sectional configuration diagram of a MOS memory.

In the process shown in FIG. 2(1), a thick field insulating film 20 (approximately 25
00) and a thin gate insulating film 21 (approximately 400) are both formed of silicon dioxide.

Further, in the insulating film, a floating gate 2 and controllers 1 to 1 to roll gates existing through the floating gate and the gate insulating film are formed with a thickness of 400 mm.

Next, move on to step (2), starting from the upper right direction on the drawing.
An impurity forming an N-layer with an angle of 5 degrees,
For example, P is I x 10I3crn-2 (70kev)
Perform oblique ion implantation.

As a result, field insulation TIg! Ions are implanted into the thin insulating film portions other than 20 and the gate region to form N515. At this time, since oblique ion implantation is performed, the impurity is diffused into the N-' layer to the right of the gate to the bottom of the gate, and the impurity is diffused into the N- layer to the left of the gate.

Shift to step (3), in the opposite direction to (2), that is,
Impurities for forming the N layer toward the bottom right of the drawing,
For example, arsenic is used at high concentration and high energy (5×I Q ”c
m-2 (100 kev)) is used for oblique ions. As a result, a <N' layer deeper than the N- layer can be formed. At this time, since arsenic is ion-implanted obliquely at an angle of 45 degrees from the direction opposite to the P ion implantation in (2), the N'' layer 13 on the right side of the gate is formed away from the gate. The N' layer 14 on the left side of 1 is formed to the bottom of the gate.As a result, the impurity diffusion layer on the left side of the gate is all N'
In contrast, the impurity diffusion layer to the right of the gate has an LDD structure having a region 15 with a low impurity diffusion concentration.

Next, by performing contact hole processing and wiring, it is possible to manufacture a FAMOS memory having an impurity diffusion layer with a small electric field concentration and an impurity diffusion layer with a large electric field concentration, as shown in FIG.

In the embodiments described above, a FAMOS memory having a two-layer gate structure of a floating gate and a control gate has been described, but the present invention is not limited thereto and can be applied to other semiconductor nonvolatile MO3 type memories. Examples of such other memories include FAMOS memory without a control gate, MNOS memory and MAOS memory of trap unit storage type, and FTMIS memory that is floating gate tunnel injection type memory.

Further, in this embodiment, an LDD structure is employed as a means for reducing electric field concentration in the impurity diffusion layer, but a DDD structure in which the N- impurity is implanted to a greater depth may also be used.

Furthermore, the numerical values explained in the above embodiments are merely examples, and other numerical values can be selected without being limited thereto.

Further, in the above embodiment, an N-channel MOS type memory has been described, but the present invention can also be applied to a P-channel MOS type memory.

[Effects of the Invention] As explained above, according to the present invention, the impurity diffusion layer is composed of one with a small electric field concentration and the other with a large electric field concentration, and the impurity diffusion layer with a small electric field concentration is used as a drain during reading. Reading errors and increases in power consumption can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram of a FAMOS memory according to an embodiment of the present invention, FIG. 2 is a cross-sectional configuration diagram showing the manufacturing process of this FAMOS memory, and FIG. 3 is a diagram showing the relationship between drain current and gate voltage. It is a characteristic diagram, and (1) is the conventional FAM.
2 shows the characteristics of the OS memory, (2) shows the characteristics of the FAMOS memory according to an embodiment of the present invention shown in FIG. 1, and FIG. 4 is a cross-sectional configuration diagram of the conventional FAMOS memory. In the figure, 1 is a P-type Si substrate, 2 is a floating gate 1.
, 3 is a control gate, and 13 to 16 are N carving blunt diffusion layers. 1st cause 〆P type 5144 counter pull” 1 Otsu 1] Te included ^ 4 cho branch / K'-Shin・ヱ (V) Gate voltage ()

Claims (1)

[Claims] (1) Comprising carrier storage means capable of writing data by accumulating generated carrier charges, and impurity diffusion layers forming a drain and a source, respectively, and changes depending on whether or not carriers are accumulated in the carrier storage means. In the semiconductor nonvolatile MOS type memory in which written data is read by conducting or non-conducting between the source and drain, the impurity diffusion layer has an impurity diffusion layer with a large electric field concentration and an electric field which is used as a drain at the time of reading. A semiconductor nonvolatile MOS type memory characterized by comprising an impurity diffusion layer with small concentration.