JPH02206912A - Interface control circuit - Google Patents

Abstract

PURPOSE: To improve the speed and efficiency of a digital system by shortening a rising time or a falling time by allowing source currents or sink currents to actively flow to or from the buffer of a circuit. CONSTITUTION: An invertor 1, delay means 2, and OR gate 3 are provided between a logic circuit 1 and a buffer 4 like shown by a broken line. Then, buffer output currents are allowed to actively flow through a line floating capacity so that a rising time from a low state to a high state can be reduced. When a negative logical mode is used, the charge of the line floating capacity is actively discharged through the buffer 4 so that a falling time from the high state to the low state can be reduced. Thus, a high speed and efficient digital system for communication hand shaking can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interface control circuit used as an interface between logic circuits for communication handshaking.

Prior Art and Its Problems Referring to FIG. 1, FIG. 1 shows an interface control circuit according to the prior art. When a "1" is applied to the buffer's enable line, a "0" appears at the output of the buffer. However, a problem arises when the output of the buffer is raised from low to high.

When the buffer enable line changes from "1" to "0", the potential of the buffer cannot immediately go high, and Vcc starts charging the line stray capacitance Cs through the pull-up resistor R1. As shown in Figure 2, the output is VCC
from tl, which is 10% of VCC, to t, where the output is 90% of VCC.
The rise time to l is approximately 3R+Cs. Normal R
1 is about 3.3 ohms and Cs is about 50 pf, so the rise time is 3x3.3x103x500x1
0, that is, about 500 nanoseconds. When the circuit is used in communications handshaking, logic circuits on one side may take a relatively long time by electronic standards while changing control lines from low to high to complete tasks and signal states on the other side. There must be. The overall speed and efficiency of the digital system is therefore reduced.

Means for Solving the Problems According to the present invention, when the output of the buffer changes from a low state to a high state or from a high state to a low state depending on whether positive logic or negative logic is used, An object of the present invention is to provide an interface control circuit in which rise time or fall time is significantly reduced by actively causing source or sink current to flow to or from a buffer in the circuit. According to the invention, handshaking in a logic system is therefore very efficient.

Embodiment FIG. 3 shows an interface logic circuit provided between two logic circuits Logic 1 and Logic 2 according to the invention. What makes the present invention different from the conventional technology is the logic circuit and buffer? 4, an inverter 11M extending means 2 and an OR gate 3 are provided as shown surrounded by broken lines. The input of the inverter 1 is connected to the logic circuit, and also to the input of the delay means 2 and to one of the input terminals of the OR gate 3. The output of inverter 1 is connected to the input of the buffer, and the output of the OR gate is connected to the enable line of buffer 4.

The output of buffer 4 is connected to Vc via pull-up resistor R1.
c Connected to power supply. Further, the output of the buffer 4 is connected to the logic circuit through a sense line so that the logic circuit detects the state of the output of the buffer 4. As shown in FIG. 3, the same interface control circuit as logic 1 can be used for logic circuit 2, but
Conventional interface circuitry may be used if rise time is not critical.

If logic 1 sends “1”, inverter 1 outputs “1”.
1” to “On”. The output of OR gate 3 is “1”
Since this enables the buffer 4, the output of the buffer is "On".

Logic 2 detects the state of logic 1 through the sense line. When the logic 1 changes state by changing the output to ``0'', the inverter inverts its input to 1''. One input of the OR gate is ``0''. However, if the delay FR is 10 nanoseconds Since a certain delay means 2 is delaying the input "1H" to the previous delay means, the output of the delay means 2 connected to the other input of the OR gate remains "1" for a certain time. The enable line of buffer 4 thus remains enabled and the "1" appearing at the output of the buffer actively charges the line stray capacitance. Therefore,
As shown in FIG. 4, since the rise time from the low state to the high state is greatly reduced, logic 2 can detect the state change of logic 1 much earlier, and subsequent operations can be performed at high speed. This results in much more efficient handshaking between logic circuits, improving the overall speed and performance of the digital system.

The rise time according to the invention is defined by
where C is the magnitude of the line stray capacitance Cs in farads, V is the potential across Cs, and I is Cs
The current in amperes flowing through Cs, and t being the rise time for Cs to change from a low state to a high state, is calculated as follows.

Q=CV It=CV t=VC/r T -r In L logic gate, high state is 2.8■5
．． 0V (7) range, low state OV-0,8V (7) [L! : The output drive current of the buffer 4 is typically 1511A. Therefore, if ■ is 3V and Cs is 50pf, the rise time is approximately t=VC/l-
50x10"'x3/15xio-3=io nanoseconds, which is much shorter than the rise time of the prior art, as shown in FIG.

Is the delay time required for delay means 2 a buffer? It depends on the output drive capacity of 4. The larger the drive capacity of the buffer, the shorter the required delay time, and vice versa.

The invention can also be used in negative logic mode as shown in FIG. In FIG. 5, the inverter is omitted and a pull-down resistor connects the output of the buffer to ground. Buff? When the output changes from "1" to O, the charge accumulated in the line floating capacitor 11Cs is rapidly discharged through the buffer, so the transition from the high state to the low state occurs very quickly, and the fall time is Its entire operation corresponds to the positive logic case.

To summarize the above, the inter-interface circuit according to the present invention consists of a buffer, an inverter, an OR gate, and a delay means. The interface control circuitry either allows the buffer output current to actively flow through the line stray capacitance, greatly reducing the low-to-high rise time, or, if a negative logic mode is used, allows the charge on the line stray capacitance to flow through the buffered line stray capacitance. A much faster and more efficient digital system for communication handshaking, where the fall time from a high state to a low state is greatly reduced by actively discharging the is obtained.

[Brief Description of the Drawings] Figure 1 shows a conventional interface control circuit, and Figure 2 shows waveforms to explain the rise time when the output of the conventional interface control circuit changes from low to high. 3 is a diagram showing a digital system comprising an interface control circuit according to the present invention, and FIG. 4 is a waveform for explaining the rise time when the output of the interface control circuit according to the present invention changes from low to high. FIG. 5 is a diagram illustrating a digital system comprising another preferred embodiment of an interface control circuit using negative logic according to the present invention. 1... Inverter, 2... Delay means, 3... OR
Gate, 4...buff? . Patent Applicant: Hongki Computer Co., Ltd.

Claims (5)

[Claims] (1) a buffer means having at least an input, an output, and an enable line; an inverter having an output connected to the input of the buffer means; one input connected to the input of the inverter and an output connected to the enable line of the buffer means; An interface control circuit for handshaking between logic circuits, comprising an OR gate connected to the line, and a delay means having an input connected to the input of the inverter and an output connected to the other input of the OR gate. . (2) An interface control circuit system for communication handshaking between logic circuits comprising at least two logic circuits in which at least one of the logic circuits is provided with the interface control circuit according to claim 1,
V from each of the logic circuits via a pull-up resistor.
A communications handshaking interface control circuit system comprising a sense line extending to the output of said buffer means connected to a cc power source. (3) buffer means having at least an input, an output and an enable line; an OR gate having one input connected to the input of the buffer means and an output connected to the enable line of the buffer means; and an input of the buffer means; an interface control circuit for handshaking between logic circuits in negative logic mode, comprising delay means having an input connected to the OR gate and an output connected to the other input of the OR gate. (4) An interface control circuit system for communication handshaking between logic circuits comprising at least two logic circuits in which at least one logic circuit is equipped with the interface control circuit according to claim 3,
A communications handshaking interface control circuit system comprising a sense line extending from each of the logic circuits to an output of the buffer means which is connected to ground through a pull-down resistor. (5) The interface control circuit according to claim 1 or 3, wherein the delay time of the delay means is inversely proportional to the output drive capacity of the buffer means.