JPH02206262A - Quaternary deciding circuit - Google Patents

Abstract

PURPOSE:To immediately decide a quaternary by means of a formed address by comparing inputted data with three thresholds on the respective levels of a shift register, successively designating a code flag and a zero flag based on a result, and inputting them to a decoder. CONSTITUTION:The input data are inputted to an accumulator 30. A threshold Th1 is set in a register 31. The data in the accumulator are compared with the threshold of the regiter, when the data are larger than the threshold, '0' is decided, when the data are not larger than the threshold, '1' is decided, and a flag S3 is designated. Next a threshold Th2 is set in the register 31, the data of in the accumulator are compared with the threshold Th2 of the register, and the values of the S3 to S1 are successively designated. Next, a threshold Th3 is set in the register 31, and the data of the accumulator 30 are compared with the threshold, and the values of the flags S3 to S1 are succes sively designated. By the values of the flags S3 to S1 designated in comparison with the respective thresholds, the quaternary is decided by the decoder.

Description

[Detailed Description of the Invention] [Summary] Regarding a four-value judgment circuit for digital signal processing (DSP), the purpose of this invention is to quantize input data into four values at high speed. A register to be set, an accumulator that accumulates input data, an arithmetic unit that compares the output of the register with the output of the accumulator, and a flag specified by the accumulator.
It consists of a decoder that judges the value, and the register A has thresholds Tb+, Tht, Tt+s.
are set sequentially, and a sign flag s is set for each threshold value when the operation result of the arithmetic unit is negative and reset when it is positive.
, s,, st, and "0' to detect O from the operation result.
Zero flags Z, , Z, , Z, which are set by the detection unit when the operation result is O and reset when the result is other than 0, are specified by the output of the shift register of the accumulator, and the sign flag and zero specified above are specified. The configuration is such that the designated value of the flag is determined by the decoder and four-value data is transmitted.

[Industrial application field]

The present invention relates to a four-value determination circuit for digital signal processing (DSP).

Digital signal processing (DSP) was initially developed for the purpose of real-time audio signal processing, but due to its high speed, it has come to be applied to various signal processing fields. One of these is digital runaway transmission (160K), which is the basis of l5DN.
bit/5ec).

A system configuration diagram of the digital transmission circuit is shown in FIG.

In the figure, 10 is a subscriber device, 20 is a central office device,
The subscriber device 10 and the central office device 20 are connected by a runaway digital transmission line (160 Kbit/5ec), and digitally control the telephone and FAX connected to the subscriber device. The subscriber device 10 includes a 2-wire and 4-wire converter 11, an A/D for prevention of interference, a D/A converter 1→, 1÷, an echo canceller 14, a waveform distortion etc. 15, a received data determiner 16, etc. consists of 160Kb sent from a digital transmission line.
The ps signal is transmitted using a 2BIQ code, which is a four-level code. In this case, the sampling rate is 80KII
z (12,5u 5ec) with normal audio processing 8KHz
10 times. Therefore, higher speed is required for digital signal processing.

Generally, the relationship between the 2-bit digital signal 2B and the IQ code quantized into four values is expressed as follows.

2B O,1−→ IQ +3 〃 0,0 −→ //+1 〃 1,1 −→ 〃−1 〃 1,0 −→ 〃−3 The present invention speeds up the process of quantizing input data into four values Provide a circuit to execute the

[Conventional technology]

A block diagram of a general digital signal processing LSI (DSP) is shown in FIG. 5(a). In the figure, 1 is an LSI, 2
3 is an address generation block ADR, 3 is an arithmetic logic unit ALU, 4 is a data memory RAM, 5 is an instruction memory ROM, and 6 is an input/output block I10.7 is an instruction decoder DEC.

The input/output block 6 exchanges input data, the instruction memory 5 stores execution memory, and the instruction decoder 7 executes the instructions. Address generation block 2
The arithmetic logic unit 3 performs arithmetic operations on the input data and stores the data in the data memory 4.

The arithmetic logic unit 3 performs the above-described digital signal processing operations, and a detailed diagram of the arithmetic logic unit 3 is shown in FIG. 5(b). In the figure, 31.32
．． 33 is register A, B, P, 34 is multiplier MPY, 3
5 is an arithmetic unit ALU, and 36 is an accumulator Acc.

The input bits input to the register A31 and the register B32 are multiplied by the multiplier 34, the output of the multiplier 34 is input to the register P33, the outputs of the register A31 and the register P33 are input to the arithmetic unit 35, and the output bits are input by the accumulator 36. It is accumulated and stored in memory.

FIG. 5(c) describes the flags of the arithmetic unit ALU in detail. In the figure, 35 is an arithmetic unit ALU, 37 is a sign flag S that is set when the operation result is negative and reset when it is positive, and 38 is a "0" that detects all bits of 0.
The detection unit 39 is set when the calculation result is “O” and becomes “0”.
Indicates a zero flag Z that is reset when the value is other than ``.

A flowchart of the conventional circuit described above is shown in FIG. The operation of conventional digital signal processing will be explained with reference to FIG. 5(c) and FIG. 6.

The input data is inserted into the accumulator Acc36 (41). A threshold Thl is set in the register A31 (42). Compare the outputs of arithmetic unit Acc36 and register A31 (
43).

As a result of the comparison (44), if the output of the arithmetic unit Acc36 is larger than the output of the register A31, set the next threshold Th2 in the register A31 (45), and compare the output of the arithmetic unit Acc36 and the output of the register A31 (46). ). As a result of the comparison, if the output of the arithmetic unit Acc36 is larger than the register A31, the 4-value is determined to be +3, and if not, it is determined to be +1 (47). Next, the comparison result calculation unit Ac in (44)
If the output of c36 is not greater than the output of register A31, set threshold Th3 in register A3148),
Compare the output of the arithmetic unit Acc36 and the output of the register A31 (49), and the output of the arithmetic unit Acc36 is the register A3.
If it is larger than the output of 1, the 4 value is determined to be -1, and if it is not larger, it is determined to be -3 (50).

[Problem to be solved by the invention]

In the conventional four-value determination method, three stages of comparison and determination circuits with thresholds are required, and the program setting is multi-stage, resulting in a long execution time.

The present invention provides a method in which a comparison judgment with a threshold value is performed each time, and a four-value judgment is immediately made based on the generated address.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 21
is the arithmetic unit ALU, 22, 23.24 is the sign flag SI+S, S3.25 is the “O” detection unit, 26, 27
．． 28 is zero flag z■.

Z, , zs, 29 indicate a decoder.

Sign flags 24, 23, 22 and zero flags 28, 2
7.26 are each constructed like a shift register, and the sign flag is set when the operation result is negative and reset when it is positive. In other words, it becomes “1” when it is 0, and when ≧0 “
The zero flag is set when the operation result is zero, and is reset when the operation result is other than zero. That is, the zero flag makes a determination when the operation result is O.

Therefore, the calculation result for zero flags 28, 27, and 26 is = 0.
When , it is set to 11'', and when ≠0, it is reset to 0.

In the above accumulation circuit, the input data is divided into three threshold values Th+Thz at each stage of the shift register.
Compare sequentially with Th:+, and the result is code 7-
7g Sr, Sz, S3 and zero 7-7g Z,, Z,,
Z, are sequentially designated and input to the decoder 29 to perform a four-value determination.

The judgment value generated by the decoder can be retrieved by address.

[Effect]

A flow chart of the present invention is shown in FIG. Figures 1 and 2
The operation of the four-value determination circuit of the present invention will be explained with reference to the drawings.

Input data is input to the accumulator 30 (51). A threshold Thl is set in the register 31 (52). The data in the accumulator is compared with the threshold value in the register, and if the data is larger than the threshold value, it is judged as "0", and if the data is larger than the threshold value, it is judged as "1", and flag S is set. specify. Sequentially specified by S2 and 31 and shift register (
53). Next, set the threshold value Th2 in the register 31 (54), and set the accumulator data and the register threshold value 'rhz.
, and sequentially specify the values of S3S, S, (55)
. Next, set the threshold value Thi in the register 31 (56
), the data of the accumulator 30 is compared with the threshold value, and the values of the flags S3 SZ S+ are sequentially designated (57). Specified flag s, sz s in comparison with each threshold
.

The decoder determines four values based on the value of (58).

In the above comparison process, when the input data and the threshold value are equal, that is, when the comparison result is detected as "0", the zero flag 2B, 27.26, performs a zero judgment, and when = 0, it becomes 1. , ≠ 0, it is determined as "0". Therefore, a flag is designated and input to the decoder 29 at each comparison stage with each threshold value.

The output of the decoder is loaded with the generated address and four values (+3.+1.-1.-3) are determined.

〔Example〕

FIG. 3 shows an embodiment of the circuit configuration of the arithmetic unit of the present invention. In the figure, 21 is an arithmetic unit, 24' is an S, a flip-flop FF3.23' is an S2 flag designation flip-flop FF2.22'' is an S, a flag designation flip-flop FFI.

When 3-bit data for accumulation is input to the arithmetic unit 21 and input to the flip-flop PF3, the data is sequentially input to the flip-flop FF2 . The flag bits SI+s, , s, are output to the FPI, and are sequentially sent to a decoder for four-value determination. The 2-bit signal is converted into a 4-value code and judged by the judgment circuit of the decoder as follows.

S3 St SI decoder 4-value judgment 000 0+3 oot t+1 Th.

Th2 Th3 In the above judgment circuit, S and the flag are threshold values Th.

Judging the comparison result with S! The flag is the threshold value Th.

The S, flag determines the comparison result with the threshold value Th+, and the h, St, S+ flag is “0”.
A four-value determination is made depending on whether it is # or “1”. Therefore, Ss
, St, Sr flags make 4 values (+3.+1
-1, -3) can be immediately determined.

〔Effect of the invention〕

According to the present invention, it is possible to immediately make a four-value judgment for each threshold value, compared to the conventional method in which a comparison circuit is provided for each threshold value of each stage to make a final judgment. Input data can be quantized into four values at high speed without increasing the size or execution time, thereby achieving high-speed processing.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration of the present invention, Figure 2 is a flowchart of the invention, Figure 3 is a circuit diagram of an embodiment, Figure 4 is a diagram of a digital transmission circuit system configuration, and Figure 5 is a conventional circuit. The configuration diagram, FIG. 6, shows a flowchart of a conventional example. In the figure, 1 is a digital signal processing LSI, 2 is an address generation block, 3 is an arithmetic logic unit, 4 is a data memory, 5 is an instruction memory, 6 is an input/output block, 7 is an instruction decoder, and 10 is a subscriber device. , 11 is 2 lines 4
line converter, 12 is a D/A converter, 13 is an A/D converter,
14 is an echo canceller, 15 is a waveform distortion, etc., 16 is a received data determiner, 20 is a telephone office equipment, 21.35 is an arithmetic unit, 22 to 24.37 are code flags, 25.38 is a zero detection unit, 26 to 28.39 are zero flags, 29 is a decoder, 30.36 is an accumulator, 31, 32.33 are registers,
34 is a multiplier, and 22'' to 24' are flip-flops. Note that (41) to (50), (51) to (58)
indicates the step number of the flowchart. Transfer F- Akira 1t

Claims (1)

[Claims] A register (31) for setting a threshold value, an accumulator (30) for accumulating input data, and an arithmetic unit (30) for comparing the output of the register and the output of the accumulator ( 21), a decoder (2) that determines four values based on the flag specified by the accumulator;
9), and the threshold value Th_1, Th_2, T is set in the register (31).
h_3 is set sequentially, and sign flags S_3, S_2, S_1 are set for each threshold value when the operation result of the arithmetic unit (21) is negative and reset when it is positive, and 0 is set from the operation result.
The zero flag Z_3, Z is set when the calculation result is 0 by the “0” detection unit that detects the
_2 and Z_1 are specified by the output of the shift register of the accumulator (30), and the specified values of the specified sign flag and zero flag are determined by the decoder (29) and four-value data is sent. A four-value judgment circuit characterized by: