JPH02206093A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To contrive to shorten a write processing time by providing a write control means consisting of a storage means for storing temporarily external input data and a control means for controlling a supply of a write use power source. CONSTITUTION:A write control means 12 consisting of a storage means 13 and a control means 14 is connected to every bit line of a memory cell 21. Therefore, by internal control information SD, external input data DIN is stored temporarily in the storage means 13 of the write control means 12, and thereafter, based on the external input data DIN stored temporarily, the control means 14 can apply a write power source Vpp simultaneously to a memory transistor connected to the same word line WL. In such a way, the external input data can be written simultaneously to all bits connected to the same word line WL, and it can be contrived to execute a write processing at a high speed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a write control circuit that writes external data to a memory cell of a non-volatile semiconductor memory device, particularly an EPROM (erasable and rewritable read-only memory). The purpose is to suppress the generation of parasitic load capacitance caused by the wiring pattern of the voltage section, shorten the write processing time, and speed up the read operation. and a write control means connected to each bit line, and the write control means includes a storage means for temporarily storing external input data, and a write control means for temporarily storing external input data, and a write control means connected to each bit line. The memory cell comprises a control means for controlling the supply of power, and the external input data is written into the memory cell based on internal control information.

[Industrial application field]

The present invention relates to a nonvolatile semiconductor memory device, and more specifically, to a write control circuit that writes external data into a memory cell such as an EPROM (erasable and rewritable read-only memory).

In recent years, with advances in microfabrication and high integration technology, the capacity of semiconductor memory devices has been increasing. Currently, nonvolatile semiconductor memory devices such as EPROMs having a memory capacity of 1 Mbit are being manufactured.

By the way, when writing data to a nonvolatile semiconductor memory device, for example, 8 bits x 64 kW.

A 512-bit E, FROM RD configuration has a problem in that it takes at least about one minute to write all the bits in one device.

Therefore, a write control circuit that writes data in units of bytes to multiple bit lines connected to the same word line is incorporated to shorten the write process.

However, in a circuit that writes in bytes, the wiring pattern of the high voltage section for data writing and the wiring pattern of the low voltage section of the data output section are mixed in a complicated manner, which can cause problems in the IC circuit pattern configuration. , there is a problem in that unnecessary load patterns and the like coexist in the data output section, which impedes high-speed read processing.

Therefore, there is a need for a semiconductor memory device that can further shorten the writing time of memory cells, simplify the wiring pattern, and improve performance.

[Conventional technology]

FIG. 8.9 is an explanatory diagram of a conventional example.

FIG. 8 shows a configuration diagram of an EP'ROM according to a conventional example.

In the figure, a conventional EPROM includes a memory cell 1, a row address buffer circuit 2, a decoder circuit 3, a column address buffer circuit 4, a column decoder circuit 5, a Y gate circuit 6, an input/output circuit with a built-in write control circuit 7, and a sense amplifier. It consists of a circuit 8 and a data output buffer circuit 9.

The external input data DIN is written as follows. First, write type source VPP, address signal XADD
, YADD, and external input data DIN. As a result, the XADD signal is amplified by the row address buffer circuit 2 and then applied to the row decoder circuit 3, and
One of n is selected. On the other hand, the YADD signal is amplified by the column address buffer circuit 4 and then applied to the column decoder circuit 5, one of YO-Yn is selected, and by turning on the selected transistor in the Y gate circuit 6, the memory cell is 1 memory transistor T31-T
One of the 39 is selected.

Next, by applying a write state as an external control signal, the internal control signal generates the write state in the internal signal generating circuit 10. The write control signal PGMI is rH,
becomes "L", and the gate transistor T25. of the data input circuit 7 with built-in T2O and write control circuit. T26.
T27 is operated and the write power supply vPP is supplied to the bit line selection transistors T28 to T30 of the Y gate circuit 6. Further, the internal control I signal generated by the internal signal generation circuit 10 connects the selected word line (any one of WLO to WLn) and the selected column line (any one of YO to Yn) to a high voltage. control (details, not shown).

As a result, the write power supply VPP is simultaneously applied to the gate and drain of one of the memory cell transistors T31 to T39 of the selected memory cell l, and external input data is written.

At this time, the write processing time is 0.1 (ms) ~
It requires about 1 (ms) or more.

For this reason, for example, in a 512-bit BPROM of 8 bits x 64 kwords, it takes about 1 minute or more to write all the bits in one device.

FIG. 9 is an explanatory diagram of problems related to the conventional EFROM.

In the figure, 11 is a write/read control circuit, in which only the write circuit is separated from the data input circuit 7 with a built-in write control circuit, and a Y gate circuit 6 and an input/output circuit 11a are arranged. . Also, write/
The read control circuit 11 is provided with a function of writing four bytes at the same time in order to shorten the writing processing time in units of one bit.

In the write/read control circuit 11 at this time, the wiring pattern of the high voltage section of the write power supply VPP system and the wiring pattern of the low voltage section of the normal operation power supply VCC system are mixed in a complicated manner. Sometimes, the word line and column line also need to be at a high voltage, so the row decoder circuit 3. The column decoder 5 is constituted by a high voltage part wiring pattern of the write power supply VPP system. Note that the wiring pattern of the high voltage section is required only during write processing.

(Problem to be Solved by the Invention) Therefore, in the EPROM of the conventional configuration as shown in FIGS. 8 and 9, stray capacitance is formed by the wiring pattern of the high voltage section near the data output buffer circuit 9. Ru.

Therefore, there is a problem in that the stray capacitance forms a parasitic load capacitance on the data output buffer circuit 9, impeding speeding up of the read operation.

On the other hand, since it is necessary to apply high voltage to the word line and column line during write processing, the row decoder circuit 3. The column decoder circuit 5 also has a mixed wiring pattern of a high voltage section and a low voltage section, which causes an increase in floating load capacitance and impedes speeding up of the read operation.

The present invention was created in view of the problems of the conventional example, and suppresses the generation of parasitic load capacitance caused by the wiring pattern of the high voltage section of the write/read control circuit and column decoder circuit, and improves the write processing. An object of the present invention is to provide a nonvolatile semiconductor memory device that can shorten the time and also speed up the read operation.

[Means for Solving the Problems] FIGS. 1(a) and 1(b) show diagrams of the principle of a nonvolatile semiconductor memory device of the present invention.

The device includes a plurality of memory cells 21 and the memory cells 2
1, and a write control means 12 connected to each bit line BL.
It consists of a storage means 13 for temporarily storing the input data IN, and a control means I4 for controlling the supply of the write power VPP to the memory cell 21. The write control means 12 is separated from the input/output means 15 for external data DIN, and is provided at a position facing the input/output circuit 15 with the memory cell 21 in between. It is characterized by this and achieves the above purpose.

[Operation] According to the present invention, the write control means 12 consisting of the storage means 13 and the control means 14 is connected to each bit line of the memory cell 21.

Therefore, the external input data DI is controlled by the internal control information SD.
N is temporarily stored in the storage means 13 of the write control means 12, and then the control means 14 simultaneously applies the write power supply VPP to the memory transistors connected to the same word line WL based on the temporarily stored external input data DIN. can be applied.

This makes it possible to simultaneously write external input data to all bits connected to the same word line WL, thereby increasing the speed of the write process, compared to the conventional writing method in byte units.

Further, according to the present invention, the write control means 12 is provided at a position facing the input/output means 15 with the memory cell 11 in between.

Therefore, the wiring pattern of the high voltage section of the write control means 12 and the wiring pattern of the low voltage section of the input/output means are separated. Furthermore, during the write process, the write power supply VPP is supplied to the drain of the memory cell to be written from the write control means 12, so the column line does not need to be at a high voltage, and the column decoder 19 is connected to the high voltage section wiring. Patterns are no longer needed.

Therefore, it is possible to eliminate the influence of the parasitic load capacitance of the conventional readout circuit due to the stray capacitance formed by the wiring pattern of the high voltage section.

This makes it possible to speed up data read operations.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 7 are diagrams for explaining a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows a configuration diagram of an EPROM according to an embodiment of the present invention.

In the figure, 21 is a memory cell, which is composed of a plurality of memory transistors Tll to T19. Each memory transistor Tll-T19 is connected to word lines XO-Xn and bit lines BLO-BLn.

Write control means 12a to 12c are provided for each bit line BLO to BLn.

Further, each of the write control means 12a to 12c is provided at a position facing the data output buffer circuit 15a with the memory cell 11 in between. Thereby, it is possible to avoid mixing the wiring pattern of the write source VPP system and the wiring pattern of the normally used voltage VCC system of the data output buffer circuits 15a and 15b.

One write control means 12a' consists of a plurality of transistors T1 to TIO. The storage means 13 is constituted by a flip-flop circuit 13a consisting of transistors T5 to T8. The control means I4 includes a gate circuit 14a comprising other transistors TI-T4, T9 and T10.
Consisted of.

Transistor TIO transfers external input data DIN to flip-flop circuit 13a by data set signal DSET.
This is to control the input.

The flip-flop circuit 1.3a receives the external input data DIN input to the data manual buffer circuit 15b via the gate transistor T24, the gate transistors T20 to T22 of the Y gate circuit 18, and the gate transistor TIO of the control means 14. It has a temporary memory function. Transistor T9 receives data reset signal DR3
By inputting T, data temporarily stored in the flip-flop circuit 13a is released.

Transistors T2 to T4 constitute a two-man NOR logic circuit, and external input data DI of the flip-flop circuit 13a
N and a write/read control signal PGMI are input to control the transistor T1.

The transistor T1 receives the output of the two-way NO'R logic circuit and controls the application of the write power supply PP to the bit line BLn.

15a is a data output buffer circuit, and memory cell 2
The data read from 1 is output as external output data DOT. 15b is a data manual buffer circuit, which inputs write data input from the outside as external input data DIN.

A sense amplifier 16 detects the contents stored in the memory cell 21. 22 is a row address buffer circuit that amplifies the address signal XADD and supplies it to the row decoder circuit 17. A column address buffer circuit 23 amplifies the address signal YADD and supplies it to the column decoder circuit 19. 17
is a row decoder circuit, which decodes the word line (WLO) based on the signal supplied from the row address buffer circuit 22.
-WLn). 19
is a column decoder circuit, which selects the column line (Y) based on the signal supplied by the column address buffer circuit 23.
(one of O-Yn) is selected. 18
is a Y gate circuit which receives the output of the column decoder circuit and selects bit lines BLO-BLn.

The Y gate circuit 18 consists of T20 to T22.

T23 is a gate transistor that controls the connection between the bit line selected by the Y gate circuit and the sense amplifier 16, and T24 is a gate transistor that performs write data transfer processing.

PGMI is a write/read control signal, DR3T is a data reset signal, DSET is a data set signal, WL
D indicates a word line all non-selection control signal, BLA indicates a write data transfer control signal, and internal control information SD
Configure.

20 is an internal signal generation circuit which receives external signals and generates PG
'MI, DR3T, DSET, WLD.

Generates internal control signals that control the operation of each functional circuit, such as BLA.

vPP is a write power supply, and normally has the same value as CC, and is a voltage of about 12 to 25 (V) during writing. ■CC
is the normally used power source, which is about 4 to 6 (V).

These constitute a nonvolatile semiconductor memory device according to an embodiment of the present invention.

Fig. 3.4 is an operation time chart related to the EPROM according to the embodiment of the present invention. Each shows an operation timing chart during write processing.

In FIG. 3, the write process is performed as follows.

First, address signals XADD and YADD are sent to the row address buffer circuit 22 and the column address buffer circuit 23.
Then, the external input data DIN is transferred to the data manual buffer circuit 1.
5b to increase the write/send power supply VPP to the write value.

As a result, the address signal XADD is amplified by the row address buffer circuit 22 and then acts on the row address decoder circuit 17 to select the word line to be written. After the address signal YADD is amplified by the column address buffer circuit 23, it acts on the column address decoder circuit 19, selects a column line to which external input data is to be transferred, and acts on the Y gate circuit.

After that, the output enable signal is turned on.

Chip enable signal CE, external write control signal PG
By setting each external control signal of M to a write state, the internal signal generation circuit 20 generates an internal control signal, which acts on each functional circuit to execute the write process.

That is, first, the entire word line non-selection control signal WLD becomes "H" and all word lines WLO to WLn are brought into a non-selected state. Next, write data transfer control signal B
When LA becomes "H", the external input data DIN amplified by the data manual buffer circuit 15b is input to the Y gate circuit 18 via the gate transistor T24, and the bit line BL selected by the Y gate circuit is input. The write control means 12 corresponding to the selected bit line BL
is transferred to the gate transistor TIO.

Furthermore, when the data set signal DSET becomes "H", the gate transistor TIO of each write control means 12 becomes "rol"L, and the external input data is set to the selection bit B.
It is temporarily stored in the L-compatible flip-flop circuit 13a. Note that the write control means 1 corresponding to the unselected bit line BL
Flip flow 2: The state of the passive circuit 13a does not change even if the gate transistor T1° is "ON" because the corresponding bit line is in the open state.

After that, the data set signal DSET goes to "L", then the write data transfer control signal BLA goes to "L", and then the word line all deselection control signal WLD goes to "L", and the external input data is reset to "L". The temporary storage operation in the flip-flop 13a of the write control means 12 is completed. The time required for this temporary storage operation is on the order of several [μS].

Furthermore, after this, the write control signal PGMI becomes "L", acts on the connection control transistor T23 between the Y gate circuit 18 and the sense amplifier 16, turns it rOFFJ, acts also on the column decoder circuit 23, and acts on the column line (YO to Yn
) are all unselected.

Furthermore, it acts on the two-man NOR gate of the write control means 12, obtains the logic with the output of the flip-flop circuit 13a, and turns the gate transistor T1, which is only the write target, into rO
NJ, and the write power supply PP is supplied only to the bit line BL connected to the memory cell transistor to be written in the memory cell 21. At the same time, the selected word line is also controlled to a high voltage (details not shown), and the write process of the memory cell transistor to be written is executed.

The LJ feedback of PGMI is set for the time required for writing, but this is controlled by an external control signal PGM and is in units of about 0.1 to 1 (ms).

Immediately after PGMI returns to "H", data reset signal DR3T becomes "rH", and all write control means 12
The temporary storage contents of the flip-flop circuit 13a are cleared. In addition, the data reset signal DR3T is "H" when the write power supply ■PP is the same value as the normal power supply ■CC.
”, and the flip-flop circuit 13a of the all write control means 12 is in a clear state.

FIG. 4 shows an operation timing chart during simultaneous write processing for a plurality of bits (or even all bits) connected to the same word line.

In the figure, first, external input data is temporarily stored in the flip-flop circuit 13a of the write control means 12 corresponding to each bit line BL. This is performed by a temporary storage operation instruction for external input data using an external control signal.

Address signals XADD, YADDO row address buffer circuit 22. After the preparation state by inputting the column address buffer circuit 23 and the external input data DIN to the data manual buffer circuit 15b, the operation shown in FIG. Similarly, the word line all non-selection control signal WL
D, a write data transfer control signal BLA, and a data set signal DSET are generated by an internal signal generation circuit, and a series of external input data is temporarily stored.

Next, the column address signal YADD is changed to the corresponding external input data, and the external control signal is again used to instruct the temporary storage operation of the external input data to temporarily transfer the data to the flip-flop circuit 13a of the corresponding write control means 12. Perform memory operations. Thereafter, in the same way, bit lines BLO to BLn
The corresponding write data is temporarily stored in each corresponding flip-flop circuit 13a.

After the temporary storage process in the flip-flop circuit 13a corresponding to all bit lines BLO to BLn is completed, a write operation is instructed by an external control signal. A write control signal PGMI is generated by an internal signal generation circuit. The internal response to the write control signal PGMI is
The operation is similar to that shown in FIG. 3, and a write voltage is applied to the memory cell transistor. However, during the operation shown in FIG. 4, the write data is temporarily stored in the flip-flop circuits 13a of all the write control means 12, and the gate transistors T1 of all the gate circuits 14a are controlled.

Therefore, since the write power supply VPP is controlled to be supplied to all bit lines BLO to BLn, the memory transistor connected to the selected word line (the selected word line is WL
In the case of O, writing can be performed to all Tll to T13) at the same time.

Note that the flip-flop circuit 1 of the write control means 12
Clearing of 3a is performed by the data reset signal DR3T, and DR3T is performed immediately before the temporary storage operation of write data after the write operation has been performed. Therefore, if writing is not completed in - times, the write operation instruction can be repeated using the external control signal without temporarily storing the write data again.

Thereby, data writing processing can be performed at high speed.

FIG. 5 shows a configuration diagram of an internal signal generation circuit according to the present invention.

The internal signal generation circuit generates internal control information SD necessary for write processing control.

In the figure, CB is a chip enable signal, OE is an output enable signal, PGM is an external write control signal, and VPP is a write power supply, which is the power supply and external control signal given to the internal signal generation circuit.

In the internal signal generation circuit, the word line all non-selection control signal WL
D, write data transfer control signal BLA, data set signal DSET, data reset signal DR3T and write control signal PGMr, high voltage sense circuit inverted output signal R
is generated and constitutes internal control information SD.

Further, FIGS. 6 and 7 show signals of each part of each logic circuit of the internal signal generation circuit according to the embodiment of the present invention.

In this way, in the configuration example of the present invention, the write control means 12 consisting of the flip-flop circuit 13a and the gate circuit 14a controls each bit line BLO to BLO of the memory cell 21.
It is connected for each Ln.

Therefore, all word line deselection control signal WLD, write data transfer control signal BLA, data set signal DSET
, data reset signal DSRT, etc., external input data DIN is temporarily stored in the flip-flop circuit 13a, and then, based on the temporarily stored external input data DIN, the gate circuit 14a outputs the same word line WLO, for example.
It becomes possible to simultaneously apply the write power supply PP to the memory transistors Tll to T13 connected to the memory transistors Tll to T13.

This allows all bits connected to the same word line to be written at the same time, making it possible to speed up the writing process, compared to the conventional method of writing in byte units.

Further, according to the present invention, the wiring pattern of the high voltage section of the write control means 12 and the input/output circuit 15a.

The wiring pattern of the low voltage section 15b is separated.

Furthermore, according to the present invention, during the write process, the column line (Y
Since there is no need to set the voltage (O-Yn) to a high voltage, a wiring pattern for the high voltage portion of the column decoder circuit 23 is not required.

Therefore, it is possible to eliminate the influence of parasitic load capacitance on a conventional readout circuit due to stray capacitance formed by the wiring pattern of the high voltage section.

This makes it possible to speed up data read operations.

[Effects of the Invention] As described above, according to the present invention, data can be written to memory cells connected to the same word line simultaneously on all bit lines.

Therefore, writing processing can be performed at high speed, and the effective writing processing time can be significantly shortened compared to the conventional method.

Further, according to the present invention, it is possible to reduce the parasitic load capacitance caused by the wiring pattern of the high voltage section. Therefore, it is possible to speed up the data read operation.

This makes it possible to improve the processing efficiency of a write-only device and to manufacture a high-performance nonvolatile semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a nonvolatile semiconductor memory device of the present invention, FIG. 2 is a block diagram of an EPROM according to an embodiment of the present invention, and FIG. 3 is an operation diagram of an EPROM according to an embodiment of the present invention. Timing chart (during 1-bit write processing); Figure 4 is an operation timing chart (during simultaneous writing of multiple bits connected to the same word line) of the EPROM according to the embodiment of the present invention; is a block diagram of the internal signal generation circuit according to the embodiment of the present invention, FIG. 6 is an operation time chart of the internal signal generation circuit according to the embodiment of the present invention, and FIG. FIG. 8 is a block diagram of a conventional EPROM, and FIG. 9 is an explanatory diagram of problems associated with the conventional EFROM. (Explanation of symbols) 21...Memory cell, 12...Write control means, 1゛3...Storage means, 14...Control means, 15...Input/output means, VPP...Write WL...word line, BL...bit line, Y...column line, DIN...external input data, SD...internal control information.

Claims (2)

[Claims] (1) A plurality of memory cells (21) and the memory cells (21)
1) bit line (BL) and word line (WL) connected to
) and a write control means (12) connected to each bit line (BL), the write control means (12) being connected to each bit line (BL).
) includes a storage means (13) for temporarily storing external input data (DIN), and a power supply (VPP) for writing to the memory cell (21).
A non-volatile semiconductor comprising a control means (14) for controlling the supply of the external input data (DIN) to the memory cell (21) based on internal control information (SD). Storage device. (2) The write control means (12) of claim 1 is separated from the input/output means (15) for external data (DIN), and is configured to operate the input/output circuit (15) with the memory cell (21) in between.
) A nonvolatile semiconductor memory device, characterized in that it is provided at a position facing the.