JPH02203527A - Etching process - Google Patents

Etching process

Info

Publication number
JPH02203527A
JPH02203527A JP2259689A JP2259689A JPH02203527A JP H02203527 A JPH02203527 A JP H02203527A JP 2259689 A JP2259689 A JP 2259689A JP 2259689 A JP2259689 A JP 2259689A JP H02203527 A JPH02203527 A JP H02203527A
Authority
JP
Japan
Prior art keywords
etching process
performed
melting point
formed
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2259689A
Other versions
JP2923962B2 (en
Inventor
Junichi Sato
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2259689A priority Critical patent/JP2923962B2/en
Publication of JPH02203527A publication Critical patent/JPH02203527A/en
Application granted granted Critical
Publication of JP2923962B2 publication Critical patent/JP2923962B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Abstract

PURPOSE: To enable a rectangular etching process leaving no residue at all to be performed by a method wherein, when a high melting point metal film is formed by reactive ion etching process, a mixed gas of fluorine base, chlorine base and oxidizing gas is used.
CONSTITUTION: A silicon oxide insulating film 3 is formed on a semiconductor substrate 4 and then a high melting point metallic film 1 comprising tungsten is formed on the film 3. Next, the whole surface is coated with a novolak base positive resist which is left conforming to a wiring pattern by lithographic process. Then, anisotropical dry etching process is performed by a reactive ion etching device. At this time, as for the applicable etching gas, a mixed gas of SF6, Cl2 and O2 is used. Through these procedures, the high melting point metal film 1 is left as a wiring pattern but leaving no undercut or normal taper cut at all thereby enabling acceptable etching process leaving no residue at all to be performed.
COPYRIGHT: (C)1990,JPO&Japio
JP2259689A 1989-02-02 1989-02-02 Etching method Expired - Fee Related JP2923962B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2259689A JP2923962B2 (en) 1989-02-02 1989-02-02 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2259689A JP2923962B2 (en) 1989-02-02 1989-02-02 Etching method

Publications (2)

Publication Number Publication Date
JPH02203527A true JPH02203527A (en) 1990-08-13
JP2923962B2 JP2923962B2 (en) 1999-07-26

Family

ID=12087221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2259689A Expired - Fee Related JP2923962B2 (en) 1989-02-02 1989-02-02 Etching method

Country Status (1)

Country Link
JP (1) JP2923962B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04254326A (en) * 1991-02-06 1992-09-09 Nec Corp Dry etching method of silicide film
US5871659A (en) * 1995-06-19 1999-02-16 Nippondenso Co., Ltd. Dry etching process for semiconductor
JP2014075593A (en) * 2013-11-22 2014-04-24 Semiconductor Energy Lab Co Ltd Method for manufacturing wiring
US9045831B2 (en) 1999-07-22 2015-06-02 Semiconductor Energy Laboratory Co., Ltd. Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04254326A (en) * 1991-02-06 1992-09-09 Nec Corp Dry etching method of silicide film
US5871659A (en) * 1995-06-19 1999-02-16 Nippondenso Co., Ltd. Dry etching process for semiconductor
US9045831B2 (en) 1999-07-22 2015-06-02 Semiconductor Energy Laboratory Co., Ltd. Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method
JP2014075593A (en) * 2013-11-22 2014-04-24 Semiconductor Energy Lab Co Ltd Method for manufacturing wiring

Also Published As

Publication number Publication date
JP2923962B2 (en) 1999-07-26

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees