JPH02201951A - Memory cell - Google Patents

Abstract

PURPOSE:To ensure the fully functioning capacitance while increasing the capacitance as a capacitor even in case of the same integration degree by forming an insulating film to become a memory capacitor to both of the upper and lower layers of a second electrode. CONSTITUTION:A first electrode 6 is composed of two layers of poly-Si films 6a and 6b. Further, an SiO2 film 7 to be memory capacitors are formed as 7a and 7b on the upper layer and the lower layer of a poly-Si film 8 to compose a second electrode. In this way, SiO2 films 7a and 7b to be memory capacitors are formed both on the upper layer and the lower layer of the poly-Si film 8 to be a second electrode. Accordingly, an area to be the memory capacitors is increased by a part of the SiO2 film 7b. Thereby, the capacity capacitance can be increased about two times so as to ensure the sufficient capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory cells, and particularly to dynamic memory (hereinafter referred to as DRAM).

[Conventional technology]

FIG. 3 is a cross-sectional view showing a stacked structure memory cell used in a conventional DRAM. In the figure, 1 is a P-type silicon substrate, 2 is a field oxide film for isolation between elements,
3 is a source/drain region of a field effect transistor (hereinafter referred to as FET), 4 is a gate oxide film of the FET, 5 is a gate electrode of an FET composed of a polycrystalline silicon film (hereinafter referred to as a Po1i-8i film), 6 7 is a Po1i-8i film which becomes the first electrode of the memory capacitor, and 7 is a silicon oxide film c and below as an insulating film which becomes the memory capacitor.
8 is a Po1i-8i film which becomes the second electrode of the memory capacitor, 9 is an insulating film for protecting the FET and the memory capacitor, and 10 is an aluminum film for wiring (hereinafter referred to as A). membrane).

Since the operation of the memory cell shown in FIG. 3 is generally well known, its explanation will be omitted.

(Problems to be Solved by the Invention) Memory cells used in conventional DRAMs are constructed as described above, but due to the desire for higher integration, 5iOz film 7
The opposing area between the first and second electrodes (i.e., Po
There was a problem in that it became difficult to increase the opposing area between the 1i-8i films 6 and 8, and it became difficult to obtain a sufficient capacity as a memory capacitor.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a memory cell that can secure a sufficient capacity as a memory capacitor in the case of high integration.

[Means to solve the problem]

The memory cell according to the present invention has a second memory capacitor.
A second conductive film (poli-3ill!i!) that becomes an electrode.
8) Oxidize the upper layer to form a second insulating film (S!Oz film 7b) that will become a memory capacitor, and electrically connect the upper layer to the first conductive film (SOzMA6a) that will become the first electrode. The third conductor film (Poli-8i film 6b)
and an upper layer of insulation I of the second electrode of the memory capacitor.
II (Sift film 7b) and the lower layer insulation 11Ji (SiC
) Z film 7a> both have a capacitance i of a melicapacitor.

(effect) Second ffim(1) of the memory cell in this invention.

In the upper and lower layers of the memory capacitor (first . Second insulation 11Q (SiOz*7
a, 7b), the area of the memory capacitor is approximately doubled, and the capacitance is approximately doubled.

〔Example〕

FIG. 1 is a sectional view of a DRAM memory cell according to an embodiment of the present invention. In the same figure, 1 to 5.9 to 1
Since 0 is the same as before, the explanation will be omitted.

The memory cell of this embodiment differs from the conventional one in that the first electrode 6
is a two-layer Po1i-3i film 6a (first conductor WA),
6b (third conductor WA). In addition, 5ICh IIQ (insulating film) 7, which becomes a memory capacitor, has 7a (first insulating film) and 7b (second insulating film) on the upper and lower layers of Poli-3i#8 that constitutes the second electrode.
It is formed as.

FIGS. 2(a) to 2(d) are cross-sectional views showing the manufacturing process of the memory cell shown in FIG. 1. The manufacturing flow will be explained below using the same figure.

First, 3.4 µm was deposited on a P-type silicon substrate 1 by a known method.
．． 5, an insulating film 9a is formed on the upper layer of the gate electrode 5 and part of the source/drain region 3 of the FET, as shown in FIG. 5(a). Then, Poti-3iWA6a is formed on the region of the source/drain region 3 where the insulation 11Q9a is not formed, and its surface is oxidized to form the 5102 film 7a.

Next, as shown in FIG. 6(b), Po I i -3iIgi 8 is formed on the upper layer of the SiO2 film 7a, a resist 11 is applied on this film 8, and the resist 11 is applied by photolithography as shown in the figure. pattern into the desired shape. Then, the Po1i-8i film 8 is etched using the patterned resist 11 as a mask. Thereafter, the surface of the Po1i-3i film 8 is oxidized to S! as shown in FIG. An Oz film 7b is formed.

Next, as shown in the same figure (d), 5iOzll<i7b
A PoIi-31fla6b is formed on the upper layer of the PoIi-31fla6b, a resist 12 is applied on the Po1i-8i film 6b, and the resist 12 is patterned into a desired shape by photolithography as shown. In this way Po1i-
The first electrode of the memory capacitor is formed by electrically connecting the 3i film 6a and the Po1i-3i film 6b.

The first electrode formed in this way, Po I
i-31llQ6a.

A memory capacitor is constituted by the 6b and 5iOz films 7a and 7b and the second electrode PoIi-8+l18. Then, by covering the entire surface with an insulating film 9b, the insulation @ 9a and 9b are integrated as shown in FIG. 1! 199 is formed. Then, a contact hole 13 is formed in a part of this insulating film 9 that exists on the source/drain region 3, as shown in FIG. 1, and an Aj film 1o is formed through this contact hole 13. , a memory cell having the structure shown in FIG. 1 is manufactured.

In this way, in this embodiment, the second electrode is Po
Since 5iOzllA7a and 7b serving as memory capacitors are formed in both the upper and lower layers of I i -8iM8, the area serving as a memory capacitor increases by the 5iOz film 7b. Therefore, even if the degree of integration is the same, the capacitor capacity can be approximately doubled compared to the conventional technology.

In this embodiment, a polysilicon film is used as the electrode of the memory capacitor, but other conductors can be used instead.

Furthermore, 5i02D is used as the insulating film of the memory capacitor.
Although I was used, the insulating film may be formed by a combination of a 5iOz film and a material such as a nitride film.

〔Effect of the invention〕

As explained above, according to the present invention, since the insulating film serving as the memory capacitor is formed on both the upper layer and the lower layer of the second electrode of the memory capacitor, the capacitance as a capacitor increases even if the integration degree is the same. It is possible to increase the capacity and ensure sufficient functioning capacity.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a memory cell according to an embodiment of the present invention, FIGS. 2(a) to (d) are cross-sectional views showing the manufacturing process of the memory cell shown in FIG. 1, and FIG. 3 is a conventional FIG. 3 is a cross-sectional view showing the structure of a memory cell of FIG. DESCRIPTION OF SYMBOLS 1... P-type silicon crystal plate, 2... Field oxide film, 3... Source/drain region, 4... Gate oxide film, 5... Gate electrode, 6, 6a, 6b... 1st
Polycrystalline silicon film (po I i -3i film) serving as an electrode, 7゜7a, 7b-...Silicon oxide III (Si
oz II), 8... Polycrystalline silicon film (ooli-3ill) serving as a second electrode, 9... Insulating film, 10
...Aluminum membrane (Ajll). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent: Masuo Daikun (and 2 others) Figure 1...P-type silicon substrate, 2...Field oxide film 3--source/drain region, 4--gate oxide film 5...gate electrode 6a , 6b-polycrystalline silicon film (poli-5i film) 7
a, 7b...Silicon oxide film (Sin, film) 8...
Polycrystalline silicon film (poli-3i film) 9...-Insulating film, 10... Aluminum film (AJ film) 13... Contact hole 1... P-type silicon substrate, 2... Field oxide film 3... Source/drain region, 4... Gate oxide film 5... Gate electrodes 6a, 6b - polycrystalline silicon 1lI (poli-3i film) 7a, 7b... Silicon oxide film (SiO! film) 8・
- Polycrystalline silicon film (pol i-3i film) 9a.
・Zettai aS, 12...Resist figure 3

Claims (1)

[Claims] A first insulating film that becomes a memory capacitor is formed on a first conductive film that becomes a first electrode of a memory capacitor that is electrically connected to a source or drain region of a field effect transistor formed on a silicon substrate. In a memory cell formed by laminating a second conductive film that becomes a second electrode of a memory capacitor, a second insulator that becomes a memory capacitor is formed by oxidizing the upper layer of the second conductive film that becomes a second electrode. A memory cell comprising a film formed thereon, and a third conductive film electrically connected to the first conductive film serving as the first electrode formed on the film.