JPH02199973A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make information storage period of all photo diodes equal to each other by providing a capacitive element to each photodiode, connecting each photodiode and a capacitive element during the information storage period and storing the picture element information at that time into the capacitive element. CONSTITUTION:Picture element information of a capacitive element 11 is stored based on an external storage signal and inverted signal. That is, the storage signal goes to a high level, the integration is started when a transistor(TR) MQ 6 is turned off and a TR MQ 7 is turned on and the electric charge stored in the capacitive element 11 is drawn in advance only by an integration time by the optical current of the photodiode 10. The storage signal and the inverse of storage signal are signals in common to each photodiode, then each photodiode starts integration simultaneously and makes it complete. Since a terminal voltage of the capacitive element being the picture element information is read via a current amplification means, the picture element information with high sensitivity is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state imaging device including an array composed of a plurality of light-receiving elements, and in particular, to a solid-state imaging device that can selectively drive a partial region. The present invention relates to solid-state imaging devices.

[Conventional technology]

Solid-state imaging devices are broadly classified into two types: a CCD (charge-coupled device) type and a MOS image sensor type, and the former is currently the mainstream. However, depending on the application, MOS image sensors are superior.

For example, information about only a limited number of light-receiving elements within the array may be required during a certain period of time. In that case, with the CCD type, there is no means to select elements within the array, so all the information of the array must be stored and transferred to a storage means such as an external memory, and then the necessary information can be selected using a computer or the like. There must be.

On the other hand, in the case of a MOS image sensor, partial reading is possible by replacing the shift register used for selecting light receiving elements on the array with a decoder and controlling the address line of the decoder from the outside.

FIG. 6 is a block diagram showing a conventional example of a partially drivable MOS image sensor. Here, a 10-bit address decoder 1 is used. The signal from the decoder 1 is logically ANDed with the strobe signal from the terminal 2, and is used as a selection signal to select the selection switch 4 of the photodiode 5.
sent to.

The purpose of the strobe signal is to prevent the timing of the output signal from the decoder 1 from varying depending on the address switching condition. Furthermore, this selection signal is ORed with a reset signal common to all elements applied to the terminal 3 before the selection switch 4 of the photodiode 5.

In this solid-state imaging device, before selecting a photodiode with the decoder 1, first, the reset signal is turned on to turn on all the selection switches 4, and all the photodiodes 5 and 5 are turned on.
clamps the charge of to a common voltage. The point in time when the reset signal is turned off is the common integration start time, and the period thereafter until it is selected by the decoder 1 is the integration period of each photodiode. The accumulated charge in the photodiode when selected by the decoder 1 is pixel information,
Pixel information from the selected photodiodes is sequentially transferred to the video line. This allows the video waveform to be observed externally.

[Problem to be solved by the invention]

However, this type of MOS image sensor has a low sensitivity to light because it transfers charges accumulated in a photodiode to a video line. Also, after the photodiode charge is reset on all elements at the same time,
Since the information storage period is until it is read out, the integration time differs for each photodiode. Therefore, there is a problem in that the read information must be converted into a correct integration time using means such as an external computer.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the solid-state imaging device of the present invention includes:
A plurality of photodiodes into which light from a pixel to be read is incident, a plurality of capacitors provided for each photodiode, and a plurality of capacitors that keep each photodiode and its corresponding capacitor in conduction during the information storage period. a plurality of current amplifying means provided for each capacitive element and outputting the terminal voltage value of each capacitive element to the outside as pixel information based on a selection signal during a readout period after an information storage period has elapsed; A plurality of reset means are provided for each of the plurality of photodiodes and reset the terminal voltage value of each capacitive element to a reference value based on a reset signal when a selection signal is input during the readout period, and a desired one of the plurality of photodiodes. and an address decoder that selects the current amplification means and provides a selection signal to the corresponding current amplification means and reset means. Further, the reset means and the address decoder each include a boot-up circuit.

[Effect]

Each photodiode is provided with a capacitive element, and each photodiode and the capacitive element are connected during the information storage period, and the pixel information at that time is stored in the capacitive element, so that the information storage period is the same for all photodiodes. In addition, since the terminal voltage of the capacitive element is read out via the current amplification means,
It is possible to read out pixel information with high photosensitivity. Furthermore, if a boot-up circuit is used for the reset means and address decoder, it can be used under a single low power supply.
Moreover, a single MOS channel structure such as N-type, which is lower in cost than 0MO8 or the like, can be used, resulting in a device with low power consumption.

〔Example〕

FIG. 1 is a partial circuit diagram showing an embodiment of the present invention, and shows a peripheral circuit corresponding to one light receiving element. The photodiode 10, which is a light receiving element, has its cathode grounded and its anode connected to the source of the MOS transistor MQ5.

The transistor MQ5 clamps the parasitic capacitance C9 of the photodiode 10 to a constant voltage, and therefore a low DC voltage V 1 is always applied to its gate. This transistor const.

The drain of the transistor MQ5 is connected to the connection point of the transistor MQ6.7. The transistor MQ6 is a switch that is turned on only during a time other than the time for accumulating pixel information (hereinafter referred to as integration time) to extract the photocurrent of the photodiode 10 and prevent blooming. The transistor MQ7 is a switch that is turned on only during the integration time to store pixel information as a photocurrent in the capacitive element 11 having a capacitance of co. Operation of these transistors MQ6 and MQ7 $-
Control is provided by an inverted accumulation signal and an accumulation signal applied to each gate. The inverted accumulation signal and the accumulation signal are mutually complementary signals.

Transistor MQ9 is a source follower for impedance converting the terminal voltage of capacitive element 11 and outputting it to video line 12. Further, the transistor MQIO is an element selection switch, and is driven and controlled by a selection signal from a decoder, which will be described later. Reference numeral 13 indicates a constant current source, which constitutes current amplification means 16.

An output terminal of a reset circuit 14 is connected to one end of the capacitive element 11 . This reset circuit 14 resets the voltage of the capacitive element 11 to a reference voltage during a predetermined period (reset period) during the read period, and includes a boot-up circuit 15 so that it can be driven under a single low power source. There is.

The boot-up circuit 15 includes transistors MQI to MQ4.
and a capacitive element 16, to which a transistor MQ8 is added to constitute a reset circuit 14.

FIG. 2 shows a part of the circuit of the 9-bit address decoder used in this embodiment, that is, a partial circuit corresponding to an element. This circuit consists of switching transistors MQ11 and MQ that determine the operation timing.
15. Transistor MQ1 for selecting address
2-1 to MQ12-9, and the transistor M013.14 and capacitive element 2 that constitute the boot-up circuit 20
It consists of 1. The output signal of this decoder obtained from the signal line 22 is applied as a selection signal to each gate of transistors MQI and MQIO in the circuit shown in FIG.

One set of circuits made up of the circuits shown in FIGS. 1 and 2 corresponds to one photodiode, and the solid-state imaging device of this embodiment includes the same number of circuits as the number of photodiodes. There is.

Next, the operation of this embodiment will be explained using timing charts shown in FIGS. 3 and 4. FIG. 3 shows the overall operation, and FIG. 4 shows the operation during one reading period in detail.

First, pixel information is stored in the capacitive element 11 based on an external storage signal and its inverted signal (see FIGS. 3A and 3B). That is, when the accumulation signal becomes high level and transistor MQ6 is turned off and transistor MQ7 is turned on, integration is started, and the charge previously stored in the capacitive element 11 is transferred to the photodiode 1o.
is extracted by the photocurrent for the integration time. Since the accumulation signal and the inverted accumulation signal are signals common to each photodiode, each photodiode starts and ends integration at the same time. Therefore, the integration time is the same for all photodiodes in the array.

Thereafter, at the end of the integration period, the transistor MQ7 is turned off and the transistor MQ6 is turned on, at which point the terminal voltage of the capacitive element 11 is fixed at a low voltage value proportional to the pixel information. Therefore, the voltage value of each capacitive element corresponding to each photodiode is a voltage value according to pixel information.

Next, the pixel information stored in the capacitive element corresponding to each photodiode is selectively and sequentially read out.

In the readout signal shown in FIG. 3(C), one pulse indicates one readout period, and the photodiode receiving the selection signal from the decoder during the readout period selects the pixel stored in the corresponding capacitor. Read information.

Here, the operation when receiving a selection signal during one read period shown by waveform C1 will be explained. When a high level selection signal is applied to the gate of transistor MQIO to turn on transistor MQIO, transistor MQ9 becomes active. That is, transistor MQ9 is current source 1
The source potential of the transistor MQ9 is fixed by the level shift of the voltage value of the capacitive element 11 so that a current equal to 3 flows. Therefore, a voltage with a slight potential drop across the transistor MQIO appears on the video line as shown in waveform e1 in FIG. 3(E). Thereafter, while this selection signal is at a high level, the charge accumulated in the capacitive element 11 is reset based on the reset signal shown in the waveform d1 of FIG. 3(D).

The voltage of the capacitive element 11 after reset is shown by waveform e2 in FIG. 3(E), and pixel information can be accurately detected by detecting the potential difference between waveform e1 and waveform e2. Then, in the next readout period shown by waveform c2, pixel information is read out for another photodiode selected by the decoder, and in the same manner, readout is performed one after another for desired photodiodes. be exposed.

Next, one read operation will be explained in detail using FIG. 4. Note that the read, reset, and video signals shown in FIGS. 3(C) to (E) are the same as those shown in FIG. 4 (D), (H), and (L), respectively.
).

The synchronizing signal shown in FIG. 4(A) is a signal applied prior to the read signal every - read period, and is applied to the gate of the transistor MQ11 of the decoder. Further, the inverted signal is applied to the gate of transistor MQ15. While the synchronization signal is at high level, the node N shown in FIG. 4(F)
1 potential is approximately higher than the synchronization signal of the transistor MQI.
Threshold voltage of I Only bones have a lower potential. Figure 4 (C)
The content of the address signal shown in is allowed to switch only during this period. The negative side (node N2 side) of capacitor 21 is at ground level because the inverted read signal applied to the gate of transistor MQ14 during this period is at high level as shown in FIG. 4(E). Therefore, the voltage at the node N1 is applied to the capacitor 21 as is.

Next, when the synchronization signal becomes low level (the inverted synchronization signal is high level), transistor MQ15 becomes active, so if one of the address signals aO to a8 has a high level signal, capacitor 21 The charge of transistor MQ12 and transistor MQ
15 to ground, and the photodiode corresponding to this decoder will not be selected. However, if all address signals aO-a8 are at low level, transistors MQ12-1 to MQI2
-9 is not turned on, so transistor MQ
15, the charge in the capacitor 21 is not discharged, and the operation moves on to the next operation.

That is, when the readout signal becomes high level while the inverted synchronization signal is high level, the voltage stored in capacitor 21 turns on transistor MQ13, so the potential of node N2 starts to rise, and as a result, the potential of node N1 increases. A so-called boot-up operation in which the potential is raised is performed, and the potential of the node N1 settles at a potential higher than the high level of the read signal. Therefore, node N2 has
The potential of the read signal appears as it is without any loss. This potential is applied to the transistor MQIO as a selection signal.

The MQI gate is directly driven to read and output pixel information to the video line as described above. In this way, this decoder circuit has extremely low power consumption because no continuous DC current flows, and the cost is also low because of the single channel configuration such as NMOS.

Next, the reset operation of the capacitive element 11 performed during the -read period will be explained. The purpose of the reset circuit 14 is to
The purpose is to supply the reset voltage to the gate of the transistor MQ8 without loss during the reset period τ shown in FIG. 4(H). The higher the reference voltage V applied to the drain of the transistor MQ8, the higher the dynamic range of pixel information, but the upper limit is [
(gate voltage of transistor MQ8) (transistor M
Q8 threshold voltage)], so it is set to a value slightly lower than that.

Therefore, ideally, the reset circuit 14 should be configured as shown in FIG. 5, and the gate potential of the transistor MQ20, that is, the selection signal, should be set to more than [(reset signal potential) + (threshold voltage of the transistor MQ20)]. Good, but in this case, it cannot be used with a single power supply, making it inconvenient to use.

Therefore, in this embodiment, the boot-up circuit 15 is used,
A single channel MOS structure, under a single low power supply, supplies the necessary voltage to transistor MQ8. That is, only when the high level of the selection signal is applied to the transistor MQI, the source of the transistor MQI is raised, and during that time, when the reset signal is at a high level and the inverted reset signal is at a low level, the source of the transistor MQ3 (node N4) is raised. Then, as shown in FIG. 4(K), a reset signal appears without loss.

When a reset signal of a necessary voltage is applied to the gate of the transistor MQ8, the transistor MQ8 is turned on and the terminal voltage of the capacitive element 11 becomes the reference voltage V.sub.2. after that,
When the reset signal becomes low level and the transistor MQ8 is turned off, the terminal voltage of the capacitive element 11 settles to a value lower than the reference voltage V by the level shift due to the gate-source parasitic capacitance of the transistor MQ8.

In this way, the capacitive element 11 converts the voltage at the end of the integration period, the voltage ef equal to the reference voltage V, and the level shift due to the parasitic capacitance between the gate and source of the transistor MQ8 from the reference voltage V to the voltage at the end of the integration period. Three levels of the drawn voltage are taken, and these appear as sections 1 to 2 on the video line, as shown in FIG. 4(L). Therefore, by externally detecting the potential difference between section (2) and section (2), it is possible to accurately detect the pixel information accumulated within the integration period.

〔Effect of the invention〕

As explained above, according to the solid-state imaging device of the present invention,
Since the integration period in each photodiode is the same, no external level correction is required.

Further, since a capacitive element is provided for each photodiode and the terminal voltage of the capacitive element, which is pixel information, is read out via the current amplification means, pixel information with high sensitivity can be obtained. Furthermore, by using a boot-up circuit, a single MOS channel structure can be achieved, resulting in lower costs and a single low power source drive.

5 is a diagram for explaining the reset circuit 15, and FIG. 6 is a circuit diagram showing a conventional solid-state imaging device.

10... Photodiode, 11... Capacitive element, 1
2... Video signal line, 13... Constant current source, 14...
・Reset circuit, 15.20... Boot-up circuit,
16...Current amplification circuit.

Patent applicant Hamamatsu Photonics Co., Ltd. Representative Patent Attorney
Yoshikima Shio for Hase
1) Tatsuya

[Brief explanation of the drawing]

FIG. 1 is a partial circuit diagram showing an embodiment of the present invention, FIG. 2 is a partial circuit diagram showing an address decoder of this embodiment, and FIGS. 3 and 4 are diagrams of this embodiment, respectively.

Claims (1)

[Scope of Claims] 1. A plurality of photodiodes into which light from a pixel to be read is incident, a plurality of capacitive elements provided for each photodiode, and each of the photodiodes and a corresponding capacitive element. A plurality of switching means are provided for each of the capacitive elements and are configured to be conductive during the information storage period, and externally output the terminal voltage value of each of the capacitive elements as pixel information based on a selection signal during a readout period after the information storage period has elapsed. a plurality of current amplifying means for outputting a plurality of current amplifying means; and a plurality of reset means provided for each of the capacitive elements and resetting the terminal voltage value of each capacitive element to a reference value based on a reset signal when the selection signal is inputted during a read period. and an address decoder that selects a desired one of the plurality of photodiodes and provides a selection signal to the corresponding current amplification means and reset means. 2. The solid-state imaging device according to claim 1, wherein the reset means and the address decoder each include a boot-up circuit.