JPH02199966A - Pulse clamp circuit - Google Patents

Abstract

PURPOSE:To reduce the low frequency noise by clamping a pedestal level of both a front porch and a back porch of a synchronizing pulse of a picture signal. CONSTITUTION:A synchronizing signal included in a picture signal inputted from a picture signal input terminal 1 is separated by a synchronizing pulse separator circuit 2 and retarded by a delay circuit 7 up to a front porch. Moreover, a delay circuit 8 retards up to the back porch of the next synchronizing pulse. The two clamp pulses are ORed by an OR circuit 9 and the result is inputted to the clamp circuit 4. The clamp circuit 4 clamps the two pedestal levels of the front porch and the back porch of the synchronizing pulse of the picture signal. Thus, even when a noise frequency deviated slightly from the frequency being an integral number of multiple of the synchronizing pulse is superimposed, the difference frequency is not converted into the low frequency noise at the clamp output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clamp circuit for image signals, and more specifically to a pulse clamp circuit that performs DC reproduction using pulses.

(Conventional technology) FIG. 3 shows an example of a conventional pulse clamp circuit.

The conventional pulse clamp circuit separates the synchronization pulse included in the image signal inputted from the image signal input connector 11 by the synchronization pulse separation circuit 12, and
st-switching. A clamp circuit 14 composed of a transistor 15 and a capacitor 14 clamps the synchronizing pulse of one image signal to the ground level.

FIG. 4 shows the phase relationship between the image signal and the clamp pulse.

(Problems to be Solved by the Invention) In the conventional pulse clamp circuit described above, the period of the clamp pulse is 15.75 KH, which is the same as the synchronization pulse of the image signal.
z (hereinafter referred to as rfuJ!), so if noise with a frequency slightly different from an integer multiple of s'H is superimposed on the image signal, the frequency of the difference between them will become low frequency noise in the clamp output. There was a drawback that the so-called low-frequency noise emphasis caused by the conversion was strong.

An object of the present invention is to provide a pulse clamp circuit in which, even when a noise frequency slightly shifted from a frequency that is an integer multiple of a synchronization pulse is superimposed, the difference frequency between them is not converted into low frequency noise at the clamp output. It is about providing.

(Means for Solving the Problems) In order to achieve the above object, a pulse clamp circuit according to the present invention includes a sync pulse separation circuit that separates a sync pulse from an image signal, and a sync pulse separated by the sync pulse separation circuit. two delay circuits that respectively delay the front porch and the back porch of the next synchronization pulse; an OR circuit that ORs the synchronization pulses of the two delay circuits; and a clamp driven by the output of the OR circuit. It consists of a circuit.

(Example) Is the drawing below? The present invention will be explained in more detail with reference to the following.

FIG. 1 is a circuit diagram showing an embodiment of a pulse clamp circuit according to the present invention.

A synchronization signal included in an image signal inputted through the image signal input terminal 1 is separated by a synchronization pulse separation circuit 2. The separated synchronization signal is delayed by the delay circuit 7 to the front porch. Further, in the delay circuit 8, the synchronization pulse is delayed until the back porch of the next synchronization pulse. These two clamp pulses are logically summed by an OR circuit 9, and then input to a clamp circuit 4 comprising a capacitor 3 and a transistor switch 5. Clamp circuit 4.

The two pedestal levels of the front porch and back porch of the synchronization pulse of the image signal are completely clamped.

FIG. 2 (al indicates an image signal, and FIG. 2(b) indicates a clamp pulse.

(Effects of the Invention) As explained above, the present invention clamps the pedestal levels of both the front porch and the bank porch of the synchronization pulse of one image signal, so that the image signal has a slight deviation from a frequency that is an integral multiple of fH. Even if a signal with superimposed wave numbers is clamped, the difference in frequency will be converted into low frequency noise.
There is an effect that there is no.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a pulse clamp circuit according to the present invention, FIG. 2 is a diagram showing waveforms of the image signal and clamp pulse in FIG. 1, and FIG. 3 is an example of a conventional pulse clamp circuit. The circuit diagram, FIG. 4, is a diagram showing waveforms of the image signal and clamp pulse of FIG. 3. 1.11... Image signal input terminal 2.12... Synchronous pulse separation circuit 3.13... Capacitor 4.14... Clamp circuit 5.15... Transistor switch 6.16... Image Signal output terminal 7.8...Delay circuit 9...OR circuit Patent applicant NEC Corporation representative Patent attorney Inoro Jusai 3rd figure 4th figure

Claims (1)

[Claims] a sync pulse separation circuit that separates a sync pulse from an image signal; two delay circuits that delay the sync pulse separated by the sync pulse separation circuit to a front porch and a back porch of the next sync pulse; and the two delay circuits. What is claimed is: 1. A pulse clamp circuit comprising: an OR circuit that ORs synchronization pulses; and a clamp circuit driven by the output of the OR circuit.