JPH02197177A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02197177A
JPH02197177A JP1019255A JP1925589A JPH02197177A JP H02197177 A JPH02197177 A JP H02197177A JP 1019255 A JP1019255 A JP 1019255A JP 1925589 A JP1925589 A JP 1925589A JP H02197177 A JPH02197177 A JP H02197177A
Authority
JP
Japan
Prior art keywords
layer
film
substrate
insulating film
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1019255A
Other languages
Japanese (ja)
Inventor
Masao Aiga
相賀 正夫
Satoru Hamamoto
哲 濱本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1019255A priority Critical patent/JPH02197177A/en
Publication of JPH02197177A publication Critical patent/JPH02197177A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PURPOSE:To manufacture a semiconductor device excellent in characteristics and small in dispersion of characteristics by a method wherein a fine crystal film is formed on an insulating film and an opening of a substrate, and the fine crystal film is selectively re-crystallized to form a flat semiconductor layer uniform in the direction in parallel with the substrate without degrading crystal grains in diameter. CONSTITUTION:A fine crystal film 13 is formed on an insulating film 7 and an opening 8 provided onto a substrate 6 though a CVD method. That is, when the film 13 is formed, the fine crystal film is uniformly formed on the insulating film 7 and inside the opening 8. And, laser rays are concentrated so as to position their focal point at a position just above the insulating film 7 and made to scan in parallel with the substrate 6 to enable only a fine crystal film 13a on the film 7 to be fused and re-crystallized. A p layer 9 is formed on a re-crystallized part 14 and a fine crystal part 13b through a liquid growth method. And, as the p layer 9 is made to grow making the re-crystallized part 14 and the fine crystal part 13b serve as nucleuses, the growth or the p layer 9 advances uniformly in parallel with the substrate and the surface of the grown p layer 3 becomes flat. As the p layer is formed flat, n flat active layer 2 uniform in a joining property throughout its whole face can be formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特lこ太陽[
aの活性層を平担で均一に、かつ、生産性よく形成でき
る方法jこ関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming the active layer of (a) flat, uniformly, and with high productivity.

〔従来の技術〕[Conventional technology]

@2図は太陽taミセル基本構造を模式的に示す概略図
である。
Figure @2 is a schematic diagram schematically showing the basic structure of solar TA micelles.

太陽電池セルItlは、活性層(2)と表面側を極(3
)および裏面側1! [14) lこより構成される。
The solar cell Itl has an active layer (2) and a pole (3) on the surface side.
) and back side 1! [14] Consists of 1 parts.

入射光tsrは活性層(2)1こ忘いて吸収され、光エ
ネルギーから電気エネルギ一番こ変換される。活性層(
21で光エネルギーから変換された電気エネルギーは、
六面側εよび裏面側電極+31.14)を通じて外部へ
出力として取り出される。
The incident light tsr is absorbed by the active layer (2), and optical energy is first converted into electrical energy. Active layer (
The electrical energy converted from light energy in step 21 is
It is taken out as an output to the outside through the hexagonal side ε and the backside electrode +31.14).

第3図は従来の半導体装置の製造方法の一実施例を示す
。例えばProceeding of 18 th I
EEKPhotovoltaic 5pecialis
ts Conference −1985。
FIG. 3 shows an example of a conventional method for manufacturing a semiconductor device. For example, Proceedings of 18th I
EEKPhotovoltaic 5specialis
ts Conference-1985.

192頁〜【97頁記載の多結晶Si薄膜太陽電池の製
造方法を工程順に示す断面図である。
192 to 97 are cross-sectional views showing the method for manufacturing a polycrystalline Si thin film solar cell in the order of steps.

図において、(6)は金属級Si基板(以下、基板と略
す)であり、太陽を池セルfi+全体の基板であると同
時に、裏面@awでもある(第3図1a))。基板[6
) 上1c熱CVD法ニヨリ5i02膜(7)c以下、
絶縁膜と呼ぶ)を形成する(第3図1bl )。これは
活性層121の特性に悪影響を及ぼす基板(6)からの
不純物拡散を防ぐためのものである。ただし、絶縁膜1
71は1電性をもたないので、選択エツチング1こより
絶縁膜17+の一部に開口部(8)を設け、活性層(2
)と基板(6)との電気的接続がとれるようにする(第
3図1hl)。開口部(8)の基板(6)からは不純物
拡散がおこるので、開口部の数・大きさは必要1に4\
限lことどめる。この実施例では、口径200μmの円
形開口部を、隣接開口部間距離2mmで形成される。
In the figure, (6) is a metal-grade Si substrate (hereinafter abbreviated as "substrate"), which is the substrate of the entire solar cell fi+ and is also the back surface @aw (FIG. 3 1a)). Substrate [6
) Upper 1c thermal CVD method Niyori 5i02 film (7)c below,
An insulating film) is formed (FIG. 3 1bl). This is to prevent impurity diffusion from the substrate (6) that would adversely affect the characteristics of the active layer 121. However, insulating film 1
Since the active layer 71 does not have a single conductivity, an opening (8) is formed in a part of the insulating film 17+ by selective etching.
) and the board (6) (FIG. 3, 1hl). Since impurity diffusion occurs from the substrate (6) in the opening (8), the number and size of the openings should be 1 to 4.
I'll stop it for a while. In this example, circular openings with a diameter of 200 μm are formed with a distance of 2 mm between adjacent openings.

絶縁膜171上8よび開口部(8)の基板(6)上に液
相成長法によりp型多結晶Si層(以ド、p層と略す)
(9)を形成する(第3図1hl〜Igl )。多結晶
Siは、基板(6)上では成長しやすいが絶縁膜17)
上では成長しにくい。従って、まず間口部(8)を埋め
、その後横方向にも広がって絶縁膜17)をおおうよう
な成長をする。このため、成長後のp層(9)の表面に
は大きな凹凸が生じる。次いで、p層(9)上にプラズ
マCVD法によりn型微結晶Si層c以下、n層と略す
)αQを形成する(第3図1hl )。この実施例にお
いては、このp層(9) $5よびn層QQが活性層(
2目こ相当する。p層(9)またはn層αQで吸収され
た入射光+51の光エネルギーによって、光励起キャリ
ア(電子と正孔)が発生する。そして、p層(9)、n
層GO間のpn接合番こより、電子はn層nc)に、正
孔はp層(9)に運ばれて電気エネルギーに変換される
A p-type polycrystalline Si layer (hereinafter abbreviated as p layer) is formed on the insulating film 171 8 and on the substrate (6) in the opening (8) by liquid phase growth.
(9) is formed (FIG. 3, 1hl to 1gl). Polycrystalline Si grows easily on the substrate (6), but the insulating film 17)
It is difficult to grow at the top. Therefore, the growth first fills the opening (8) and then spreads laterally to cover the insulating film 17). Therefore, large irregularities occur on the surface of the p-layer (9) after growth. Next, an n-type microcrystalline Si layer c (hereinafter referred to as n layer) αQ is formed on the p layer (9) by plasma CVD (FIG. 3, 1hl). In this example, the p layer (9) $5 and the n layer QQ are the active layer (
This corresponds to the second time. Photo-excited carriers (electrons and holes) are generated by the optical energy of the incident light +51 absorbed by the p-layer (9) or the n-layer αQ. And p layer (9), n
From the pn junction between the layers GO, electrons are transported to the n layer (nc) and holes are transported to the p layer (9), where they are converted into electrical energy.

n層(10上にスパッタリング法によりITO(Inと
Snの酸化物) / 5nOt透明21E電膜(以下、
透明電極と略す)Oυを形成する(第3図1it)。こ
の透明電極θυは表面側電極(3)の一部であると同時
に、反射防止膜としての役割ももっている。最後に、透
明a極0])上に電子ビーム蒸着法によりAg/Ti金
属電極膜C以下、金属!極と略す) 02をパターン形
成する(第3図り))。透明を極0υおよび金属電極Q
2は表面@電極(3)として作用する。
ITO (oxide of In and Sn) / 5nOt transparent 21E film (hereinafter referred to as
A transparent electrode (abbreviated as "transparent electrode") is formed (FIG. 3, 1it). This transparent electrode θυ is a part of the front side electrode (3) and also has the role of an antireflection film. Finally, an Ag/Ti metal electrode film C is formed on the transparent a-pole by electron beam evaporation. (abbreviated as pole) 02 is patterned (third diagram)). Transparent pole 0υ and metal electrode Q
2 acts as a surface@electrode (3).

以上の工程により、この実施例による半導体装置の製造
方法を用いた多結晶St薄膜太陽電池セルIl+が形成
される。
Through the above steps, a polycrystalline St thin film solar cell Il+ is formed using the method of manufacturing a semiconductor device according to this embodiment.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

m記従来の半導体装置の製造方法を用いた多結晶St薄
膜太陽電池セル川用は、絶縁膜17)上および開口部(
8)の基板(6)上に直接p層(9)が形成されるが、
p層(9)の材料である多結晶Siは、開口部(8)の
基板(6)上では成長しやすく、絶縁膜17)上では成
長しにくいので、前述のように表面の凹凸の大きなp層
(9)が形成される。このよう(こ表面の凹凸の大きな
p層(9)上にn層Qlを形成してできる活性層(2)
は、その接合特性が基板に対して平行方向5こ分布をも
つ不均一なものとなり、p層(9) ′s3よび1層α
0を最適な膜厚に形成することが非常に困難である。ま
た、n層αq、透明電極0υを形成した後も表面の凹凸
が残り、金属電極O″4の線幅・縁高の−様なパターン
形成が困難である。
For the polycrystalline St thin film solar cell using the conventional semiconductor device manufacturing method, the insulation film 17) and the opening (
A p layer (9) is formed directly on the substrate (6) of 8),
Polycrystalline Si, which is the material of the p-layer (9), grows easily on the substrate (6) in the opening (8) but does not grow easily on the insulating film 17). A p-layer (9) is formed. Active layer (2) formed by forming n-layer Ql on p-layer (9) with large surface irregularities like this
The bonding characteristics are non-uniform with a 5-layer distribution in the parallel direction to the substrate, and the p layer (9)'s3 and the 1 layer α
It is very difficult to form 0 to the optimum thickness. In addition, even after forming the n-layer αq and the transparent electrode 0υ, surface irregularities remain, making it difficult to form a pattern such as the line width and edge height of the metal electrode O″4.

この発明は以上のような問題点を解決するためlζなさ
れたもので、特に太wI電池の活性層lこ適した。平担
で均一な半導体層を生産性よく形成できる半導体装置の
製造方法を得ることを目的とする。
The present invention was developed to solve the above-mentioned problems, and is particularly suitable for active layers of thick-width batteries. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can form a flat and uniform semiconductor layer with high productivity.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、基板上に、選
択的に設けられた開口部を有する絶縁膜を形成し、この
絶縁膜上および開口部の基板上に半導体層を形成する半
導体装置の製造方法lこおいて、この絶縁膜上および開
口部の基板上に微結晶膜を形成する工程と、この微結晶
膜を選択的に再結晶化する工程とを含むようにしたもの
である。
A method for manufacturing a semiconductor device according to the present invention includes forming an insulating film having selectively provided openings on a substrate, and forming a semiconductor layer on the insulating film and on the substrate in the opening. The manufacturing method 1 includes the steps of forming a microcrystalline film on the insulating film and the substrate in the opening, and selectively recrystallizing the microcrystalline film.

〔作用〕 この発明によれば、基板上に形成された絶縁膜上および
開口部の基板上に微結晶膜が形成され、この微結晶膜を
選択的に再結晶化した後に、この膜上に半導体層が形成
されることとなるので、露出するほぼ全面が成長の核に
なり、半導体層は基板に対して平行方向1こ均一に形成
される。この結果、半導体層の特性は全面にわたって均
一になり、その表面は平担になる。加えて、微結晶膜を
選択的に再結晶化しであるため、活性層の粒径は確保さ
れ、損なわれることはない。従って、同じ条件で′4数
の半導体装置を形成した場合、その特性のばらつきは小
さく押えされる。
[Operation] According to the present invention, a microcrystalline film is formed on the insulating film formed on the substrate and on the substrate in the opening, and after selectively recrystallizing the microcrystalline film, the microcrystalline film is selectively recrystallized. Since a semiconductor layer is to be formed, almost the entire exposed surface becomes a growth nucleus, and the semiconductor layer is uniformly formed in one direction parallel to the substrate. As a result, the characteristics of the semiconductor layer become uniform over the entire surface, and the surface becomes flat. In addition, since the microcrystalline film is selectively recrystallized, the grain size of the active layer is maintained and is not impaired. Therefore, when four semiconductor devices are formed under the same conditions, variations in their characteristics can be kept small.

〔実施例〕〔Example〕

以下、この発明の一実施例を図番こついて説明する0 @1図はこの発明の半導体装置の製造方法の一実施例を
用いた1例えば多結晶Si薄膜太陽を池の製造方法を工
程順に示す断面図である。
An embodiment of the present invention will be explained below with reference to the drawings. 0 @1 Figure 1 shows a method for manufacturing a polycrystalline silicon thin film using an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps. FIG.

図において、Ill〜04は第2図および第3図に8い
て同一符号で示す部分と同一または相当する部分である
。□□□は絶縁膜17)上および開口部(8)の基板(
6)1番こプラズマCVD法により2000A8度に形
成されたp型機結晶Si膜(以下、微結晶膜と略す)、
a4はこの微結晶膜(至)を選択的に再結晶化した領域
である(以下、再結晶化部と略す)。
In the figure, Ill-04 are the same or corresponding parts to the parts 8 in FIGS. 2 and 3 indicated by the same reference numerals. □□□ is on the insulating film 17) and on the substrate (8) in the opening (8)
6) p-type machine crystalline Si film (hereinafter abbreviated as microcrystalline film) formed at 2000A8 degrees by the first plasma CVD method;
A4 is a region where this microcrystalline film is selectively recrystallized (hereinafter abbreviated as recrystallized region).

基板(6)上への絶縁膜(7)の形成、開口部(8)の
形成は前記従来の実施例と同様である(第1図1al〜
Ic1絶@膜17)上8よび開口部(8)の基板(6)
上にプラズマCVD法により微結晶go3(絶縁膜1二
(t3a)。
The formation of the insulating film (7) on the substrate (6) and the formation of the opening (8) are the same as in the conventional embodiments (FIG. 1, 1al to 1).
Ic1 isolation @ membrane 17) top 8 and substrate (6) of opening (8)
Microcrystalline go3 (insulating film 12 (t3a)) is formed on top by plasma CVD.

開口部(x3b) )を形成する(第1図1d))。プ
ラズマCVD法を用いれば露出する表面全面に一様な成
膜がなされる。これ−こより微結晶膜03を形成すれば
、絶縁膜17)上および開口部(8)1こ一様に微結晶
膜(至)か形成される。微結晶I11!(2)の形成は
、p層(9)形成の際に成長の核となる程度の膜厚が得
られれば十分である。
An opening (x3b) is formed (FIG. 1 1d)). If the plasma CVD method is used, a uniform film can be formed over the entire exposed surface. If the microcrystalline film 03 is formed from this, the microcrystalline film is formed uniformly over the insulating film 17) and the opening (8). Microcrystal I11! For the formation of (2), it is sufficient to obtain a film thickness that can serve as a growth nucleus when forming the p layer (9).

微結晶膜03はこのままでは粒径か北常に小さい。As it is, the grain size of the microcrystalline film 03 is always small.

何の処理も施さずにこの微結晶膜01上にp層(9)を
形成すると、p層(9)は微結晶膜(至)を核として成
長するので、p層(9)の粒径も小さくなる。粒径が小
さいと、結晶粒界に郭けるキャリアの再結合が増え、光
励起キャリアの効率のよい取り出しができなくなる。p
層(9)の粒径を確保するためには、その核となる微結
晶膜a葎の粒径を大きくする必要がある。この実施例に
2いては、微結晶膜(至)をレーザアニールにより溶融
し、再結晶化することで粒径を大きくしている。ただし
、開口部(8)の微結晶膜(13b)については、溶融
番こ伴う高温が基板(6)からの不純物拡散を助長する
ことになる。このことを考慮に入れ、溶融・再結晶化は
絶縁膜171上の微結晶膜(1ab)については行うが
、開口部(8)の微結晶膜(t:(a) lこついては
行わないC以下、1t3b)を微結晶部と呼ぶ)。絶縁
膜+71の直上の高さが焦点になるようにレーザを集光
し、基板(6)Iこ平行にレーザを走査して絶縁1[1
71上の微結晶膜(t3a)のみを溶融・再結晶化する
(@1図1el)。
If a p-layer (9) is formed on this microcrystalline film 01 without any treatment, the p-layer (9) will grow using the microcrystalline film (to) as a nucleus, so the grain size of the p-layer (9) will be will also become smaller. If the grain size is small, recombination of carriers at grain boundaries increases, making it impossible to efficiently extract photoexcited carriers. p
In order to ensure the grain size of the layer (9), it is necessary to increase the grain size of the microcrystalline film a, which forms the core thereof. In this Example 2, the grain size is increased by melting the microcrystalline film by laser annealing and recrystallizing it. However, for the microcrystalline film (13b) in the opening (8), the high temperature associated with melting promotes impurity diffusion from the substrate (6). Taking this into consideration, melting and recrystallization are performed on the microcrystalline film (1ab) on the insulating film 171, but not on the microcrystalline film (t: (a) l) on the opening (8). Hereinafter, 1t3b) will be referred to as the microcrystalline part). The laser beam is focused so that the height directly above the insulating film +71 is focused, and the laser beam is scanned parallel to the substrate (6).
Only the microcrystalline film (t3a) on 71 is melted and recrystallized (@1 Figure 1el).

再結晶化部αカ上詔よび微結晶部(13b)1番こ液相
成長法によりp層(9〕を形成する(第1図1h1. 
Igl )。
A p-layer (9) is formed on the recrystallized part α and the microcrystalline part (13b) by the liquid phase growth method (FIG. 1h1.
Igl).

p層(9)は再結晶化部α41i3よび微結晶部(ta
b)を核として成長するので、基板(こ対して平行方向
に均一な成長が進み、形成後のp層(9)の表面は平担
になる。
The p layer (9) has a recrystallized part α41i3 and a microcrystalline part (ta
Since it grows using b) as a nucleus, uniform growth progresses in the direction parallel to the substrate (the substrate), and the surface of the p layer (9) after formation becomes flat.

n層叫の形成、透明電極0υの形成、金属電極o諺のパ
ターン形成は前記従来の実施例と同様である(第1図1
h1. +jl )。
The formation of the n-layer layer, the formation of the transparent electrode 0υ, and the formation of the pattern of the metal electrode are the same as in the conventional embodiment described above (see FIG. 1).
h1. +jl).

p層(9)が平担に形成されたため、全面にわたって接
合特性の均一な、平担な活性層(2)が形成される。こ
れにより、p層(9)およびn層at1を最適な膜厚に
容易Iこ形成できる。
Since the p layer (9) is formed flat, a flat active layer (2) with uniform bonding characteristics over the entire surface is formed. Thereby, the p layer (9) and the n layer at1 can be easily formed to the optimum thickness.

以上の工程により、上記実施例による半導体装置の製造
方法を用いた多結晶Si薄膜太陽電池セル11.1が形
成される。
Through the above steps, a polycrystalline Si thin film solar cell 11.1 is formed using the semiconductor device manufacturing method according to the above embodiment.

な8、上記実施例では絶縁膜上および開口部の露出する
全面上に微結晶膜を形成する方法を示したが、絶縁膜上
および開口部の基板上のみに微結晶膜を形成してもよい
。また、上記実施例では、絶J1[上の微結晶膜につい
ては全て再結晶化する方法を示したが、絶縁膜上の微結
晶膜についても一部のみを選択的に再結晶化してもよい
8. In the above example, a method was shown in which a microcrystalline film was formed on the insulating film and the entire exposed surface of the opening, but it is also possible to form the microcrystalline film only on the insulating film and the substrate in the opening. good. In addition, in the above embodiment, a method of recrystallizing all of the microcrystalline film on the insulating film may be selectively recrystallized. .

また、上記実施例では、多結晶Si薄膜太陽電池の製造
に利用した場合を示したが、基板と基板上に選択的に設
けられた開口部を有し形成され1こ絶縁膜と、この絶縁
膜上および開口部の基板上に形成された半導体層とを含
む半導体装置ならば、この発明Iこおける半導体装置の
製造方法を利用することができる。
In addition, in the above embodiment, a case where it is used for manufacturing a polycrystalline Si thin film solar cell is shown, but an insulating film formed with a substrate and an opening selectively provided on the substrate, and an insulating film formed with an opening selectively provided on the substrate, The method of manufacturing a semiconductor device of this invention I can be used for any semiconductor device including a semiconductor layer formed on a film and a semiconductor layer formed on a substrate in an opening.

例えば、三次元集積回路などの活性Si層をこの発明に
よる方法によって形成できることは明らかである。
It is clear that active Si layers, such as for example three-dimensional integrated circuits, can be formed by the method according to the invention.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、基板上に形成された絶縁膜上Sよび
開口部の基板上に微結晶膜を形成し、この微結晶膜を選
択的に再結晶化した後に、この膜上に半1体層が形成さ
れることとなるので、特性が基板に対して平行方向に均
一な、平担な半導体層が粒径が損なわれることなく形成
される。これにより、その後の工程を目指す通りに進め
ることができ半導体装置を特性よく、ばらつき少なく製
造することができる。
According to the present invention, a microcrystalline film is formed on the insulating film S formed on the substrate and on the substrate in the opening, and after selectively recrystallizing the microcrystalline film, half the Since a body layer is formed, a flat semiconductor layer with uniform properties in the direction parallel to the substrate is formed without loss of grain size. As a result, subsequent steps can proceed as intended, and semiconductor devices can be manufactured with good characteristics and less variation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明に係る半導体装置の製造方法を用いた
一実施例を工程順に示す断面図2第2図は太陽電池の基
本構造を模式的に示す概略図、第3図は従来の半導体装
置の製造方法を用いた一実施例を工程順に示す断面図で
ある。 図に忘いて、(2)は半導体層、(6)は基板、(7)
は絶縁膜、(8)は開口部、崗は微結晶膜、α4は再結
晶化部である。 な2、図中、同一符号は同一 または相当部分を示す。
FIG. 1 is a cross-sectional view showing one embodiment of the manufacturing method of a semiconductor device according to the present invention in the order of steps. FIG. 2 is a schematic diagram schematically showing the basic structure of a solar cell, and FIG. 3 is a conventional semiconductor device. FIG. 3 is a cross-sectional view showing an example of a device manufacturing method in the order of steps. (2) is the semiconductor layer, (6) is the substrate, (7)
(8) is an insulating film, (8) is an opening, (3) is a microcrystalline film, and α4 is a recrystallized portion. 2. In the figures, the same symbols indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)基板上に選択的に設けられた開口部を有する絶縁
膜を形成し、該絶縁膜上および上記開口部の上記基板上
に半導体層を形成する半導体装置の製造方法において、 上記絶縁膜上および上記開口部の上記基板上に微結晶膜
を形成する工程と、 該微結晶膜を選択的に再結晶化する工程と、を含むこと
を特徴とする半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, comprising forming an insulating film having an opening selectively provided on a substrate, and forming a semiconductor layer on the insulating film and on the substrate in the opening, comprising: A method for manufacturing a semiconductor device, comprising: forming a microcrystalline film on the substrate above and in the opening; and selectively recrystallizing the microcrystalline film.
JP1019255A 1989-01-26 1989-01-26 Manufacture of semiconductor device Pending JPH02197177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1019255A JPH02197177A (en) 1989-01-26 1989-01-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1019255A JPH02197177A (en) 1989-01-26 1989-01-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02197177A true JPH02197177A (en) 1990-08-03

Family

ID=11994321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1019255A Pending JPH02197177A (en) 1989-01-26 1989-01-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02197177A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283429A (en) * 1994-04-04 1995-10-27 Hitachi Ltd Method for manufacturing thin-film solar cell
JPH0936403A (en) * 1995-07-17 1997-02-07 Canon Inc Production of basic body and solar cell employing it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283429A (en) * 1994-04-04 1995-10-27 Hitachi Ltd Method for manufacturing thin-film solar cell
JPH0936403A (en) * 1995-07-17 1997-02-07 Canon Inc Production of basic body and solar cell employing it

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