JPH02196540A - Loop communication system - Google Patents

Abstract

PURPOSE:To use a MAP between a signal channel and a communication channel in common and to relieve the hardware by exchanging the data among a signal channel time slot of a frame on a transmission line, a time slot for a corresponding communication channel and a consecutive time slot for a circulating frame. CONSTITUTION:Plural stations are connected in a loop by a loop transmission line 3, communication is applied by using a circulating frame circulating the loop transmission line 3, each station is connected to communication equipments 7a-7c by the transmission line 3 and the communication is implemented by using a frame moved on the transmission line 3. Then the data is exchanged among a time slot for signal channel of a frame, a time slot for communication channel corresponding thereto and a consecutive time slot of the circulating frame. Thus, the sender side MAP and the receiver side MAP are used in common for the signal channel and the communication channel and the hardware for the MAP control is relieved.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) TECHNICAL FIELD The present invention relates to a loop communication system.

(Prior Art) As a conventional loop communication system, there is one shown in FIG. 7, for example. As shown in the figure, this loop communication system has a plurality of stations 1a, lb, lc, . . .
... are connected in a loop by the loop transmission line 3. Each station 1a, lb, lc has a transmission line 5a s
Communication device 7as 7b, 7 by 5 b s 5 c
connected to c. A circulating frame circulates on the loop transmission line 3, and each station 1a.

lb and lc communicate using this circulating frame. Communication is performed between the station 1a and the communication device 7a using frames moving on the transmission path 5a. Communication is similarly performed using frames between other stations (for example, lb) and their corresponding communication devices (for example, 7b).

For example, when sending data from the communication device 7a to the communication device 7b, the data is sent from the communication device 7a to the station 1a using a frame on the transmission path 5a, and the station 1a loads this data on a circulating frame, Send to 1b. The station 1b transmits this data to the communication device 7b using the frame on the transmission path 5b.
send to

In such a loop communication system, it is necessary to transmit data on a communication channel and a signal channel, and a method for transmitting such data is to allocate communication channels on time slots arranged in periodic frames,
Furthermore, there is a common line signaling system in which signal channels are transmitted in packets.

However, with this method, the station must interpret the contents of the signal channel and assemble packets before the signal channel is manually input to the loop transmission path, and the station must also There was a problem in that the packets output from the transmission path had to be interpreted and converted into signal channel data.

On the other hand, as one of the individual line signaling systems, a method has been proposed that does not interpret the contents of the signal channels, does not disassemble time slots that include multiple signal channels, and transfers them directly to the time slots of the circulating frames on the loop transmission path. However, as shown in Figure 7, if there are multiple stations outputting data and data buses are set in multiple locations, the communication channel where the bus is set at the station outputting data from the loop and its corresponding communication channel. Only the data of the signal channel to be transmitted must be extracted from the time slot of the circulating frame and transferred to the time slot of the frame on the transmission path, making control complicated. Another method is to disassemble the signal channel time slots in which signal channel data is collected in a frame on the transmission path, and transmit each signal channel to a separate time slot on the loop transmission path. . Using this method, the time slot data can be output as is, but in order to send the signal channel data and the communication channel data in separate time slots on the loop transmission path, it is necessary to output the frames on the transmission path and the circulating frames. There is a problem in that separate MAPs for mapping time slots are required for signal channels and communication channels, resulting in an increase in the number of nodes.

(Problem to be Solved by the Invention) In this common line signaling system in which signal channels are transmitted in packets, operations such as interpretation of the contents of signal channels and assembling and disassembling packets are required, resulting in an increase in the scale of software. was there.

In addition, in the method of transmitting the time slot of the frame on the transmission path as it is on the time slot of the circulating frame of the loop transmission path, when outputting data to multiple devices,
It is necessary to extract only the data for which the bus is set from the time slot that collects the data of the signal channel, which complicates the hardware. One possible solution to this problem is to break down the signal time slots of a frame and transmit them within the loop transmission path using separate time slots when inputting data into the loop transmission path.
It has been reported that MAPs are required for both signal channels and communication channels, increasing the amount of hardware.

The present invention eliminates the above problems, uses an individual line signaling method that allocates data for each communication channel and signal channel data one by one to the time slot of the circulating frame of the loop transmission path, and also reduces the hardware for MAP control. The purpose of the present invention is to provide a loop type communication system that can perform

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a system in which a plurality of stations are connected in a loop through a loop transmission path and communicate using circular frames circulating on the loop transmission path. Each station is connected to a communication device via a transmission path, and communicates using frames moving on the transmission path, and each station communicates with a signal channel time slot of the frame, a corresponding communication channel time slot, and the continuous time of the circulating frame. It is characterized by exchanging data between slots.

(Function) At each station, data is exchanged between the signal channel time slot of the frame on the transmission path, the corresponding communication channel time slot, and consecutive time slots of the circulating frame. MAP can be used for both signal channels and communication channels.

(Example) An example of the present invention will be described in detail below based on the drawings. 1 and 2 are block diagrams showing the configuration of a system for sending data from the communication device 7 side to the loop transmission line 3 side in FIG. 7 in the station. As shown in the figure, this system uses Erastake memory 11.4 parallel conversion manual CLK
Selector 12, signal channel time slot decomposition unit 13
, parallel-to-serial conversion output CLK selector 14, communication channel time slot stand-to-parallel converter 15, time slot manual buffer 17, input time slot counter 19, receiving side M
It consists of an AP 21, a time slot counter 23, an input buffer address switching timing generation section 25, and a selector 27.

Further, the signal channel time slot decomposition unit 13 includes a parallel-to-parallel conversion circuit 29, a parallel-to-serial conversion circuit 31, and a signal channel selector 3.
Consists of 3.

The erasure take memory 11 temporarily stores input data sent from the transmission line 5 in order to absorb the phase difference between the frame on the transmission line 5 and the circulating frame.

A 4-parallel conversion manual CLK selector 12 extracts a clock signal CLK from input data from the transmission line 5 side and sends it to a signal channel time slot decomposition section 13 and a communication channel time slot serial to parallel conversion section 15.

The signal channel time slot decomposition unit 13 decomposes the time slot data of the signal channel in the serial data sent from the erasure take memory 11, and converts the data into time slots according to the clock sent from the parallel-to-serial conversion output CLK selector 14. Send it to the human buffer 17. The communication channel time slot serial/parallel converter 15 converts the communication channel time slot data in the serial data sent from the elasticity memory 11 into parallel data and sends it to the time slot manual buffer 17 .

The time slot manual buffer 17 writes the data sent from the signal channel time slot decomposition unit 13 or the communication channel time slot serial/parallel conversion unit 15 according to the write address sent from the receiving side MAP 21, and also writes the data sent from the time slot counter 23. The data written in accordance with the read address is read out and sent to the loop transmission line 3. The input time slot counter 19 counts the clock signal CLK sent from the transmission line 5 side and gives a MAP address to the receiving side MAP 21. The receiving side MAP 21 stores data indicating the correspondence between frames on the transmission path 5 and time slots on circulating frames. In this embodiment, data indicating the correspondence is sent to the receiving side MAP 21 so that the signal channel of the frame on the transmission path and the data of the time slot of the communication channel corresponding to this signal channel are assigned to consecutive time slots on the circulating frame. remembered. The time slot counter 23 counts the loop clock CLK sent from the loop transmission line 3 and outputs the time slot manual buffer 1.
Outputs the read address of 7. The selector 27 selects the receiving side MAP 21 and the time slot counter 2 according to the command from the input buffer address switching timing generating section 25.
5 is selected to give a write or read address to the time slot manual buffer 17.

As shown in FIG. 2, the signal channel time slot decomposition section 13 includes six serial conversion circuits 29, six parallel to serial conversion circuits 31, and a signal channel selector 33. A frame moving on the transmission path 5 consists of a signal channel time slot and a communication channel time slot, as shown in FIG. The time slot for the signal channel is 8 bits, and the time slot for the communication channel is composed of 30 consecutive slots each having 8 bits (time slot 16 is not used). The signal channel time slot consists of an 8 kHz synchronization bit F1, a multi-frame synchronization bit MF, an opposing device alarm bit S, and 5 signal bits. These eight frames are periodically moved on the transmission path 5. The 8kHz synchronization bit F indicates the beginning of the frame. When the multi-frame synchronization bit MF is "0", it indicates that this is the first frame of eight frames. The signal bits include signal bits A1 to 30 corresponding to the communication channel time slots.
The A30 will be loaded every 8 frames.

No data is written in the signal time slots of the first and eighth frames, and five signal bits are loaded in the signal bits of the second to seventh frames.

The serial conversion circuit 29a of the signal channel time slot decomposition unit 13 converts the serial type 5 bits A of the second frame.
1 to A5 are converted into parallel data. Parallel to serial conversion circuit 3
1a is the parallel-to-serial conversion output CL of this parallel data.
According to the clock signal output from the K selector 14, it is converted back into a serial type and sent to the signal channel selector 33. Similarly, the parallel-to-parallel conversion circuit 29b and the parallel-to-serial conversion circuit 31b process the third frame, and similarly, the six parallel-to-parallel conversion circuits and six parallel-to-serial conversion circuits process the second to seventh frames.
The signal bits of the th frame are processed. The signal channel selector 33 selects one of the data from the parallel-to-serial conversion circuit 31g to the parallel-to-serial conversion circuit 31f and sends it to the time slot manual buffer 17.

FIGS. 3 and 4 are block diagrams showing the configuration of a system for sending data from the loop transmission line 3 side to the communication device 7 side in the station. As shown in the figure, this system includes a time slot output buffer 41, a manual CLK selector 4 for vertical-to-parallel conversion.
3. Signal channel time slot assembling unit 45, communication channel time slot parallel-to-serial conversion unit 47, parallel-to-serial conversion output CL
K selector 49, selector 51, loop time slot counter 53, selector 55, output time slot counter 57, time slot switching timing generator 59,
The signal channel time slot assembling unit 45 includes a transmitting side MAP 61, a time slot output buffer switching timing generation unit 63, and a signal channel time slot assembling unit 45, as shown in FIG. Selector 6
Consists of 9.

The time slot output buffer 41 transfers data sent from the loop transmission line 3 to the loop time slot counter 5.
Data is written in accordance with the write address sent from the transmitting side MAP 61, and data is read out in accordance with the read address sent from the transmitting side MAP 61. As shown in FIG.
Send a clock signal to 5. The signal channel time slot assembling unit 45 assembles the signal channel data read out from the time slot output buffer 41, and generates a 4-parallel conversion output C.
The clock signal is sent to the selector 51 in response to a clock signal sent from the LK selector 49.

The communication channel time slot parallel-to-serial converter 47 converts parallel type communication channel data read from the time slot output buffer 41 into serial type communication channel data. The selector 51 selects one of the output signals of the signal channel time slot assembly section 45 or the communication channel time slot parallel-to-serial conversion section in response to a command from the time slot switching timing generating section 59 and sends it to the transmission line 5 side.

The loop time slot counter 53 counts the clock signal CLK sent from the loop transmission line 3 and provides a write address for the time slot output buffer 41.

The selector 55 selects one of the output of the loop time slot counter 53 and the output of the transmitting side MAP 61 in response to an instruction from the time slot output buffer switching timing generating section 63 and sends the selected output to the time slot output buffer 41 . The output time slot counter 57 counts the clock signal CLK sent from the transmission line 5. A time slot switching timing generating section 59 generates timing for switching between a signal channel and a communication channel according to the output of the output time slot counter 57 and sends it to the selector 51 . Sending side M
The AP 61 stores data indicating the correspondence between the time slots of the circulating frames and the frames on the transmission path, and this data is read out in response to the output of the output time slot counter 57 and used as the read address of the time slot output buffer 41. Output. The time slot output buffer switching timing generation section 63 generates a timing signal for switching between writing and reading of the time slot output buffer 41 and sends it to the selector 55 .

As shown in FIG.
It consists of 7. The parallel-to-parallel conversion circuit 65a converts the signal bits A1 to A5 described above into parallel data, and the parallel-to-serial conversion circuit 67a further converts the data into serial data and sends it to the selector 69. Similarly, the parallel-to-parallel conversion circuit 65b and the parallel-to-serial conversion circuit 67b process signal bits A6 to AIO,
Thereafter, 30 signal bits A1 to A30 are processed in the same manner. The parallel-to-serial conversion circuit 67g is for timing the signal bits of the first frame,
The parallel-to-serial conversion circuit 67h is for timing the signal bits of the eighth frame.

Next, the main operations of this embodiment will be explained.

For example, a case will be described in which data is transmitted from the communication device 7a to the communication device 7b. When sending data from the communication device 7a to the station 1a, the data is sent in six frames moving on the transmission path 5a.

As shown in FIG. 6, this frame 69 consists of 30 time slots for communication channels and 30 time slots for signal channels. In the station 1a, the data loaded in the frame 69 is temporarily stored in the elastic memory 11, the signal channel time slot is decomposed by the signal channel time slot decomposition unit 13, and the communication channel time slot is subjected to communication channel time slot 4 parallel conversion. The data is converted into parallel data by the unit 15. In the time slot manual buffer 17, the signal channel data sent from the signal channel time slot decomposition unit 13 and the communication channel data sent from the communication channel time slot 4 parallel conversion unit 15 are combined once according to the write address sent from the receiving side MAP 21. written to. In this case, the corresponding signal channels and communication channels are written in consecutive time slots on the circulating frame 73 at the receiving side M.
A write address is given from AP21.

Next, the selector 27 is switched to select the output signal of the time slot counter 23, the read address is sent from the time slot counter 23 to the time slot manual buffer 17, and the time slot manual buffer 1
Data is read from 7 and written onto the circulating frame on the loop transmission line 3.

However, the circulating frame 731 on the loop transmission line 3 is the sixth
As shown in the figure, a signal channel and a communication channel corresponding to this signal channel are written in consecutive time slots.

In the station 1b, when receiving this circulating frame, the selector 55 selects the output of the loop time slot counter 53, and data is stored in the time slot output buffer 41 according to the write address sent from the loop time slot counter 53. written. When the data is written, the selector 55 is switched to select the output of the transmitting side MAP 61, a read address is given from the transmitting side MAP 61 to the time slot output buffer 41, and the data is read out. The signal channel data is then sent to the signal channel time slot assembling section 45, where time slots are assembled. Further, the communication channel data is sent to the communication channel time slot parallel-to-serial converter 47 and converted into serial type data. selector 51
selects one of the outputs of the signal channel time slot assembly section 45 or the communication channel time slot parallel-to-serial conversion section 47 in response to a command from the time slot switching timing generation section 59 and sends it to the transmission line.

Therefore, in station 1b, contrary to the case shown in FIG. 6, the signal channel data and communication channel data corresponding to each other on the circulating frame are written in consecutive areas in the signal channel time slot of the frame on the transmission path. and 3
It is moved to the area of time slots for 0 communication channels.

(Thus, according to this embodiment, data is exchanged between the signal channel time slot of a frame, the corresponding communication channel time slot, and consecutive time slots of the circulating frame. MAP and communication channel MAP can be shared, and the receiving side M
It is sufficient to have one AP and one MAP each to reduce the amount of hardware required.

[Effects of the Invention] As described above in detail, according to the present invention, data is transmitted between the signal channel time slot of a frame on a transmission path, the corresponding communication channel time slot, and consecutive time slots of a circulating frame. MAPs for signal channels and communication channels can be shared, and hardware can be reduced.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams showing the configuration of a system that transmits data from the station's transmission line to the loop transmission line, and Figures 3 and 4 are block diagrams that show the configuration of the system that transmits data from the station's loop transmission line to the transmission line. A block diagram showing the configuration of the system, FIG. 5 is a format diagram of frames on a transmission path, and FIG. 6 is an explanatory diagram of moving data from a frame on a transmission path to a circulating frame.
FIG. 7 is a schematic diagram of the loop communication system. 1a11b11c...Station 3...Loop transmission line 5 a s 5 b s 5 c...Transmission line 7
a, 7bs 7c... Communication device 13...
・Signal channel time slot decomposition unit, 15...
・Communication channel time slot tray conversion unit 17...Time slot manual buffer 21...
...Receiving side MAP 41...Time slot output buffer 45...
...Signal channel time slot assembly section 47...
...Communication channel time slot parallel-to-serial converter 61...Transmission side MAP Applicant: Nippon Telegraph and Telephone Corporation
Toshiba Corporation

Claims (1)

[Claims] A plurality of stations are connected in a loop by a loop transmission path and communicate using circular frames circulating on the loop transmission path, and each station is connected to a communication device via a transmission path and communicates using frames moving on the transmission path, A loop communication system characterized in that data is exchanged between a signal channel time slot of the frame, a communication channel time slot corresponding thereto, and consecutive time slots of the circulating frame.