JPH02196465A - Integrated optical element - Google Patents

Abstract

PURPOSE:To obtain a technology through which light emitting or photodetecting components are disposed quite densely in an element where a plurality of light emitting or photodetecting components are integrated on the same substrate by providing the second conductivity type impurity regions of the light emitting or photodetecting components each having a diode structure so that the above impurity regions are independent of each other and they are able to establish respective potential gradients individually. CONSTITUTION:A plurality of the second conductivity type impurity regions 3 are formed on a semi-insulating or the first conductivity type substrate 4 and a plurality of light emitting components 1 having a diode structure consisting of the second conductivity type semiconductor connecting to the second conductivity type impurity regions 3 and the first conductivity type semiconductor which is adjacent to the above second conductivity type semiconductor are integrated in an element. In this element, the foregoing second conductivity type impurity regions 3 are provided so that the regions are independent of each other and they are able to establish respective potential gradients individually. For example, the light emitting components 1 which are disposed in an array form are divided into two separate groups for each component and anodes in each group are connected one another for each p<+> type diffusion layer 3 which is formed at a lower part of each light emitting component 1. Then electrodes which provide electric potential from the outside for the above anodes respectively are shown at A and B. Cathodes of the light emitting components which are adjacent to the anodes are connected to one bonding pad 2 by making every two cathodes form a set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical device in which a plurality of elements are integrated on the same substrate. III.The present invention relates to a technique for providing an element structure suitable for achieving miniaturization.

[Conventional technology]

Conventionally, an element in which a plurality of diode-structured light emitting elements are integrated has been used as a light emitting device (LED), which is described in Hitachi Cable No. 5 (1985-12).
gDiode) array, one of the anode and cathode electrodes is connected to the substrate to serve as a common electrode.

The on/off state of each LED is controlled by applying a predetermined potential to the other electrode and causing current to flow. Wire bonding pads are connected to each of these independent electrodes, through which external signals are input, and LgD
The light emission pattern is controlled. An element in which such light-emitting elements are arranged in an array is a key device for improving the performance of, for example, an optical printer.

In conventional optical printers, a single beam from one laser 27 is scanned over the photoreceptor by a mirror 28 as shown in FIG. 13, but if an LED array is used as shown in FIG. Since a scanning system is no longer required, a compact and highly reliable optical printer can be realized.

By the way, in order to improve the image quality of such LED printers, it is necessary to increase the number of light emitting elements per unit length, but there is a limit to increasing the density of light emitting elements in the conventional LED play.

Figure 15(a) shows a layout diagram of an LED array according to the conventional technology.
(1)). A bonding pad 2 is connected to the upper electrode of each LED, and an on-off signal for each LED is input. In order to eliminate mutual interference between bonding wires and to secure a working space for the bonder head, the bonding pad arrangement interval must be longer than a certain length. As shown in FIG. 15(a), even if the padding pads 2 are arranged on both sides of the light emitting region 1, the arrangement period of the light emitting regions is 1. The lower limit is tt, which is half of . 15th
In the conventional structure shown in Figure (b), each light emitting element has a diode structure. The anode 15 is common to each light emitting element and is kept at a constant potential during operation.

The cathode 14 is independent for each light emitting element,
A predetermined potential is applied to the light emitting element to emit light.

In order to make any light-emitting element emit or not emit light in a device in which light-emitting elements having such a structure are arranged in an array, one bonding pad is required for each light-emitting element. The upper limit of the number of light-emitting elements to be arranged per unit length has been limited by the minimum required spacing for arranging the pads.

FIG. 16 shows an example in which a single LED is formed on an 81 substrate. Comparing this with FIG. 15, the p region and n region are upside down, but both have in common that the LED is formed in a direction perpendicular to the substrate. 16th
A feature of the figure is that the cathode 14 is connected to the drain 6 of a MOS transistor formed on the same Sl substrate.

For this reason, the ON/OFF control of the LED is not directly controlled via the bonding wire (it can be controlled by the voltage applied to the gate 7 of the MO 89).

Therefore, when considering an element in which a plurality of light emitting elements are integrated, there is no restriction on bonding wires, so it can be said that this structure has an advantage in achieving high integration. However, FIG. 15 shows the structure of a single LED, and does not consider the case where a plurality of light emitting elements are integrated on the same substrate. Therefore, it became necessary to clarify the problems involved in integration and to clarify effective solutions.

Next, let's consider the structure of a single light emitting element. The structure of a conventional light emitting diode is described, for example, in Physics of Semiconductor Devices, 2nd edition, pages 702 to 703.
Devices, John Wiley & 5o
ns, NY, USA 1981), one of seven nodes or cathode electrodes is connected on the light emitting surface. Au-based alloys are generally used for this electrode material. Since this metal-based electrode does not transmit light in the visible to infrared region, the light emitted below the electrode does not contribute to effective light emission. In other words, since a portion of the actual light emitting surface is hidden by the electrode,
There is a problem that the effective light emitting area becomes small. Also, in order to make the light emission of the diode as uniform as possible,
It is desirable that the electrode have the same width as the light emitting part as much as possible, and this is a fundamental and contradictory problem in the structure of light emitting diodes based on surface emission.

This problem becomes more serious when arranging a plurality of devices such as a light emitting diode display. Light emitting diode arrays are, for example, Hitachi Cable No. 5, December issue 1985.
The structure is described on pages 29 to 52 of . In this case, the electrodes are connected in a rectangular region at the center of the light emitting surface, and the light emitting surface is also considerably narrowed by the electrodes.

Currently, this array is used as a light source for LED printers, but as printers become more sophisticated, arrays with higher element density are required. For that purpose, 1
One light emitting diode needs to be made compact. In this case, the aforementioned electrode problem becomes more serious. That is, in order to reduce the size of the light emitting diode and obtain the same light emitting area, it is necessary to reduce the area of the electrode connection. However, if the electrode connection portion is made smaller, it becomes difficult to maintain uniform light emission and it becomes difficult to ensure the reliability of the contact.

In this way, the light emitting diode array has a high +1! Solving this problem is essential for improving police enforcement.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the light emitting regions cannot be arranged at a distance less than a certain distance because it is necessary to ensure the distance between the bonding wires. Therefore, there is a limit to increasing the density of the light emitting regions in a device in which the light emitting regions are arranged in an array.

An object of the present invention is to provide a technique that allows light-emitting or light-receiving elements to be arranged at high density in an element in which a plurality of light-emitting or light-receiving elements are integrated on the same substrate.

Also, when considering each light emitting or light receiving element, the 15th
As shown in the figure, there is a problem in that the effective light emitting surface or light receiving surface is narrower than the actual light emitting surface or light receiving surface because the electrode covers a part of the light emitting surface or light receiving surface. This prevents high-density integration of light-emitting or light-receiving elements. Therefore, it is an object of the present invention to provide a light-emitting element having a diode structure that can expand the effective light-emitting or light-receiving area and can be integrated at high density.

[Means to solve the problem]

The above objective of high-density integration of light-emitting or light-receiving elements is achieved by independently applying a potential to the anode and cathode of each light-emitting or light-receiving element in an element in which a plurality of light-emitting or light-receiving elements having a diode structure are integrated on the same substrate. This can be achieved by making it possible to apply voltage, and it can also be achieved by forming a 1fC% electrode into a device using a conductive material that is transparent to emitted or received light.

That is, the present invention forms a plurality of second conductivity type impurity regions on a semi-insulating or first conductivity type substrate, and
In an element in which a plurality of light-emitting or light-receiving elements having a diode structure are integrated, each of which includes a second conductivity type semiconductor connected to a conductivity type impurity region and a first conductivity type semiconductor adjacent thereto, the M2 conductivity type impurity regions are independent of each other. Then, in an integrated optical element that is provided so that the potential can be set individually, and in an integrated optical element that has a plurality of light emitting or light receiving elements on the substrate, each light emitting or light receiving element The integrated optical device has electrodes of each element divided into a plurality of groups, and is provided with means for independently controlling the potential of each group.

Further, the present invention provides a light emitting or light receiving element comprising a substrate, a p-n junction layer, a contact layer and an electrode layer, in which the electrodes connected to both sides of the light emitting or receiving light are made of a material that has the ability to transmit at least the emitted or received light. Further, an integrated optical element module assembled by combining a plurality of the above-mentioned integrated optical elements, and an optical printer head using the integrated optical element or module, and those heads. It is also present in the optical printer used.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a partial plan view of an element in which a plurality of light emitting elements are integrated, and the shaded area is the light emitting region 1. In FIG.

Figure 2 is a sectional view taken along II-1' in Figure 1;
FIG. 3 is a sectional view taken along the line m-m' in FIG. 1, and shows the means of the present invention. A feature of this structure is that the cathode and anode electrodes of each light emitting element of the diode structure are electrically isolated. In this case, the substrate is a semi-insulating substrate or n-type. In the case of an n-type substrate, a voltage is applied to reverse bias the p-type region, which is the anode, and each light-emitting element has a pn
The junction is separated.

It will be explained with reference to FIG. 1 that when a structure is adopted in which both the cathode and anode of adjacent light emitting elements are electrically isolated as described above, the arrangement interval of the light emitting elements can be reduced. The light-emitting elements arranged in an array are divided into two separate groups, and the seven nodes in each group are connected to each other by a p+ diffusion layer formed under each light-emitting element, and each one is connected to each other from the outside. Let A%B be the electrode that gives the potential of . Then, the cathodes of adjacent light emitting elements are connected to one bonding pad 2 in pairs. For example, to turn on the light-emitting element (2), an appropriate bias is applied between the bonding pad (2) and the electrode (2).

In this case, it is not possible to control all the light emitting elements independently, so by opening and closing electrodes 1 and 2 in a time-division manner, light emission can be controlled in an arbitrary pattern.

In such a configuration, it is only necessary to arrange one bonding pad 2 for every two light emitting elements.If the bonding pads 2 are arranged on both sides of the light emitting element play as shown in FIG. Minimum required spacing t for placement!
A interval of 1. It can be placed in Therefore, even if conventional bonding technology is used, it is possible to achieve four times higher definition.

In addition, in an element in which both poles of adjacent diode-type light emitting elements are electrically separated from each other as shown in FIG. 2, the structure in which the lower electrode is common as shown in FIG. It is also possible to have a structure in which the lower electrode is connected to the bonding pad 2 via the p+ layer, and whether or not to emit light is controlled by the potential applied to the lower electrode. In such a structure, it is important to consider the etched mesa shape to separate the light emitting elements from each other. GaAs is one of the most important semiconductors for forming light emitting devices, but in the case of this semiconductor, (+
00) is the surface, the side surface becomes tapered by using, for example, an H, PO4 etching solution. At this time, when looking at a cross section along the (011) plane, if the angle formed by the side surface of the convex portion with respect to the substrate surface is an acute angle, that is, a normal mesa shape, as shown in Figure 5, then the (011) plane perpendicular to this (11 As shown in FIG. 6, in a cross section along the curve, the angle formed by the side surface of the convex portion with respect to the substrate surface is an obtuse angle, that is, an inverted mesa shape.

In FIG. 4, the upper pole 5 to which one pole of each light emitting element is connected extends parallel to the direction in which the light emitting elements are arranged. Therefore, by paying attention to the orientation of the substrate so that the convex portions are mesa-shaped in the direction in which the light-emitting elements are arranged as shown in FIG. 5, wiring for the upper electrode can be formed without great difficulty. This is because if the shape is a forward mesa, when metal wiring material is deposited by sputtering or the like, the wiring material can be easily deposited on the side surface of the convex portion.

On the other hand, if the substrate orientation is chosen in this way, the cross section taken in the direction perpendicular to the arrangement of the light emitting elements, that is, along the lines becomes difficult. However, since the anode located at the bottom of the diode structure is drawn out by the p+ diffusion layer,
There is no need to form wiring across this inverted mesa-shaped step. Therefore, when adopting the electrode configuration as shown in Figure 4, it is necessary to select the substrate orientation depending on the etchant used to form the convex portion, and make the mesa shape as shown in Figures 5 and 6. . The structure shown in FIG. 4 has the advantage that the potentials applied to the anode and cathode can both be supplied from the front side of the substrate, but the arrangement period of the light emitting elements is % of the arrangement period of the bonding pads. If this continues, it will not be a measure to increase the definition of elements.

7 and 8 show a structure based on the structure of the integrated light emitting device shown in FIGS. 4 to 6, which can dramatically improve the degree of integration. In the structure of FIG. 1, the degree of integration of the light emitting elements is limited by the spacing required for placement of the bonding pads. According to the structures shown in Figures 1 to 3, it is possible to achieve twice as high integration as compared to the element with the structure shown in Figure 4, but the arrangement period of the light emitting elements is still the same as the arrangement interval of the bonding pads. Because of this dependence, there was a limit to achieving even higher levels of integration.

In FIG. 7, the lower electrode of a light emitting element having a diode structure is drawn out by a diffusion layer formed on a substrate, and MOS transistors are formed on the same substrate in a one-to-one correspondence with this diffusion layer and each light emitting element. It shows the structure connected to.

If the conductivity of the semiconductor in the diode structure of the light emitting part is n-p type from above, the p-type diffusion layer for extraction is the drain 6 of the p-channel MO8 transistor, as shown in FIG. connected to. If the diode structure is p-n type from above, the n-type diffusion layer for extraction is connected to the source of the n-channel MOS transistor, as shown in FIG. 8(b).

In the case of the structure shown in FIG. 8(a), the cathodes of the diode structure are connected to each other by a common electrode as shown in FIG.
A predetermined potential is applied. (5) in Figure 9(a)
shows the configuration of the portion in FIG. 8 (=L). Light emission or non-light emission of each light emitting element is controlled by a voltage applied to the gate of a corresponding MOS transistor. (G) and (C) are a latch circuit and a data register circuit formed on the same substrate as the light emitting element and the MOS transistor. In the data register circuit, parallel human input DA from the outside
A light emission pattern of the integrated light emitting elements is determined from TAx to DATAm. The latch circuit temporarily stores the signal from the data register circuit and outputs this signal to each MO8 transistor.

If such a configuration is formed on the same substrate, the arrangement period of the light emitting elements can be significantly reduced compared to the structure shown in FIG. 15, and a high-definition element can be realized.

If the p-n type is selected from above as shown in Figure 8 (possible), the configuration will be as shown in Figure 9 (1) J.The basic configuration is Figure 9 <1
->, and detailed explanation will be omitted.

Next, to explain in detail the second half, that is, expansion of the effective light emitting area, the electrodes are made into devices using a conductive material that is transparent to the emitted light.

A typical light emitting diode structure is shown in FIG. An electrode 52 is formed below the substrate 53. This electrode may be a conventional thin metal film. Substrate 5 as required (size of electrode area)
It is preferable to provide a contact layer between the electrode 3 and the electrode 52. P-n junction layers 55a and 55b are formed on the upper surface of the substrate 53, and a contact layer 54 is formed on top of the p-n junction layers 55a and 55b. The configuration of 55 &, ssb may be upside down. The present invention consists in covering the surface of the upper layer of the contact with a transparent conductive material. Table 1 shows materials suitable for this electrode material.

First Table Materials include oxide-based and non-oxide-based compounds and metal-based thin films. In the case of a metal-based film, it is preferable that the film thickness be thin in order to obtain optical transparency. In order to obtain sufficient light transparency,
It is preferable that the film thickness is 50 nm or less. Mixed layers of metal-based materials and oxides are also suitable. A mixed layer of a metal and a dielectric material having a high refractive index is preferable as a material that takes advantage of the low resistance without overcoming the disadvantage of low transparency of metal-based materials.

For example, In402+Sn, In2O3+W,
In2O3+Mo, 5nO1+8b, ZnO+
At etc. Further, a composite oxide, which is a combination of oxides, is suitable. For example, In1O1+5nO1(
ITO), In2O3+CdSnO4, In2O3+
Examples include ZnO3. In addition, 8nO1+-F, In2O3+F, 8nO1+F fully doped with fluorine or arsenic
, ITO+F.

There are 8nO + As, etc.

FIGS. 22 and 23 show a typical structure when light emitting diodes are arranged in a p-array using stiff transparent conductive materials as electrodes. FIG. 22 shows the play structure seen from above in the light emitting direction, and FIG. 23 shows one of the light emitting diodes seen from the side. A transparent electrode 51 is formed on the top layer of each light emitting diode, and the electrode is connected to an electrode band portion 528. The pad section is connected by wire bonding to a transistor that turns the light-emitting diode on and off. The other electrode is the substrate 53
It is formed at the bottom and serves as a common electrode for all diodes. In this structure, the entire surface of the p-n junction layer becomes the light emitting surface, so the light emitting surface is wider than the conventional one. If the pn junction emits light with the same luminous efficiency as the conventional one, the area of the conventional electrode can be made smaller to obtain the same luminous intensity.

Furthermore, in the conventional case, even a portion that is hidden by the electrode and does not appear to emit light generates heat at the pn junction, and that heat must be dissipated.

Therefore, according to the present invention, it is possible to produce a light emitting diode that has the same light emission intensity as the conventional light emitting diode and generates less heat. This is a great advantage when arranged in a play. Heat generation associated with higher array density leads to deterioration of diode characteristics.

Therefore, how to dissipate this heat and how to suppress heat generation are important issues. From this point of view, the present invention has the great advantage of being able to reduce the amount of heat generated with substantially the same emission intensity.

This problem of heat dissipation becomes more effective when combined with the use of the substrate 1si. Sl has a higher thermal conductivity than general compound semiconductors, so it has a large heat dissipation effect.

Therefore, by forming the light emitting diodes of the present invention on an 81-layer substrate, it is possible to further increase the density of the array.

FIG. 24 is an example in which the electrode structure of the present invention and the back electrode are formed on the same side of the substrate. In this case, the transparent electrode is connected to the common
It can be wired as an electrode.

Further, when using Sl as a substrate, either electrode is connected to a control transistor formed in the 81 substrate.

As a result, there is no need for wiring by wire bonding, and the pad portion 528 is no longer necessary, so that the overall density can be increased.

Although all of the above has been described as a light-emitting element or a light-emitting element, if the light-emitting element or light-emitting element is replaced with a light-receiving element or a light-receiving element, the present invention can be directly applied to a light-receiving element or a light-receiving element.

[For production]

In a device in which multiple light emitting elements with a diode structure are integrated on the same substrate, the cathodes and anodes of adjacent light emitting elements are electrically isolated.
It becomes possible to apply a potential to each independently. Here, the cathode and anode of each light emitting element are divided into appropriate groups, one electrode is formed in each group, and by connecting a specific electrode to the nine fixed electrodes, any light emitting element can be selected. Can be done. This makes it possible to reduce the number of bonding pads formed on the element to control whether the light emitting element emits light or not, and it is possible to achieve higher integration and higher definition of the element.

At this time, it is important to make sure that the side surfaces of the mesa-shaped protrusions that become the light-emitting elements make an acute angle to the substrate, that is, to form a mesa-like shape, so that a common a-line can be easily formed in the arrangement direction of the light-emitting elements. It is.

As described above, in an element in which the cathode and anode of each adjacent light emitting element are separated from each other, a MOS) transistor for driving the light emitting element, a latch circuit, and a data register circuit are formed on the same substrate, and the MO8) transistor for the driver and the light emitting element are formed on the same substrate. It is connected to one electrode of the element via a diffusion layer formed on the substrate.

By adopting a configuration in which a signal from the data register circuit is input to the gate of the driver MO8 transistor via a latch circuit, the arrangement period of the p1 light emitting element can be significantly reduced. This is because in the conventional device, the arrangement period of the light emitting elements was determined by the minimum required interval for the arrangement of the bonding pads, but in the present invention, the light emitting elements are emitted by MOS transistors that can be arranged in high density. This is because elements can be driven.

〔Example〕

Example 1 An embodiment of the present invention will be described with reference to FIG.

FIG. 10 shows an element in which a plurality of light emitting elements are integrated. The basic configuration is the same as that in FIG. 1, with the upper electrode 1o being shared by two adjacent light emitting elements, and the lower electrode 11 being drawn out through a diffusion layer formed on a different surface of the substrate. and the lower electrode 11
are connected to the electrodes of two systems A and B, and adjacent light emitting elements are connected to different systems.

According to this configuration, by opening and closing the A%B2 system in a time-sharing manner, it is possible to control whether or not any light emitting element emits light. Since only one bonding pad is required for two light emitting elements, it is possible to achieve twice as high integration as in the conventional configuration shown in FIG. 15. A feature of FIG. 10 is that every other light emitting element is arranged in a different manner. When an integrated light-emitting element divided into two systems is used as a light source for a printer, when the two systems of light-emitting element arrays are controlled in a time-sharing manner, the photosensitive drum is rotating, so there is a difference between each system. The dot position is shifted. If the time division interval is tls and the peripheral speed of the photosensitive drum is vl, then the dot deviation between each system is vlx
It becomes tl. Therefore, in advance, set the luminescent elements of each system to vl.
By arranging the dots at an interval of xtl, misalignment of the dots can be eliminated.

Embodiment 2 A second embodiment of the present invention is shown in FIG. This embodiment is a modification of the structure shown in FIG. Two systems of upper electrodes are provided, and adjacent light emitting elements are connected to the upper electrodes of different systems. The lower electrode has two adjacent light emitting elements in common.
As shown in the figure, it is connected to one electrode of the MOS transistor via a diffusion layer formed on the substrate.

FIG. 18 shows the overall structure of the device based on this structure. The method of driving the light-emitting elements Fi is the same as in the case of FIG. 1, in which the upper electrodes of two systems are controlled in a time-division manner, and the light-emitting elements within each system are controlled by MOS transistors. According to this structure, the light emitting elements can be arranged at a period of h, which is the minimum period required for the arrangement of MOS transistors, and an element with a higher N-thinness than the structure shown in FIG. 7 can be realized.

Example 3 A third example of the present invention is shown in FIG. This structure is a combination of FIGS. 10 and 11, and is characterized by high integration of light-emitting elements and the ability to correct deviations between adjacent dots through time-division control.

FIG. 19 shows the manufacturing process of the device described in the present invention. P++ semiconductor regions separated from each other are formed on a semi-insulating or n-type semiconductor substrate, and a light emitting layer is deposited. After processing the light emitting layer to match the p+ type region formed on the substrate, depositing a protective film, and opening a contact window,
Form wiring.

FIG. 20 shows a manufacturing process of an element in which a MOS transistor and a light emitting section are formed on the same substrate. First, a MOS (MOS) transistor is formed on the semiconductor substrate before the wiring process,
Cover with a protective film. Next, a light emitting element array is formed in the formation region of the light emitting part by the same procedure as shown in FIG. 19, and finally, wiring for the MOS transistor and the light emitting part is formed.

Embodiment 4 A fourth embodiment of the present invention is shown in FIG. The structure shown in FIG. 21 was fabricated by molecular beam epitaxy.

As the substrate 52, an n-GaAs substrate was used. n-type semiconductor layer 551) K is n-G&ALkB, p-type semiconductor layer 55a
p-GaA8B was formed. Emission wavelength is 780
The At composition was selected to be .nm. B for p-type dopant
e.

Using f′isi as the n-type dopant, −
It was evaporated and doped using a cell. The upper contact layer is a p'' GaALAs layer, and the upper layer is In3.
03+ SnO, (I'l'O) was formed by vacuum evaporation.

Further, as a back electrode, a two-layer metal film of Cr/Au was deposited in the same manner. For comparison, a light emitting diode was also prototyped in which the upper electrode was a metal film similar to the back electrode and a contact point was provided at a 30% area ratio in the center. Emission intensity is compared relative to the intensity height of the emission spectrum. the result,
It was found that the light emitting intensity from the light emitting diode provided with the ITO electrode was clearly higher than that of the conventional type.

When this light emitting layer was formed by MOCVD, similar dependence of the light emitting intensity on the electrode material was observed.

Example 5 A fifth example of the present invention will be described. 1) A light-emitting layer having an -n junction and a contact skin are coated in liquid phase bitaxy (LPE).
). In this case, p-G on p-GaAs
aA! A8/n-GaAtk8/n”GaAAA
s, an ITO1 electrode was formed on the top by vacuum evaporation, and an Au/Cr two-layer electrode was formed on the back by vacuum evaporation.

As a result, as in Example 2, good light emission was observed.

Furthermore, we fabricated an array with a mesa-shaped light emitting part.9.

The dimensions of the light emitting part of the array are 44 x 55 μm, and the density is 4
00 dots/inch.

As a result of forming an ITO electrode in this shape and examining its luminescence intensity, a luminescence intensity higher than that of the conventional method was obtained.

〔Effect of the invention〕

According to the present invention, in an element in which a plurality of light emitting elements having a diode structure are integrated, both the cathode and the anode of adjacent light emitting elements are electrically isolated from each other, so that each electrode can be independently potentialized. can be applied, compared to an element in which one electrode is common and the light emitting element is controlled only by the other electrode, the number of input signals from the outside can be reduced, and high integration is possible.

Also according to the invention, the diffusion layer region formed on the substrate is connected to the lower electrode of the light emitting element. Since the diffusion layer region is separated for each light emitting element, the diffusion layer can be drawn out and connected to the source or drain of a MOS transistor formed on the same substrate. Therefore, the lower electrode of the light emitting element and the MOS transistor can be connected without using wiring.

If a data register and a latch circuit that generate a signal to be applied to the gate of a MOS transistor are formed on the same substrate, the number of signals input to the device can be significantly reduced, and the degree of integration of the device can be greatly improved.

Further, according to the present invention, the effective luminous efficiency of the light emitting diode is increased, and high definition of the LED array for an LRD printer can be achieved. From the current 400 DpI to the next generation 600
This is a technology that can support higher density LED arrays to Dp1 or higher.

[Brief explanation of the drawing]

FIG. 1 is a plan partial configuration diagram showing an embodiment of the present invention, wc2
The figure is a sectional view taken along the line n-n' in Figure 1, and Figure 3 is a cross-sectional view along the line n-n' in Figure 1.
1-I[[' in the figure, FIG. 4 is a plan partial configuration diagram showing an embodiment of the present invention, and FIG.
-v+' cross-sectional view, Figure 6 is ■-x■' in Figure 4.
FIG. 7 is a plan partial configuration diagram showing an embodiment of the present invention, and FIG. 8 (a) (1)) is a cross-sectional view along the
9(a) and 9(b) are circuit diagrams showing an embodiment of the present invention, FIGS. 10 to 12 are plan partial configuration diagrams showing an embodiment of the present invention, and FIG. 15 14 is a diagram showing the structure of an optical printer with a conventional structure, FIG. 14 is a diagram showing the structure of an optical printer using an element to which the present invention is applied, and FIG. 15(a)
is a partial plan view of an integrated optical device with a conventional structure;
Figure 5 (1)) is a cross-sectional view taken along line A-A' in Figure 15 (a), Figure 16 is a cross-sectional view of an element that combines a single LED and a MOS transistor according to a conventional structure, and Figure 17 is a cross-sectional view of Figure 14. FIG. 18 is a circuit diagram showing the configuration used in FIGS. 11 and 12, and FIGS. 19 and 20 are diagrams showing an optical system used in an optical printer according to the present invention. 21 is a cross-sectional view showing the structure of a light emitting diode, FIG. 22 is a planar partial configuration diagram of light emitting diodes arranged in an array, FIG. 23 is a cross-sectional view of FIG. 22, and FIG. FIG. 3 is a cross-sectional view of diodes arranged in an array. 1... Light emitting area, 2... Ponding pad, 3...
...p-type region, 4...substrate, 5...upper electrode, 6.
...Drain, 7...Gate, 8...Source, 9.
...MOS. 51... Transparent electrode layer, 52... Electrode layer, 53...
Substrate, 54--Contact layer% 55a... P-type semiconductor layer, ssb... N-type semiconductor layer, 56... Insulating layer Patent applicant Hitachi, Ltd.

Claims (1)

[Claims] 1. A second conductivity type semiconductor in which a plurality of second conductivity type impurity regions are formed on a semi-insulating or first conductivity type substrate and connected to the second conductivity type impurity regions; In an element in which a plurality of light emitting elements having a diode structure are integrated, each of which has a first conductivity type semiconductor adjacent to the first conductivity type semiconductor, the second conductivity type impurity regions are independent from each other and are provided so that a potential can be set individually. An integrated optical device characterized by: 2. In an integrated optical device having a plurality of light emitting elements on a substrate, each electrode of each light emitting element is divided into a plurality of groups, and a means is provided for independently controlling the potential of each group. An integrated optical device featuring: 3. An integrated optical device according to claim 1 or 2, characterized in that FETs for driving light emitting elements are integrated on the same substrate. 4. An integrated optical device according to claim 3, characterized in that a latch circuit for controlling a signal applied to the gate of a light emitting element driving FET and a data register circuit are integrated on the same substrate. 5. In the integrated optical device according to claim 1, the light emitting element is an LED (Light Emitting Diode).
An integrated optical device characterized by: 6. The integrated optical device according to claim 1, wherein the light emitting element is an LD (Laser Diode). 7. The integrated optical device according to claim 1, further comprising means for dividing the plurality of integrated light emitting elements into several groups and controlling each group by time division. . 8. In the integrated optical device according to claim 1, a plurality of light emitting elements are arranged in an array, and the side surfaces of the convex light emitting elements perpendicular to the array arrangement are mesa-shaped and parallel to the array arrangement. An integrated optical device characterized in that the substrate orientation is selected so that the side surface has an inverted mesa shape. 9. The integrated optical device according to claim 1, characterized in that the integrated optical device uses a silicon substrate on which a compound semiconductor of groups III to V of the periodic table is deposited. 10. In the integrated optical device according to claim 3, a substrate in which compound semiconductors of Groups III to V of the periodic table are deposited on a silicon substrate is used, the FET is placed on the silicon substrate, and the light emitting element is placed on the silicon substrate.
An integrated optical device characterized in that it is formed of a III-V group compound semiconductor. 11. An integrated optical device according to claim 10, characterized in that a latch circuit and a data register circuit are formed on a silicon substrate. 12. A plurality of second conductivity type substrates on a semi-insulating or first conductivity type substrate.
a second conductivity type semiconductor forming a conductivity type impurity region and connected to the second conductivity type impurity region; and a first conductivity type semiconductor adjacent thereto;
In an element in which a plurality of light-receiving elements having a diode structure made of a conductive semiconductor, that is, PDs (Photo Diodes) are integrated, the second conductive type impurity regions are independent from each other and are provided so that a potential can be set individually. An integrated optical device characterized in that: 13. The integrated optical device according to claim 12, wherein the FET for driving the light receiving element is integrated on the same substrate. 14. In the integrated optical device according to claim 13, a substrate is formed by depositing a compound semiconductor of groups III to V of the periodic table on a silicon substrate, the FET is placed on the silicon substrate, and the light-receiving element is formed of a compound semiconductor of groups III to V of the periodic table. An integrated optical device characterized in that it is formed by. 15. A light emitting element comprising a substrate, a pn junction layer, a contact layer and an electrode layer, wherein the electrodes connected to both sides of the light emitting element are made of a material that has the ability to transmit at least the emitted light. 16. The light-emitting device according to claim 15, characterized in that the light-emitting device uses a substrate in which a III-V group compound semiconductor of the periodic table is deposited on a silicon substrate. 17. The light emitting device according to claim 15, wherein the electrode material is an oxide. 18. The light emitting device according to claim 15, wherein the electrode material is a metal or alloy film with a thickness of 30 nm or less. 19. A light receiving element having a similar structure to the light emitting element according to any one of claims 15 to 18. 20. The light receiving element according to claim 19, characterized in that a layer having an impurity concentration lower than that of the p layer or the n layer is provided between the p-n junction layer, the p layer and the n layer. 21. An integrated optical element module, characterized in that a plurality of integrated optical elements according to claim 1 or 12 are combined and assembled. 22. An integrated optical element module comprising a plurality of integrated optical elements according to claim 3 or 13 combined and assembled. 23. An integrated optical element module comprising a plurality of integrated optical elements according to claim 8 combined and assembled. 24. The integrated optical element module according to any one of claims 21 to 23, characterized in that an element having the structure according to any one of claims 15 to 20 is used as the light emitting element or the light receiving element. Integrated optical element module. 25. The integrated optical device according to claim 1, which has 400 DpI (
1. A head for an optical printer, characterized in that it uses an integrated optical element having a dot density of at least 100 dots per inch. 26. An optical printer head characterized by using the integrated optical element module according to any one of claims 21 to 24. 27. An optical printer head constructed by hybridly integrating the integrated optical element according to claim 1, a latch circuit and a data register circuit formed on separate substrates on one mounting substrate. 28. An optical printer using the optical printer head according to any one of claims 25 to 27.