JP2784010B2 - Self-scanning light emitting element array - Google Patents

Abstract

PURPOSE:To simplify manufacturing steps by connecting second conductivity type semiconductor control electrodes in contact with first conductivity type semiconductor of a light emitting element to which a bias voltage is applied therebetween by resistance elements. CONSTITUTION:Assume that a transfer clock phi3 shows a high level and a light emitting thyristor T(0) is turned ON. In this case, the base of an NPN transistor Tr 2 (0) is set to a potential at which ON current of the T(0) can flow, this potential is transmitted to the bases of NPN transistors Tr2(-1), Tr2(1) of the adjacent T(-1), T(1) through a connecting resistor RL, and the base currents flow. Next clock pulse phi1 of the pulse phi3 is applied to the T(1), T(-2). Since the ON voltages respectively attain the values of ON voltage Vs(1), Vs(-2), if the high level voltage of the clock pulse is set between the ON voltages Vs(1) and Vs(-2), only the T(1) can be turned ON. If the phi1, phi2, phi3 are so set as to be superposed at the high level, the ON state light emitting elements are sequentially transferred. Thus, the light emitting element arrays are connected therebetween by the resistor to simply manufacture it in simple manufacturing steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention is, for example, integrated light emitting elements on the same substrate,
The present invention relates to providing a self-scanning function to a light emitting element array.

[Prior art]

LED (Light Emitting) is a typical light emitting element.
Diode) and LD (Laser Diode) are known. LEDs form a PN or PIN junction of a compound semiconductor (GaAs, GaP, AlGaAs, etc.) and apply a forward voltage to inject carriers into the junction and use the light emission phenomenon that occurs during the recombination process. Things. The LD has a structure in which a waveguide is provided inside the LED. When a current higher than a certain threshold current is passed, the number of injected electron-hole pairs increases to form a population inversion state, photon multiplication (gain) occurs by stimulated emission, and parallel reflection using a cleavage plane or the like. The light generated by the mirror is returned to the active layer again, and laser oscillation occurs. Then, the laser light is emitted from the end face of the waveguide. As a light emitting element having the same light emitting mechanism as these LEDs and LDs, a negative resistance element (light emitting thyristor, laser thyristor, etc.) having a light emitting function is also known. The light-emitting thyristor is a compound semiconductor having a PNPN structure as described above, and has been practically used as a thyristor in silicon (see “Light-emitting Diode” Industrial Research Committee, edited by Shoji Aoki, pp. 167-169). The basic structure and current-voltage characteristics of this light emitting thyristor are shown in FIG. 9 and FIG. The structure shown in FIG. 9 is an N-type GaAs
It has a PNPN structure formed on a substrate and has exactly the same structure as a normal thyristor. FIG. 10 also shows the same S-shaped negative resistance as that of a normal thyristor. As the thyristor, not only the two-terminal thyristor shown in FIG. 9 but also a three-terminal thyristor shown in FIG. 11 is known. The gate of the three-terminal thyristor has a function of controlling the ON voltage, and the ON voltage is a voltage obtained by adding a diffusion potential to the gate voltage. After being turned on, the gate electrode becomes substantially equal to the cathode potential. If the cathode electrode is grounded, the gate electrode will be at zero volts. Further, it is known that the threshold voltage of the light emitting thyristor is lowered when light is incident from the outside. Furthermore, a laser thyristor can be formed by providing a waveguide in this light-emitting thyristor and using the same principle as that of an LD (Tashiro et al., 1987 Autumn Applied Physics Conference lecture, number 18p-ZG).
-10). A large number of such light-emitting elements, particularly LEDs, are manufactured on a compound semiconductor substrate, cut, packaged as individual light-emitting elements, and sold. Also, LEDs as light sources for contact image sensors and printers are sold as LED arrays in which a plurality of LEDs are arranged on one chip. On the other hand, in a contact type image sensor, an LED printer, and the like, a scanning function (light scanning function) of a light emitting point by these light emitting elements is required in order to designate a reading point and a writing point. However, in order to perform optical scanning using these conventional light emitting elements, each LED made in the LED array is connected to a driving IC by a technique such as wire bonding, and this IC is used for one-shot operation. Each LED had to be driven. For this reason, when the number of LEDs is large, the same number of wire bondings are required, and a large number of drive ICs are required, resulting in high costs. In addition, this necessitates securing a space for installing the drive IC, which has caused a drawback that it is difficult to reduce the size. Also, the pitch at which the LEDs are arranged is determined by wire bonding technology, and there is a disadvantage that it is difficult to reduce the pitch. Therefore, the inventors have made the invention to solve the above-mentioned problems of the number of wire bondings, the problem of the drive IC, the compactness, and the short pitch by giving the light emitting element array itself a self-scanning function ( Japanese Patent Application No. 63-65392,
“Light-emitting element array and driving method thereof”). The contents of the present invention will be briefly described below. The gist of the above invention is to realize a self-scanning function of light emission by configuring the turn-on voltage or current of the light emitting element to be influenced by the ON state of another light emitting element, that is, by making the light emitting element interact. is there. FIG. 12 shows a first example of the embodiment of the present invention. This uses the light-emitting thyristor described above as a light-emitting element, and is configured so that a part of generated light is incident on an adjacent light-emitting thyristor, and utilizes a phenomenon in which the ON voltage of the light-emitting thyristor containing light is reduced. Things. Now transfer clock pulse φ ₃ is at a high level, the light-emitting thyristor T (0)
Is turned on. For this reason, the ON voltages of the light emitting thyristors T (-1) and T (1) located on both sides thereof are reduced.
Thus the high level voltage becomes possible to be the T (1) only is ON applied to the next transfer clock pulse phi _1.
The self-scanning can now be performed. FIG. 13 shows the device structure of the configuration shown in FIG. N-type Ga
A light emitting thyristor composed of a P-type (23), an N-type (22), and a P-type (21) was provided on an As substrate, and a transfer clock line was connected to an electrode (40) in contact with each of the P-type (21) layers. It has a configuration. The operation is as described above. FIG. 14 shows a second example of the embodiment of the present invention. The gate terminal R _L of the three-terminal thyristor shown in FIG. 11, a configuration of connecting the R _I to each other. Now transfer clock pulses phi ₃ is a light-emitting thyristor T to the high level voltage (0) is in the ON state. In this case the node G ₀ is nearly zero volts. Then current flows from the resistor network,
The voltage of the node closest to the light emitting thyristor T (0) is reduced most, and the farther away from the node, the less the effect is. Although the next transfer clock phi ₁ to a high level voltage is applied emitting thyristor T (1) and T (-2) is enabled ON, because the more the node G ₁ is has a lower voltage than node G _-2, Only the light emitting thyristor T (1) can be turned on. The self-scanning can now be performed. FIG. 15 shows the device structure of the configuration shown in FIG. N-type Ga
A light emitting thyristor composed of a P-type (23), an N-type (22), and a P-type (21) is provided on an As substrate, and a transfer clock line is connected to an electrode (40) in contact with each P-type (21) layer. And the gate electrode (41) in contact with each N-type (22) layer
R _L and R _I are connected to each other. This operation is exactly the same as in FIG. According to the prior invention briefly described above, it has become possible to solve the problem of the number of wire bonding, the problem of the drive IC, the problem of downsizing, the short pitch, and the like.

[Problems to be solved by the invention]

12 and 13 (method by optical coupling), there is no need to provide a gate electrode, the structure is simple, and the device can be manufactured by a simple manufacturing process. However, in the configuration example shown in FIGS. 14 and 15 (method by electrical connection), it is necessary to provide a gate electrode, and it is necessary to provide resistances R _L and R _I and internally wire them to each other. The structure is relatively complicated and the manufacturing process is also complicated. For this reason, the method using electrical connection has a problem that the manufacturing cost is relatively high.

[Means for Solving the Problems]

The present invention is an improvement of the method of connection by electrical means, and enables the manufacture by simple manufacturing steps also by the method of connection by electrical means. As a means for simplifying the manufacturing method, a second conductivity type semiconductor (an N-type gate electrode in the above example) in contact with the first conductivity type semiconductor connected to the clock line of the light emitting element as shown in the example of the above invention is used. ) Are connected electrically via resistors R _L and R _I (potential coupling), and the first conductivity type semiconductor in contact with the second conductivity type semiconductor to which the bias voltage of the light emitting element is applied (the above example) In this case, the P-type gate electrodes are connected by a resistor (current inductive coupling). More preferably, the connection resistor is configured to use the gate layer (P-type semiconductor layer in the above example) of the light emitting element itself. This makes it possible to further simplify the manufacturing method. The present invention provides a large number of stacked semiconductor light-emitting elements having a control electrode for controlling a threshold voltage or a threshold current, one-dimensionally, two-dimensionally, or three-dimensionally arranged, and a control electrode of each light-emitting element. A light-emitting element array in which a control electrode of at least two light-emitting elements located in the vicinity is connected to each other by electrical means, and a network line is connected to each light-emitting element to apply a voltage or current from outside. The electrical means is such that a second conductive type semiconductor control electrode of the light emitting element which is in contact with the first conductive type semiconductor to which a bias voltage is applied is connected using a resistance element. As the stacked semiconductor light emitting device used in the present invention, a device whose threshold voltage or threshold current can be controlled from the outside, for example, a light emitting device having a negative resistance in which a plurality of P conductive semiconductor regions and N conductive semiconductor regions are stacked. Element can be used. Further, it is preferable to use the first or second conductive semiconductor layer for forming the light-emitting element as the resistance element because the manufacturing method can be further simplified.

[Action]

In the present invention, since the second conductivity type semiconductor (gate electrode) in contact with the first conductivity type semiconductor to which the bias voltage of the light emitting element is applied is connected by a resistance element, the light emitting element which is turned on is electrically connected to the semiconductor. A current flows into the connected light emitting element, which lowers the threshold voltage of the connected light emitting element by electrical means, and triggers ON state transfer (self-scanning). Further, since the second conductivity type semiconductor layer (gate layer) of the light emitting element can be used as the resistance element, a self-scanning light emitting element array can be manufactured by a simpler manufacturing process as described in detail in the embodiment. Becomes possible.

【Example】

First Embodiment FIG. 1 shows an equivalent circuit diagram of the principle of the first embodiment. This shows the case where the most standard three-terminal light-emitting thyristor is used as an example of a light-emitting element whose light-emitting threshold voltage and current can be externally controlled. Light-emitting thyristors T (-2) to T
(+2) has a configuration arranged in a line. Each light emitting thyristor is represented as a combination of transistors Tr1, Tr2. The transistor Tr1 is a PNP transistor, and the transistor Tr2 is an NPN transistor. The connection resistance _RL between the light emitting thyristors is connected between the bases of the NPN transistor Tr2. The anode electrode of each light emitting thyristor,
The three transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are sequentially and repeatedly connected. The clock line is provided with a current limiting resistor Rc for the clock line. The operation will be described. The transfer clock phi ₃ becomes the high level first, and the light-emitting thyristor T (0) is turn ON.
At this time, the base of the NPN transistor Tr2 (0) is set to a potential at which the ON current of the light emitting thyristor T (0) can flow. This potential is applied to the NPN transistors Tr2 (−) of the adjacent light emitting thyristors T (−1) and T (1) through the connection resistance _RL.
1), are transmitted to the base of Tr2 (1), and these base currents flow. However, as long as the transfer clock lines φ ₁ and φ ₂ are at a low level, the light emitting thyristors T (−1), T (
(1) remains in the OFF state. If the connection resistance _RL is small, the NPN transistors Tr2 (-1) and Tr2 (1) have the ability to flow the same current as the ON current of the light emitting thyristor T (0). However, if the connection resistance _RL is large, the base current of the NPN transistor Tr2 (-1), Tr2 (1) is controlled by the connection resistance _RL , and the NPN transistor Tr2 (-1),
The current driving capability of Tr2 (1) decreases. NPN transistor
NP located farther than Tr2 (-1), Tr2 (1))
The base currents of the N-transistors Tr2 (-2) and Tr2 (2) are further reduced, and their current driving capabilities are further reduced. It is known that when the base current amount of the NPN transistor Tr2, that is, the current driving capability increases, the ON voltage of the light emitting thyristor decreases. FIG. 2 shows this state. The horizontal axis is the anode voltage (emitter voltage of PNP transistor Tr1)
And the vertical axis is the anode current. Here, ON voltage Vs
Is the ON voltage when there is no external influence.
Vs (1) is the ON voltage Vs (−) of the light emitting thyristor T (1).
2) represents the ON voltage of the light emitting thyristor T (-2). ON
The minimum current required to maintain the state is the hold current Vh
Called. The light-emitting thyristors T (−1) and T (1) closest to the light-emitting thyristor T (0) that is turned on decrease in voltage when turned on for the reason described above, and become the ON voltage Vs (1). The next closest light-emitting thyristors T (-2) and T (2) are less affected by the base current and become the ON voltage Vs (-2). Now the next clock pulse phi ₁ clock pulse phi ₃ in Figure 1 is the light-emitting thyristor T (1), is applied to T (-2). Since these ON voltages have the values of the ON voltages Vs (1) and Vs (-2), respectively, for the reasons described above, the high-level voltage of the clock pulse is changed to the ON voltage Vs
(1) If set between Vs (-2), only the light emitting thyristor T (1) can be turned on. From now on, if the clock pulses φ ₁ , φ ₂ , φ ₃ are set so that their high levels overlap each other, the ON state light emitting elements are sequentially transferred. Thus, a self-scanning light emitting element array can be realized. As described above, in this embodiment, the resistance connecting the light emitting elements is 1
It can be seen that it can be formed by a simple manufacturing process. In the present embodiment, the operation has been described in the case where the transfer clock pulse has three phases.
Further, in FIG. 1, the light-emitting elements are arranged in a line. However, the arrangement is not necessarily linear, and the light-emitting elements may be meandered depending on the application, or may be increased to two or more lines in the middle. In this description, the light-emitting thyristor is limited, but the device is not limited to this as long as it has a similar function. As described in another embodiment of the present invention, a laser thyristor may be used as the light emitting element. In this driving method, the light emitting element may be constituted by a single component, or may be integrated by any method as shown in the next embodiment. <Embodiment 2> In Embodiment 1, an equivalent circuit is shown and described, but in Embodiment 2, a configuration in which Embodiment 1 is integrated and created will be described. The essential point of this embodiment is a structure in which a resistance element can be formed in the same process as a light-emitting thyristor by providing a connection resistor for performing electrical coupling by using a part of the light-emitting element. FIG. 3 shows a conceptual diagram of a structural cross section of the present invention. An N-type semiconductor layer (24), a P-type semiconductor layer (23), an N-type semiconductor layer (22), and a P-type semiconductor layer (21) on a grounded N-type GaAs substrate (1).
Are formed. Then, the individual light emitting elements T (-2) to T (2) are separated by photolithography or the like and etching (separation groove (50)). The N-type GaAs substrate (1) serves as the cathode of this thyristor and is grounded. P serving as the anode of each single light emitting element
Transfer clock line φ ₁ ,
φ ₂ and φ ₃ are connected every _third element. The feature of this configuration is that the P-type semiconductor layer (23) constituting the thyristor is connected through each element. The internal resistance of the P-type semiconductor layer (23) is the connection resistance _RL shown in FIG. FIG. 4 shows a schematic plan view of the structure. This is because each of the light emitting elements T (-2) to T (2) shown in FIG.
, The inner square indicates the P-type semiconductor layer (21), and the surrounding area indicates the P-type semiconductor layer (23). In this structure, a cut (55) is formed in the P-type semiconductor layer (23). This is the connection resistance described in the first embodiment.
This is for changing the value of _RL , and the larger the cut (55), the larger the connection resistance _RL . Therefore, in this embodiment, the connection resistance _RL can be freely changed and optimized, and the transfer operation can be further stabilized. The configuration of this embodiment is exactly the same as the equivalent circuit shown in the first embodiment (FIG. 1), and performs exactly the same operation. Therefore, if the high-level voltages of the transfer clocks φ ₁ , φ ₂ , φ ₃ are set so as to slightly overlap each other in order, the ON state of the light emitting thyristor is sequentially transferred. That is, the light emitting points are sequentially transferred. As described above, in this embodiment, there is no need to provide a gate electrode, and only one resistor is required to connect the light emitting elements. Further, the connection resistance _RL can be formed by a semiconductor layer forming the light emitting element. From this, it can be seen that it can be formed in a simple manufacturing process. In this embodiment, φ ₁ ,
Although three phases of φ ₂ and φ ₃ are assumed, when more stable transfer operation is required, the number of phases may be increased to four phases or five phases. In this embodiment, the structure of the light-emitting thyristor is described as being the simplest. However, introducing a more complicated structure and layer structure in order to increase luminous efficiency is also included in the scope of the present invention. A specific example thereof is the adoption of a double hetero structure. An example is shown in FIG. 16 (Tashiro et al., Lecture by the Society of Applied Physics, Spring 1987, number 28p-ZE-8). This is N-type GaAs
A 0.5 μm N-type GaAs layer is stacked on a substrate, N-type AlGaAs with a wide band gap is 1 μm, and a P-type GaAs layer is
m, N type GaAs layer 1μm, P type AlG with wide band gap
The structure is such that aAs is 1 μm, and a P-type GaAs layer for making ohmic contact with the extraction electrode is 0.15 μm. The light emitting layer is a 1 μm N-type GaAs layer interposed therebetween. The injected electrons and holes are confined in the GaAs layer having a narrow band gap, and recombine in this region to emit light. Also, here, a PNPN thyristor configuration has been described as an example, but the configuration of detecting this potential, lowering the threshold voltage, and performing a transfer operation using this is not limited to only the PNPN configuration, and its function is The device is not particularly limited as long as it can achieve the above. For example, a similar effect can be expected with a configuration having six or more layers instead of a PNPN four-layer configuration, and it is possible to achieve exactly the same self-scanning function. Further, the same is true even when a thyristor called an electrostatic induction (SI) thyristor or an electric field control thyristor (FCT) is used, and is included in the present invention. This SI thyristor or FC
T has a structure in which the central P-type semiconductor layer serving as a current block is replaced with a depletion layer (SMSze, Physic
s of Semiconductor Devices, 2nd Edition pp238-24
0). <Embodiment 3> Embodiment 3 is shown in FIG. 5 and FIG. This embodiment shows a more realistic structure of the second embodiment. FIG. 5 is a plan view of this embodiment, and FIG. 6 is a cross-sectional view taken along line XX 'of FIG. The plan view in FIG. 5 will be described. The transfer clock lines φ ₁ , φ ₂ , φ ₃ are connected to the underlying anode electrode (40) through through holes C2. This anode electrode (4
0) is connected to the P-type semiconductor layer (21a) of each light emitting element through the contact hole C1. Each light emitting element T (-2) to T
In (2), the P-type semiconductor layer (23) is drawn outside the rectangular P-type semiconductor layer (21a). This layer has a cut (55) as described in the second embodiment, and is configured so that the connection resistance _RL can be optimized. FIG. 6 is a sectional view. Light emitting element is N-type GaAs
N-type GaAs layer (24b), N-type AlGaAs layer (24a), P
GaAs layer (23), N-type GaAs layer (22), P-type AlGaAs layer (21
b), forming each layer of the P-type GaAs layer (21a). Then, they are separated into individual light emitting elements by photolithography or the like and etching (separation groove (50)). The groove (55) is a cut groove for changing the value of the connection resistance _RL . Although not shown in the cross-sectional view, the connection resistance _RL is a P-type semiconductor layer (23).
(A GaAs layer in this example). The insulating layer (30)
The anode electrode (40) is electrically separated from each semiconductor layer. As the material of the insulating layer (30), it is desirable to use a substance that does not transmit light from the present light emitting element in the sense of light separation between the light emitting elements. Alternatively, this layer may be a multilayer film including a plurality of layers, and may have an insulating function and a light separating function. However, when a light separating function is provided, it is necessary to provide a window separately so that light can be extracted outside.
The interlayer insulating layer (31) insulates and separates the anode electrode (40) from the clock line. The manufacturing process of the third embodiment will be described. First, on an N-type GaAs substrate (1), an N-type GaAs layer (24b), an N-type AlGaAs layer (24a),
P-type GaAs layer (23), N-type GaAs layer (22), P-type AlGaAs layer (21b), and P-type GaAs layer (21a) are sequentially formed. Then, a separation groove (50) is formed to separate light emitting elements. Next, a cut groove (55) is formed, and a connection resistance _RL is formed. Insulating film to form a (30), contact holes (C ₁₎ provided. An electrode (40) is formed. Forming an interlayer insulating film (31), the provided through hole C _2, the clock line electrodes φ
₁ , φ ₂ and φ ₃ are formed. Through the above steps, the structure of the third embodiment is completed. As described above, in this embodiment, there is no need to provide a gate electrode, and only one resistor is required to connect the light emitting elements. Further, the connection resistance _RL can be formed by a semiconductor layer forming the light emitting element. From this, it can be seen that it can be formed by a simple manufacturing process. The order of this step is not necessarily required to be as described above. For example, the order of forming the separation groove (50) and the cut groove (55) may be reversed. Further, a light-transmitting insulating film may be further provided on FIG. 4 to improve reliability.
Furthermore, if it is not desired that the thickness of the insulating film on the light emitting element is increased and the light transmittance is reduced, part or all of the upper insulating film of the light emitting element may be removed by a method such as photoetching. Although GaAs and AlGaAs are used here as the semiconductor layer, the present invention is not limited to this, and another semiconductor may be used. <Embodiment 4> Application to Laser In the description of the embodiments up to this point, a light emitting thyristor has been described as a light emitting element. However, the present invention is not limited to a light-emitting thyristor, and operates in exactly the same manner using, for example, a laser thyristor. A case where a laser thyristor is used in the following embodiment will be described. FIG. 7 and FIG. 8 are structural views of the fourth embodiment. This shows a case where the present invention is applied to a laser. FIG. 7 is a plan view of the fourth embodiment, and FIG. 8 is a cross-sectional view. The manufacturing method will be outlined. N-type Al on N-type GaAs substrate (1)
GaAs (25), P-type AlGaAs (24), I-type (non-doped) Ga
As (23), N-type AlGaAs (22), P-type AlGaAs (21), and upper electrode (20) are sequentially laminated (a good ohmic contact between the P-type AlGaAs (21) and the upper electrode (20)). P to do
(In some cases, a GaAs layer is interposed.) Next, the upper electrode (20) is processed into a rectangle having the same width as the width of the N-type AlGaAs layer (25) in the figure by photoetching, and the P-type Al is used as a mask.
Each layer of GaAs (21) to P-type AlGaAs (24) is etched. At this time, a separation groove (50) between the elements is formed. Next, the same upper electrode (20) is further etched by photoetching to provide a stripe pattern (current injection portion of a laser thyristor) having a width of 10 μm or less. Using this as a mask, the layer of P-type AlGaAs (21) and N-type AlGaAs (22) is etched. The N-type AlGaAs (22) layer is not removed completely but partially left. Further, a cut groove (55) is formed by photoetching. Then, an insulating film (30) is formed.
The insulating film desirably has two functions of insulation and light shielding, and may be formed using a plurality of types of films. For example, when an SiO ₂ film is used as the insulating film,
Because it transmits 870 nm, which is the emission wavelength of GaAs, there is a possibility that optical coupling will be induced, and it may be necessary to provide a light shielding film made of a light absorbing material such as amorphous silicon in the meantime. is there. Next, a contact hole (C ₁ ) is provided by photo-etching, a wiring metal for a transfer clock line is formed by vapor deposition or sputtering, and the transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are formed by photo-etching. Finally, the end face on the laser light output side is formed with good parallelism by a method such as cleavage, and the structure of this embodiment is completed. The structure of the laser is not limited to this structure,
For example, TJS type, BH type, CSP type, VSIS type, etc. may be used (of course, SMSze, Physics of Semiconductor Devic
es, 2nd Edition pp724-730). The material is also AlG
Although the explanation has been mainly focused on aAs, other materials (for example, AlGaI
nP, InGaAsP, ZnSe, etc.). Although a series of embodiments of the present invention described above use a semiconductor substrate as the substrate and set the potential to zero volt (ground), the present invention is not limited to this, and the present invention is not limited to this. May be used. Speaking of the closest example, an n-type GaAs layer corresponding to the n-type GaAs substrate of the embodiment is formed on a semi-insulating GaAs substrate doped with chromium (Cr), and the structure described in the embodiment is formed thereon. May be. Also, for example, a semiconductor film is formed on an insulating substrate such as glass and alumina,
The structure of the embodiment may be formed using this semiconductor. Further, in the configuration shown in the embodiment, even if the conductivity types P and N are reversed, the operation is exactly the same as long as the bias condition and the like are reversed, and is included in the scope of the present invention. <Application Examples> The self-scanning light emitting element array described in the above embodiments can be expected to have various applications as in the previous invention (Japanese Patent Application No. 63-65392, "Light Emitting Element Array and Driving Method Thereof"). As described in the preceding invention as an example, a contact image sensor for optical scanning, a writing head of an optical printer, a display, and the like can be cited, which can greatly contribute to lowering the price and improving performance of these devices.

【The invention's effect】

As described above, the present invention enables the light emitting element arrays to be manufactured in a simpler manufacturing process by connecting the light emitting element arrays with resistors. That is, various problems such as the problem of the number of wire bonding, the problem of the driving IC, the downsizing, the short pitch, and the like can be more easily solved. Also, the present invention provides a contact image sensor,
It can be applied to optical printers, displays, etc., and can greatly contribute to improving the performance of these devices and lowering their prices.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of the light emitting element array according to the first embodiment, and FIG.
FIG. 3 is a characteristic diagram of the light emitting thyristor, FIG. 3 is a sectional view of the second embodiment, FIG. 4 is a plan view of the second embodiment, FIG. 5 is a plan view of the third embodiment, and FIG. FIG. 7, FIG. 7 is a plan view of the fourth embodiment, FIG. 8 is a cross-sectional view of the fourth embodiment, FIG. 9 is a cross-sectional view showing a schematic structure of the light-emitting thyristor, and FIG. FIG. 11, FIG. 11 is a cross-sectional view showing a schematic structure of a three-terminal thyristor, FIG. 12 is a diagram showing the earlier invention, an equivalent circuit of a light emitting element array by optical coupling, and FIG. 13 is a diagram showing the earlier invention. FIG. 14 is a cross-sectional view showing a schematic structure of a light emitting element array by optical coupling, FIG. 14 is a diagram showing the prior invention, an equivalent circuit of the light emitting element array by potential coupling, and FIG. FIG. 16 is a sectional view showing a schematic structure of an element array, and FIG. 16 is a sectional view showing a schematic structure of a light emitting thyristor having a double hetero structure. It is a diagram.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Shuhei Tanaka 4-8 Doshomachi, Higashi-ku, Osaka-shi, Osaka Inside Nippon Sheet Glass Co., Ltd. (56) References JP-A-48-96291 (JP, A) JP-A-1 −238962 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) B41J 2/45 B41J 2/455 H01L 33/00

Claims (3)

(57) [Claims] 1. A light-emitting device comprising a first transistor and a second transistor, wherein a number of light-emitting elements are arranged one-dimensionally, two-dimensionally, or three-dimensionally. A light emitting element is connected to a clock line to which a clock pulse is externally applied, and a base of the second transistor of each light emitting element is connected to at least two light emitting elements located near a certain direction with respect to each light emitting element. And the base of the second transistor of the light emitting element in a light emitting state is connected to the base of the second transistor of the light emitting element in the light emitting state through the resistor. Being transmitted to the base, controlling the current driving capability of the transistor so that the light emitting element becomes a light emitting state when the clock pulse is applied. Characteristic self-scanning light emitting element array. 2. The light emitting device according to claim 1, wherein the light emitting device is a stacked semiconductor light emitting device in which a plurality of first conductivity type semiconductor layers and a plurality of second conductivity type semiconductor layers are stacked. 2. The self-scanning light-emitting element array according to claim 1, wherein the light-emitting element array is formed by utilizing. 3. The self-scanning light emitting element array according to claim 2, wherein said light emitting element is a light emitting thyristor, a laser thyristor, an electrostatic induction thyristor, or an electric field control thyristor.