JPH02195707A - Gain variable type amplifier - Google Patents

Abstract

PURPOSE:To prevent a gain control voltage from being outputted to a load by forming three differential amplifiers including the one for current distribution of three dual gate FETs whose characteristics are similarly arranged. CONSTITUTION:Currents divided into two by dual gate FETs 5 and 6, which constitute the differential amplifier and whose characteristics are similarly arranged, are supplied to similar FETs 1 and 2, and FETs 3 and 4 forming the similar differential amplifiers. For a gate Q1 of these FETs 2 to 4, a signal from a signal source 13 is interrupted by the filter circuit of a resistance 9 and a capacitor 10, only a bias current is supplied, a fixed bias state is prepared, the FETs 3 and 4 do not execute amplifying operation, and the signal and bias current are supplied only to the gate G1 of the FET 1. Further the outputs of the FETs 1 and 3 and the outputs of the FETs 2 and 4 are supplied to load 7, the impedance of the FET is made high, the small bias current is negligible, the current flowing through a point A of the load 7 is always at 1/2 of a current source 12, and even when the gage G of the FET 1 is controlled and the gain is controlled, the potential of the point A does not fluctuates.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable gain amplifier circuit using dual gate MO8FETs.

[Prior art]

Variable gain amplifiers using dual-gate MO5FETs perform gain control, so the voltage applied to the terminals to which no signal is input is generated at the output terminals [Television/Image Engineering Handbook (Ohmsha Publishing, 1980 1)]
February 30th, 1st edition), Chapter 3, 3.1.3. VHF tuner circuit chapter (p. 975-976)].

FIG. 8 shows an example of an amplifier circuit using the dual gate MO5FET.

In Fig. 8, coil (inductance) Ll, L2
and capacitors C1, C2, and C3 constitute a filter.m T r l is a dual-gate MO5FET transistor, and capacitor C4 and mutual inductance M
The primary coil L3 constitutes a resonant circuit and serves as a load for the dual gate MO5FET-Tr1. Coil L
4 and capacitor C5 form a resonant circuit for outputting to the next stage circuit. Capacitor C6 is an AC coupling capacitor for cutting DC.

The feature of the variable gain amplifier using the dual gate MO5FET is that a DC control voltage is applied to the AGC terminal to change the gain of the dual gate MO8FET-Tr4.

The control voltage can be applied with several types of fixed bias depending on the selected channel, or to ensure that the amplitude strength of the received signal is always constant (if the radio wave condition is affected by weather or location conditions, etc.). In order to prevent the output signal from becoming weaker due to interference), the output side signal is detected and peak-held, then smoothed and fed back to the AGC terminal.

FIG. 2 shows the static characteristics of the second gate G2 (control signal input terminal) voltage versus drain current of the dual gate MO5FET Tri, with the horizontal axis representing the second gate-source voltage and the vertical axis representing the drain current.

Voltage of the first gate G1 (voltage of the first gate G of multiple types)
The set drain current for the second gate G2 is plotted under the condition that G2 is fixed.

[Problem to be solved by the invention]

However, in the conventional variable gain amplifier, the eighth
When the control voltage of the AGC terminal of the variable gain amplifier shown in the figure is changed, the bias condition of T r i changes. As a result, the drain saturation current changes with respect to the gate voltage (see FIG. 2). Since this drain current changes depending on the voltage of the second gate G2, a transient response due to the above-mentioned cause occurs in the output every time the control voltage is changed.

There was a problem in that a signal could not be detected at the output until this response became stable.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a circuit in which a gain control voltage is output to a load as little as possible when a variable gain amplifier is constructed using dual gate MOSFETs.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides three sets of dual-gate MO8FETs with the same electrical characteristics.
In a variable gain amplifier consisting of 1 differential amplifier, 1
The differential amplifier has means for distributing the current flowing to the other two differential amplifiers, and a filter circuit for filtering the input signals of the two differential amplifiers operating with the divided current, The most important feature is that the drains of these two differential amplifiers are connected to the output load through terminals with different signal polarities.

In other words, three differential amplifiers using two balanced (equal electrical characteristics) dual-gate MO5FETs, three current sources, a variable bias circuit, a fixed bias circuit, and It consists of passive elements that act as loads.

The key to the invention is the use of two balanced pairs of dual gate MO8FETs.

In other words, the three sets of dual-gate MO5FETs are transistors in the same process, in the same lot, and on the same univer, and ideally they should be on the same chip when molded into a package (generally, one (This refers to transistor arrays and paired transistors, which are commercially available in which multiple semiconductor elements are housed in a package.)

[Effect]

The principle of the present invention will be explained using a variable gain amplifier configured as an analog multiplier using conventional bipolar transistors shown in FIG.

In FIG. 9, ell e2 is each input, e□xe
2 shows this output. Bipolar transistors 901 and 902 supply the current of current source 911, bipolar transistors 903 and 904 pair, and bipolar transistor 90.
5 and 906 pairs. This current difference changes the gains of the differential amplifiers of bipolar transistors 903 and 904 and the differential amplifiers of bipolar transistors 905 and 906.

The important point in the present invention is not that the conventional multiplier controls the gain based on the current difference, but that even if the amount of current is changed, the change does not occur in the output. First, it is assumed that a voltage is applied to the e-channel and a current difference of Δ1 occurs between bipolar transistors 901 and 902.

The pair of bipolar transistors 903 and 904 and the pair of bipolar transistors 905 and 906 are balanced if the input to C2 is zero (0), so the collector currents are equal and the collector currents of bipolar transistors 903 and 906 are equal.
The current difference of 05 is 1/2・∆mechanism. The same applies to bipolar transistors 904 and 906. however.

Base current is ignored. Resistor 9 is connected to the output of e□xe2.
13 and bipolar transistors 903 and 905 are connected, the collector current of bipolar transistor 903 is If the collector current of the bipolar transistor 905 is h, then from L-I, = 1/2 · Δ h,
L-1/4・Δwork=I, +174・Δwork. Each side corresponds to 1/4 of the current of the current source 911 (ΔI=
When O, I, = I), therefore, I, +I
, = 2・I, +1/2・ΔI= (I, +1/4・8I
), which is 172 of the current of the current source 911. Because Δwork is arbitrary.

The current flowing through the resistor 913 is always constant. When applying this configuration to the present invention and configuring an amplifier using dual gate MO8FETs, by adopting a differential configuration,
No influence of gain control - system can be configured.

The amplifier using dual gate MO5FET transistors has a common source configuration. Therefore, the difference in bias state appears as an output through the drain load. However, since gain control is performed, it is inevitable that the bias state will change, so by creating a path that compensates for the change in bias, the current flowing to the load can be kept constant. This path is achieved by providing a differential pair. By operating one differential pair as a differential amplifier and applying only the gain control voltage to the remaining differential pair without inputting a signal, the same bias change as that of the differential amplifier that inputs the signal is generated. let By connecting the drains of these two differential pairs to the load,
Perform current addition.

At this time, one differential pair is in a no-signal state.

Not involved in amplification, but the current flowing through the circuit is 1
Since there is only one current source, if the two electrical characteristics are equal, bias changes can be caused complementary to the two differential pairs by gain control. If the drain current of one differential pair is decreased by the amount that the drain current of one differential pair has increased.

A constant current will always flow through the load. Therefore,
Even if gain control is performed, its effect will not appear on the output.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a circuit diagram showing a schematic configuration of an embodiment of a variable gain amplifier according to the present invention.

In FIG. 1, numerals 1 to 4 are dual gate MO8FETs with uniform characteristics. Each dual gate MO5FET
1 to 4 (7) The bias potential of the bias power supply 8 is commonly applied to the first gate G1.

Further, a signal voltage from the signal source 13 is also commonly input to each of the first gates G1, but the dual gate MOSFET
The resistor 9 and capacitor 10 form a high-pass cut filter, so no signal is input to ET2-ET4. The cutoff frequency is determined by the values of the resistor 9 and capacitor 10, but it is sufficient that the time constants of these are one octave or less from the signal band. However, the capacitance of the capacitor 10 must be selected so that the frequency characteristics sufficiently extend to the signal band.

In order to operate the dual gate MO8FETs 5 and 6 with the same control voltage as the dual gate MO5FETs 1 to 4, the dual gate MOβFET1 is connected in parallel, and the dual gate MO5FETs are laid out so that twice the drain current of the dual gate MO8FETI flows through them. use. 11 is a level shifter, all of which can be the same, 12 is a current source, 7 is an output load,
Select resistors, capacitors, inductance, etc. depending on the application. CL and C11 are control voltage terminals for gain control.

Figure 2 shows the second gate of the dual gate MOSFET.
FIG. 3 is a diagram showing a characteristic curve of gate 02 versus drain current.

The gain control voltages of the control voltage terminals CL and 05 will be explained using FIG.

As is clear from Fig. 2, the characteristics of the dual-gate MO5FET are almost linear, as shown in the characteristic curves (a) and (b).
It can be seen that 1v or more can be approximated by a straight line (characteristic curve (c) can be approximated by a straight line).

The operation of the control voltage will be explained below using the characteristic curve (c) in FIG.

The voltage of the first gate G1 is set to 1V, and as shown in the characteristic line of FIG.
The voltage across gate 62 is controlled. At this time, as can be read from the characteristic curve 11A(C) in FIG. 2, the drain current changes by 2 to 20 mA for a control voltage of 0 to 1.2 V.

Therefore, a current of 22 mA always flows through the output load 7.

Next, the operation of the differential amplification type amplifier circuit of this embodiment will be explained.

In Figure 1, a dual-gate MO for signal amplification is shown.
By changing the gain control voltage of the control voltage terminal CL for gain control from 0 to 1.2 V, the forward transfer admittance of the dual gate MO5FETI and 2 can be changed as shown in Fig. 3 (first gate G forward transfer admittance characteristic curve versus source voltage).
The voltage of the first gate G1 is set to 1■). As a result, the gains of the dual gate MO5FETs 1 and 2 change by ZXYfs, where Z is the impedance of the dual gate MO8FET6 and Yfs is the forward transfer admittance. Similarly, the gains of dual-gate MO8FETs 3 and 4 change according to the characteristic curve ZXYfs' in Figure 3, but as mentioned above, the input is filtered and can be considered to be in a fixed biased state, so that the amplification effect does not change. is not involved.

Here, it is clear from Kirchhoff's law that the current at point A in FIG.
(Because the impedance between the gate and drain or source of the MOSFET is large, the bias current is very small and can be ignored.)

Therefore, ideally, the potential at point A will not change even if the gain of the dual gate MO5FETI is controlled. From the above, since gain control has no effect on the output, the output signal can be detected immediately even after gain switching. Further, even if gain control is performed near the signal frequency band, extremely high-speed gain control is possible without generating a gain control voltage at the output.

Next, an embodiment of the control voltage circuit of the control voltage terminal C8 for gain control is shown in FIGS. 5A and 5B.

Control voltage terminal C for gain control is controlled by the fifth control voltage terminal when gain control is performed using several types of fixed bias.
As shown in Figure A, it can be configured with fixed resistors R1°R2...Rn and switches SWI, 5W2---5Wn.

Moreover, the block diagram shown in FIG. 5B is for stabilizing the output amplitude to a constant value.

In this circuit, the output is detected by a detection circuit 51, the gain is adjusted by a gain adjustment circuit 52, the level is shifted by a level shift circuit 53, and the output is temporarily held by a buffer circuit 54 to apply feedback.

Next, FIG. 6 shows an embodiment of a control voltage circuit for the control voltage terminal CL for gain control.

The control voltage circuit for the control voltage terminal CL for gain control can be constituted by an operation (OP) amplifier-stage addition circuit, as shown in FIG.

In FIG. 6, the negative (-) value of the full range control voltage of the characteristic line shown in FIG. 4 is input to one terminal of the adder, and the other terminal is the gain control voltage of the control voltage terminal C5 for gain control. Connect to the output of

At this time, the driving ability of the control voltage terminal CL is required to be able to sufficiently drive this adder circuit. Here, if the feedback resistance is R, then 1/3R
The circuit must have a buffer function that can drive With this circuit, when the control voltage terminal CL has the minimum output, the control voltage terminal C3 has the maximum output, and when the control voltage terminal CL has the maximum output,
The control voltage terminal CR has a minimum output. The minimum value can also be changed by applying an offset voltage to the positive (+) input terminal of this operational amplifier.

However, since the signal frequency band of the dual gate MO3FET is very high, high-speed gain control is possible at the operating frequency of the operational amplifier.

The current source 12 is not limited in terms of elements, and may be a current source using bipolar transistors Q, Q, as shown in FIG. 7A, or a MOS transistor P, as shown in FIG. 7B.
A current source using ,N,,N, is used.

As can be seen from the above description, according to this embodiment, no gain control voltage is generated at the output. For this reason.

Gain control is possible at the same frequency as the signal. A high-speed multiplier can be realized.

In addition, conventional variable gain amplifier circuits require a filter to cut the gain control voltage output, but this is no longer necessary.

This is also suitable for monolithization.

Above, the present invention was specifically explained using examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a variable gain amplifier in which no gain control voltage is generated at the output.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a schematic configuration of an embodiment of an amplifier circuit of the present invention, and FIG. 2 is a diagram showing a static characteristic curve of the second gate 62 versus drain current of a dual MO8FET. FIG. 3 is a diagram showing the first gate G to source voltage vs. forward transfer admittance characteristic curve, FIG. 4 is a diagram showing control voltage characteristics, and FIGS. 5A and 5B are control voltage terminal C0 control for gain control. FIG. 6 is a diagram showing an embodiment of the voltage circuit, FIG. 6 is a diagram showing an embodiment of the control voltage circuit of the control voltage terminal C for gain control, and FIG. 7 is an embodiment of the current source of FIG. FIG. 8 is a diagram showing an example, and FIG. 8 is a diagram for explaining the problems of an amplifier using a conventional dual-gate MO8FET. FIG. 9 is a diagram showing the basic configuration of a multiplier for explaining the present invention in detail. It is a diagram. , In the figure, 1 to 6... dual gate MO8FET. 7... Output load, 8... Bias power supply, 9...
Resistor, 10... Capacitor, 11... Level shifter, 12... Current source, 13... Signal source. #2 times #3rfJ - #r Gate Nzu/#! Le (Vat phantom Cv3C10
Razor P'f Death [v] Meoto Exit 7A Exit

Claims (1)

[Claims] (1) Three sets of dual gate MOs with uniform electrical characteristics
In a variable gain amplifier consisting of three differential amplifiers configured with SFETs, means for distributing the current flowing in one differential amplifier to the other two differential amplifiers; A variable gain device comprising a filter circuit that filters the input signals of two differential amplifiers in operation, and in which the drains of the two differential amplifiers are connected to terminals with different signal polarities to the output load. type amplifier.