JPH021950A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH021950A JPH021950A JP14433888A JP14433888A JPH021950A JP H021950 A JPH021950 A JP H021950A JP 14433888 A JP14433888 A JP 14433888A JP 14433888 A JP14433888 A JP 14433888A JP H021950 A JPH021950 A JP H021950A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- region
- layer
- electrode layer
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 9
- 239000007772 electrode material Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置に関し、特に複数の半導体素子が
設けられた半導体基板上に、複数の半導体素子と共通接
続された電極層が設けられ、上記複数の半導体素子のう
ち少なくとも１つ以上の半導体素子に対応する電極層の
一部をボンディングパッドとして利用する半導体装置の
ボンディングパッド部分の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device, and in particular, an electrode layer commonly connected to the plurality of semiconductor elements is provided on a semiconductor substrate on which a plurality of semiconductor elements are provided, The present invention relates to a structure of a bonding pad portion of a semiconductor device in which a part of an electrode layer corresponding to at least one semiconductor element among the plurality of semiconductor elements is used as a bonding pad.
第２図はパワーＭ ＯＳ Ｆ Ｅ Ｔ素子１ａの構造を
示す断面図である。同図において、Ｎ＋層２の一方主面
、トにはＮ−層３がエピタキシャル成長により形成され
て半導体基板が構成されている。このＮ−層３の表面か
ら選択的に不純物を二段階に分けて拡散させる二重拡散
法により、Ｐ領域４が形成され、このＰ領域４の表面か
ら選択的に不純物を拡散して、Ｐ領域４内に２個のＮ＋
領域５が一定間隔をもって形成されている。さらに、
層３の表面から各Ｎ゛領域の表面の一部にか【プて絶縁
層６が形成され、各絶縁層６の中には例えばポリシリコ
ンから成るゲート電極７がそれぞれ形成されている。ま
た、Ｐ領Ｉｊ！！４およびＮ＋領域５の両方に電気的に
接続されるようにＡＪ−８ｉからなるソース電極８が形
成されている。また、Ｎ１半導体基板２＠面には金属か
らなるドレイン電極９が形成されている。FIG. 2 is a sectional view showing the structure of the power MOSFET element 1a. In the figure, an N- layer 3 is formed by epitaxial growth on one main surface of an N+ layer 2, forming a semiconductor substrate. A P region 4 is formed by a double diffusion method in which impurities are selectively diffused in two stages from the surface of this N- layer 3. By selectively diffusing impurities from the surface of this P region 4, P 2 N+ in area 4
Regions 5 are formed at regular intervals. moreover,
An insulating layer 6 is formed extending from the surface of the layer 3 to a part of the surface of each N'' region, and a gate electrode 7 made of polysilicon, for example, is formed in each insulating layer 6. Also, P territory Ij! ! A source electrode 8 made of AJ-8i is formed so as to be electrically connected to both the N+ region 4 and the N+ region 5. Further, a drain electrode 9 made of metal is formed on the @ surface of the N1 semiconductor substrate 2.
次に、このパワーＭＯ８Ｆ Ｅ Ｔ素子１ａの動作につ
いて説明する。第２図に示すパワーＭＯ３ＦＥＴ素子１
ａのドレイン電極９とソース電極８間に一定のドレイン
電圧Ｖ。８を印加した状態で、ゲート電極７とソース電
極８間にそのパワーＭＯ８ＦＥＴ１のしぎい値電圧ｖ１
以上のゲート電圧ＶＧＳを印加すると、Ｐ領域４のうち
Ｎ 層３とＮ＋領域５とに挟まれ、かつゲート電極７に
対応する領域にチｉ？ネルが形成されてドレイン電極９
とソース電極８間にドレイン電流が流れる。したがって
、ゲート電圧ＶＧＳを制御することによりドレイン電流
を制御することができる。Next, the operation of this power MO8FET element 1a will be explained. Power MO3FET element 1 shown in Fig. 2
A constant drain voltage V between the drain electrode 9 and the source electrode 8 of a. 8 is applied, the threshold voltage v1 of the power MO8FET1 is applied between the gate electrode 7 and the source electrode 8.
When the above gate voltage VGS is applied, a region of the P region 4 that is sandwiched between the N layer 3 and the N+ region 5 and that corresponds to the gate electrode 7 is filled with chi? A channel is formed and the drain electrode 9
A drain current flows between the source electrode 8 and the source electrode 8. Therefore, the drain current can be controlled by controlling the gate voltage VGS.
ところで、実使用においては、第３図に示すように、半
導体基板にパワーＭＯ８ＦＥＴ索子１ａを複数設け、ソ
ース電極層８０によりこれら複数のパワーＭＯ８ＦＥＴ
素子１ａを並列接続して、１つのパワーＭ ＯＳ Ｆ
Ｅ Ｔ １を形成している。また、適当な位置にボンデ
ィングパッドを設け、パワーＭＯ８ＦＥＴＩの適当な部
位と電気的に接続している。従来、このボンディングパ
ッド直下にはパワーＭＯ８ＦＥＴ素子１ａ（第２図）を
形成してい低かったが、近年集積度の向上に対応すべく
ボンディングパッド直下にもパワーＭＯ８ＦＥＴ素子１
ａを形成するようになった。すなわち、第３図に示すよ
うに、ソース電極層８０のうらボンディングワイヤ（図
示省略）をボンディングするボンディング領域２０以外
の領域上にパワーＭＯ８ＦＥＴＸ子保護用のガラスコー
ト２１を形成し、さらにワイヤボンディング工程におい
てボンディング領域２０とリードフレーム（図示省略）
とを金！２笠のボンディングワイヤノ（図示省略）によ
り電気的に接続している。そして、これらソース電極層
８０．ボンゲイングワイヤおよびリードフレームを介し
て、外部から適当な電位がＰＴＩＩＩ！４ Ｊ３よびＮ
＋領域５の両方に供給されるように構成されている。By the way, in actual use, as shown in FIG.
By connecting the elements 1a in parallel, one power MOSF
It forms E T 1. Further, bonding pads are provided at appropriate positions and electrically connected to appropriate parts of the power MO8FETI. Conventionally, the power MO8FET element 1a (Fig. 2) was formed directly under this bonding pad, and the power MO8FET element 1a (Fig. 2) was formed directly below the bonding pad.
began to form a. That is, as shown in FIG. 3, a glass coat 21 for protecting the power MO8FETX element is formed on a region other than the bonding region 20 to which a bonding wire (not shown) is bonded behind the source electrode layer 80, and then a wire bonding process is performed. The bonding area 20 and the lead frame (not shown)
And gold! They are electrically connected by two bonding wires (not shown). These source electrode layers 80. A suitable potential is applied externally via the bonding wire and the lead frame. 4 J3 and N
+ region 5.
上記のように、ワイヤボンディング工程においてボンデ
ィングワイヤをボンディング領域２０上にボンディング
すると、ボンディング時のダメージがソース電極層８０
を介してそのボンディング領［２０に対応するパワーＭ
Ｏ８ＦＥＴ素子群１ｂにおよび、パワーＭＯ８ＦＥＴＩ
の信頼性が低下する。As described above, when a bonding wire is bonded onto the bonding region 20 in the wire bonding process, damage during bonding is caused to the source electrode layer 80.
The power M corresponding to the bonding region [20
O8FET element group 1b and power MO8FETI
reliability decreases.
これを防止する方法としてソース電極層８０全体を厚く
形成し、上記ダメージをそのソース電極層８０により吸
収するという対策が考えられる。A possible method for preventing this is to make the entire source electrode layer 80 thick so that the damage is absorbed by the source electrode layer 80.
しかしながら、ソース電極層８０全体を厚（することは
、パワーＭＯ８ＦＥＴ１の微細化に不具合が生じる。そ
の理由を説明り°るとつぎのとおりである。すなわち、
ソース電極層８０を所定パターンにパターンニングする
ための方法としＣ従来より写真製版法が一般的に用いら
れている。この方法は、第３図に示すように、まず基体
２２上にソース電極１１１８０の電極材料２３、例えば
Ａ！−３ｉ等を均一に形成し、所定領域に開口部２４ａ
を有するレジスト２４をその電極材料２３上に形成した
後、このレジスト２４をマスクとしてエツチングを行う
。この場合、電極材料２３が厚くなるにしたがってサイ
ドエラ１２５の度合いが増寸ため、上述したようにソー
ス電極層８０全体を厚くすることは微細パターンの形成
を困難とする。However, making the entire source electrode layer 80 thick causes problems in miniaturization of the power MO8FET 1. The reason for this is as follows. That is,
Photolithography has been commonly used as a method for patterning the source electrode layer 80 into a predetermined pattern. In this method, as shown in FIG. 3, the electrode material 23 of the source electrode 11180, for example A! -3i etc. are formed uniformly, and the opening 24a is formed in a predetermined area.
After forming a resist 24 having the following properties on the electrode material 23, etching is performed using the resist 24 as a mask. In this case, as the electrode material 23 becomes thicker, the degree of the side erra 125 increases, so increasing the thickness of the entire source electrode layer 80 as described above makes it difficult to form a fine pattern.
また、ソース電１［８０の厚みの増大に伴ってカバレッ
ジに対する考慮が必要となり、この点からも一定厚み以
上のソース電極層８０を形成することができない。Furthermore, as the thickness of the source electrode 1 [80 increases, consideration must be given to coverage, and from this point of view as well, the source electrode layer 80 cannot be formed to have a thickness greater than a certain value.
この発明は上記のような課題を解消するためになされた
もので、ワイヤボンディング時にボンディング領域直下
の半導体素子に与えられるダメージを軽減することがぐ
ぎるとともに、ボンディング領域以外の領域での微細パ
ターンの形成を可能とする半導体装買を１！？ることを
目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to reduce the damage caused to semiconductor elements directly under the bonding area during wire bonding, and to reduce the damage caused to fine patterns in areas other than the bonding area. 1. Semiconductor equipment that enables formation! ? The porpose is to do.
この発明は、半導体基板と、前記半導体基板に・形成さ
れた複数の半導体素子と、前記半導体基板上に形成され
、前記複数の半導体素子と共通接続された電極層とを備
え、前記複数の半導体素子のうち少なくと６１つ以上の
半導体素子に対応する前記電極層の一部をボンディング
パッドとして利用する半導体装置において、前記電極層
のうち前記ボンディングパッドとしても機能するボンデ
ィング領域の厚みを前記ボンディング領域、以外の領域
の厚みよりも厚くしている。The present invention includes a semiconductor substrate, a plurality of semiconductor elements formed on the semiconductor substrate, and an electrode layer formed on the semiconductor substrate and commonly connected to the plurality of semiconductor elements, In a semiconductor device in which a part of the electrode layer corresponding to at least 61 or more semiconductor elements among the elements is used as a bonding pad, the thickness of the bonding region of the electrode layer that also functions as the bonding pad is defined as the bonding region. , is thicker than the other areas.
この発明における半導体装置によれば、電極層のうらボ
ンデ、Ｃングパツドとして６機能するボンディング領域
の厚みが前記ボンディング領域以外の領域の厚みよりも
厚くなるように前記電極層が構成されているため、前記
ボンディング領域にＪ：リワイＡ７ボンデイング時のダ
メージが軽減される一方、ボンディング領域以外の領域
での微細パターンの形成が可能となる。According to the semiconductor device of the present invention, the electrode layer is configured such that the thickness of the bonding region that functions as a back bonder and C ring pad of the electrode layer is thicker than the thickness of the region other than the bonding region. J: Rewie A7 damage to the bonding area during bonding is reduced, while fine patterns can be formed in areas other than the bonding area.
第１図はこの発明にかかる半導体装置であるパワーＭＯ
３ＦＥＴ１’の構造を示す断面図である。FIG. 1 shows a power MO which is a semiconductor device according to the present invention.
It is a sectional view showing the structure of 3FET1'.
このパワーＭＯ８ＦＥＴＩ’ が従来のパワーＭＯ８Ｆ
ＥＴＩと異なる点は、本発明においてソース電極Ｆ１８
０のうちボンディング領域２０とそのボンディング領ｌ
ｌＡ２０に対応するパワーＭＯ８ＦＥＴ素子群１ｂとの
間にソース電極層８０を構成する電極材料と同一の材料
からなるダメージ吸収層３０を設けていることであり、
その他の構成は従来のパワーＭＯ３ＦＥＴ１と同一であ
る。This power MO8FETI' is the conventional power MO8F
The difference from ETI is that in the present invention, the source electrode F18
0, the bonding area 20 and its bonding area l
A damage absorption layer 30 made of the same material as the electrode material constituting the source electrode layer 80 is provided between the power MO8FET element group 1b corresponding to the lA20,
The other configurations are the same as the conventional power MO3FET1.
以上のように、ダメージ吸収層３０を設けることにより
、ボンディング領域２０の表面からパワーＭＯ８ＦＥＴ
素子群１ｂまでの厚みが従来のらのに比べてダメージ吸
収層３０の分だけ厚くなるので、本実施例にお【ノるワ
イヤボンディング時のダメージはダメージ吸収層３０を
設けた分だけ従来のパワーＭＯ８Ｆ Ｅ Ｔ １より軽
減される。また、ボンディング領域２０以外の領域での
ソース電極Ｅ’４８０の厚みが従来と同一であるため、
微細パターンの形成に支障をきたすこともない。As described above, by providing the damage absorption layer 30, the power MO8FET can be removed from the surface of the bonding region 20.
The thickness up to the element group 1b is thicker than the conventional one by the amount of the damage absorption layer 30. The power is reduced from MO8FET1. Furthermore, since the thickness of the source electrode E'480 in the region other than the bonding region 20 is the same as that of the conventional one,
It does not interfere with the formation of fine patterns.
なお、上記実施例ではボンディング領域２０の表面から
パワーＭＯ８Ｆ Ｅ Ｔ素子群１ｂまでの厚みを従来の
ものより厚くするためにボンディング領域２０とそのボ
ンディング領域２０に対応するパワーＭＯ８ＦＥＴ素子
群１ｂとの間にダメージ吸収層３０を設けたが、これ以
外に第３図に示ず従来のパワーＭＯ３ＦＥＴ１のソース
電極層８０におけるボンディング領域２０上にダメージ
吸収層３０を設けてもよい。In the above embodiment, in order to make the thickness from the surface of the bonding region 20 to the power MO8FET element group 1b thicker than that of the conventional one, there is a gap between the bonding region 20 and the power MO8FET element group 1b corresponding to the bonding region 20. Although the damage absorption layer 30 is provided in FIG. 3, the damage absorption layer 30 may be provided on the bonding region 20 in the source electrode layer 80 of the conventional power MO3FET 1, which is not shown in FIG.
また、上記実施例ではダメージ吸収層３０をソース電極
層８０の電極材料と同一のものくＡｌ５ｉ）により構成
したが、これ以外に伯の電極材料、例えばモリブデンシ
リサイドやタングステンシリサイド等を用いてもよいこ
とは言うまでらない。Further, in the above embodiment, the damage absorption layer 30 is made of the same electrode material as the source electrode layer 80 (Al5i), but other electrode materials such as molybdenum silicide, tungsten silicide, etc. may also be used. Needless to say.
また、上記実施例ではＮチ１ｐネルパワーＭＯ３ＦＥＴ
の場合について説明したが、この発明はＰヂｐネルパワ
ーＭＯ８ＦＥＴにも適用することができる。In addition, in the above embodiment, an N channel 1p channel power MO3FET is used.
Although the case has been described, the present invention can also be applied to a PDP channel power MO8FET.
また、上記実施例ではパワーＭＯ８ＦＥＴについて説明
したが、その他の半導体装置、例えば絶縁ゲー］・型バ
イポーラ１−ランジスタに本発明を適用することも可能
であり、上記と同様に、絶縁ゲート型バイポーラトラン
ジスタ等の半導体装置へのワイヤボンディング時のダメ
ージを軽減でき、その信頼性を向上させることができる
。Furthermore, although the above embodiment describes a power MO8FET, the present invention can also be applied to other semiconductor devices, such as an insulated gate type bipolar transistor. It is possible to reduce damage during wire bonding to a semiconductor device such as the like, and improve its reliability.
以［のように、この発明によれば、電極層のうちボンデ
ィングパッドとしても機能するボンディング領域の厚み
を前記ボンディング領域以外の領域の厚みＪ：りも厚く
しているので、前記ボンディング領域によりワイヤボン
ディング時のダメージを軽減ぐきるとともに、ボンディ
ング領域以外の領域での微細パターンの形成が可能とな
るという効果がある。As described above, according to the present invention, the thickness of the bonding region of the electrode layer that also functions as a bonding pad is made thicker than the thickness J of the region other than the bonding region. This has the effect of reducing damage during bonding and making it possible to form fine patterns in areas other than the bonding area.
第１図はこの発明にかかる半導体装置であるパワーＭＯ
８ＦＥＴの断面図、第２図はパワーＭＯ８ＦＥＴ素子の
断面図、第３図は従来のパワーＭＯ３ＦＥＴの断面図、
第４図はソース電極の製造ＩＪ法を示す断面図である。
図において、１ａはパワーＭ ＯＳ Ｆ Ｅ Ｔ素子。
１ｂはパワーＭＯ８Ｆ Ｅ Ｔ素子群、２０はボンディ
ング領域、８０はソース電極層である。
なお、各図中同一符号は同一または相当部分を示す。
第
図FIG. 1 shows a power MO which is a semiconductor device according to the present invention.
8FET cross-sectional view, Figure 2 is a cross-sectional view of a power MO8FET element, Figure 3 is a cross-sectional view of a conventional power MO3FET,
FIG. 4 is a cross-sectional view showing the IJ method for manufacturing the source electrode. In the figure, 1a is a power MOSFET element. 1b is a power MO8FET element group, 20 is a bonding region, and 80 is a source electrode layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Diagram
Claims (1)
の半導体素子と、前記半導体基板上に形成され、前記複
数の半導体素子と共通接続された電極層とを備え、前記
複数の半導体素子のうち少なくとも１つ以上の半導体素
子に対応する前記電極層の一部をボンディングパッドと
して利用する半導体装置において、 前記電極層のうち前記ボンディングパッドとしても機能
するボンディング領域の厚みが前記ボンディング領域以
外の領域の厚みよりも厚いことを特徴とする半導体装置
。(1) A semiconductor substrate, a plurality of semiconductor elements formed on the semiconductor substrate, and an electrode layer formed on the semiconductor substrate and commonly connected to the plurality of semiconductor elements, In a semiconductor device in which a part of the electrode layer corresponding to at least one semiconductor element is used as a bonding pad, the thickness of the bonding region of the electrode layer that also functions as the bonding pad is a region other than the bonding region. A semiconductor device characterized by being thicker than .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14433888A JPH021950A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14433888A JPH021950A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH021950A true JPH021950A (en) | 1990-01-08 |
Family
ID=15359786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14433888A Pending JPH021950A (en) | 1988-06-10 | 1988-06-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH021950A (en) |
-
1988
- 1988-06-10 JP JP14433888A patent/JPH021950A/en active Pending
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