JPH02193247A - Controller provided with plural microcomputers - Google Patents

Abstract

PURPOSE:To increase the processing speed of each microcomputer by connecting the operation processing part of each microcomputer to another microcomputer or an external device through a dual port RAM and independently operating the operation processing part of the microcomputer. CONSTITUTION:A microcomputer 1 in a high hierarchy and two microcomputers 2 and 3 in a low hierarchy as the fundamental constitution are provided. Since operation processing parts (CPU) 10a and 10b of these microcomputers 1 to 3 are connected to another microcomputer or an external device through a dual port RAM 60, processing parts (CPU) 10a and 10b of microcomputers 1 to 3 are independently operated. Thus, the processing speed of each microcomputer is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device equipped with a plurality of microcomputers.

[Prior Art 1] FIG. 7 shows, for example, three microcomputers 301.
302 and 303, and is a block diagram of a conventional control system for controlling individual control objects individually or in a correlated manner.

In the control system shown in FIG. 7, each address terminal of microcomputers 301, 302, 303 is connected to an address bus 310,
Each data terminal of 2,302,303 is a data bus 311
are connected to each microcomputer 301, 3.
02.303 mutually transmits address data via the address bus 31O in order to perform correlated control.
Data is mutually transmitted via the data bus 311, and information data necessary for control is exchanged in a time-sharing manner.

[Problems to be Solved by the Invention] However, in the conventional control system described above, one pair of address buses 310 and one pair of data buses 31
1, address data and data are exchanged on a time-sharing basis, respectively, so software or hardware is required to control the use of the address bus 310 and data bus 311, making the configuration of the control system complex. become. Further, while any two microcomputers are communicating, the other microcomputer cannot communicate via the buses 310 and 311, so it must wait, and as a result, each microcomputer 301', There was a problem in that the processing speed of 302 and 303 was reduced.

An object of the present invention is to solve the above problems, to provide a microcomputer for each microphone (hereinafter referred to as a first microcomputer), which has a simpler configuration than the conventional example.

) is connected to another microcomputer (
Hereinafter, it will be referred to as the second microcomputer. ), first, the arithmetic processing unit of the first microcomputer transfers the data to the dual bus via the master bus of the first microcomputer and the slave bus of the second microcomputer. Write to port RAM. Next, the arithmetic processing section of the second microcomputer reads the data written in the dual port RAM, thereby transferring the data from the arithmetic processing section of the first microcomputer to the arithmetic processing section of the second microcomputer. The data transfer ends.

Furthermore, when transferring data from the arithmetic processing section of the second microcomputer to the arithmetic processing section of the first microcomputer, the arithmetic processing section of the second microcomputer transfers the data to the dual port RA in advance.
Write in M. Another object of the present invention is to provide a control device equipped with a plurality of microcomputers that can improve the processing speed of the first microcomputer.

[Means for Solving the Problems] The present invention is a control device comprising a plurality of microcomputers, each microcomputer having a control unit for communicating data between an arithmetic processing unit and other microcomputers or external devices. The bus includes at least a master bus that is directly connected to other microcomputers or external devices and directly controlled by the arithmetic processing section, and a dual port RAM that is connected to other microcomputers or external devices. A slave bus is connected through the slave bus, and data communication is controlled by the other microcomputer or external device.

Further, the configuration of the master bus and the slave bus are the same.

[Operation] In the control device configured as described above, one section transfers the data written to the dual port RAM via the slave bus of the second microcomputer and the master bus of the first microcomputer. This completes the data transfer from the arithmetic processing section of the second microcomputer to the arithmetic processing section of the first microcomputer.

As described above, since the arithmetic processing section of each microcomputer is connected to other microcomputers or external devices via the dual port RAM, the arithmetic processing section of each microcomputer operates independently. be able to.

Furthermore, if the configurations of the master bus and slave bus of each microcomputer are the same, connection with other microcomputers or external devices can be easily performed.

[Embodiment] FIG. 1 is a block diagram of a control system including three microcomputers 1 and 2.3, which is an embodiment of the present invention.

This control system includes an upper layer microcomputer 1 and two lower layer microcomputers 2, 3, and the upper layer microcomputer 1 connects each slave bus SB2.
A central computing geographical unit (hereinafter referred to as C
It is called PU. ) tOa, and each microcomputer 2.3 in the lower hierarchy has an input/output controller 72a,
72b and is directly controlled by the CPU 10b and the CPU (not shown) of the microcomputer 3 in order to communicate data with the input/output controllers 72a and 72b. MB3, microcomputer 1 and dual baud 1-RAM (hereinafter referred to as DP-RAM)
That's what it means. ) 60, and data communication is controlled by the microcomputer 1.
, SB3.

Here, this control system includes a sensor 70a, 7CPU
The data input/output terminals D7-Do of the CPU 10a are connected to the 8-bit data bus 32a, and are connected to the reset signal input terminal RESET and the ready signal input terminal READY of the CPU 10a.
and interrupt signal input terminal INT are connected to a 3-bit status bus 33a. CPUl0a is ROM1
Operates according to the system program stored in 4a,
After performing predetermined calculations based on each input signal input via the status bus 33a and data input via the data bus 32a, an address is output to the address bus 31a for predetermined control, and Data is output to data bus 32a.

Furthermore, CPU IQ a, RAM13 a, RO
When accessing M14a and the DP-RAM 60, which will be described in detail later, the address valid signal ASTB is output to the control bus 30a at LH level (for data reading) or L level (for data writing).
A read/write signal R/W is output to the control bus 30a.

In FIG. 2, the decoder lla performs calculations for predetermined control based on the detection signals detected by each module 120b, and transfers the calculated control data to the actuator 74.
a, 74b for control. In FIG. 1, the microcomputer 3 in the lower hierarchy has the same basic configuration as the other microcomputer 2, so it is shown in a greatly simplified manner.

The upper layer microcomputer 1 includes a CPU 10a that controls the microcomputer 1, and a decoder 11.
a, a timer 12a, a random access memory (hereinafter referred to as RAM) 13a, and a read only memory (hereinafter referred to as ROM).

) 14a and buffer amplifiers 20a, 51a, 52'a
, 53a, a bidirectional buffer amplifier 54a, and a signal generation circuit 40a.

The address valid signal output terminal ASTB and the read/write signal output terminal R/W of the CPU 10a are connected to the 2-bit control bus 30a, and the address output terminals A16-AO of the CPU 10a are connected to the 17-bit address bus 31.
connected to a. It is also a diagram showing an address map of the microcomputer l used when outputting select signals to a, 13a, and 14a, and in the address map of FIG. 2, addresses are expressed in hexadecimal numbers.

In the address map in Figure 2, address 00000
The addresses from 07FFF to 07FFF are addresses used when communicating data with the microcomputers 2 and 3 or another external device via the master bus MB1.
Addresses from ooo to 03FFF are used when communicating data with external devices other than microcomputer 2.3 in the lower hierarchy, and addresses from 04000 to 0
Up to 7FFF, the lower layer microcomputer 2,
It is used as an address when communicating data with 3. Here, addresses 04000 to 047FF are used as addresses when communicating data with the microcomputer 2, and addresses 04800 to 047FF are used for data communication with the microcomputer 2.
The addresses up to FFF are used as addresses when communicating data with the microcomputer 3, and thereafter, addresses are assigned in the same manner so that up to eight lower layer microcomputers can be connected to the upper layer microcomputer 1. has been done.

Further, addresses 08000 to 087FF are addresses used when transmitting data to a microcomputer in an upper layer, and are not used in the case of this microcomputer 1.

Further, addresses 08800 to lFFFF are addresses for specifying internal modules of the microcomputer 1. Here, from address 08800 to 0
Until 8FFF, timer 12a and input/output controller (
The microcomputer 1 is not provided, but the microcomputer 2.3 in the lower hierarchy is provided. , ) is used as an address to specify the address 09000.
The addresses from 0FFFF to 0FFFF are used as addresses for specifying the RAM 13a, and the addresses 10000 to 1FFFF are used as addresses for specifying the ROM 14a.

3a to the reset signal input terminal RE of the CPU 10a.
It is input to SET and interrupt signal input terminal INT.

The signal generating circuit 40a transmits the upper 8 bits of the address (hereinafter referred to as the upper address) and the lower 8 bits of the address (hereinafter referred to as the lower address) on the data bus AD7-ADO in a time division manner, as shown in FIG. As shown in FIG. 3, in response to the change in the read/write signal R/W at time t1, the upper address valid signal πAs at L level is output to the buffer amplifiers 51a to 54a, and then at time t1.
At time t2 after a time Δ from
Output to a.

The master bus MBI has a 1-bit ready signal line READ.
Y and 3-bit control buses HAS, LAS, R
/W and an 8-hit notator bus AD7-ADO, and is connected to each slave bus SB2.3B3 of the microcomputer 2.3 in the lower hierarchy.

Decoder lla receives address bus 3 from CPIJIOa.
1a and according to the address map of FIG. 2 described above, the timer 12aS
A select signal SEL for enabling each module is output to the RAMI 3a or ROM 14a. R
The AM1aa is connected to the control bus 30a1, the address bus 31a, and the data bus 32a, and temporarily stores data input from the CPU 1Oa via the data bus 32a in response to an L-level read/write signal R/W. , and outputs the accumulated data to the data bus 32a in response to the H level read/write signal R/W. R
OM1Ja is connected to control bus 30a, address bus 31a, and data bus 32a, and outputs data stored in ROM 14a to data bus 32a in response to an H-level read/write signal R/W.

A reset signal RESET and an interrupt signal INT output from an external device (not shown) are transmitted to the buffer amplifier 20a and the status bus 3 buffer amplifier 51, respectively.
a is always enabled, and after buffering and amplifying the upper address signal π top 1 and lower address valid signal LAS inputted from the signal generation circuit 40a, and the read/write signal R/W inputted from the control bus 30a, the master bus MBI control bus HAS, LAS, R/W
Output to. The buffer amplifier 52a is enabled only before and after the upper effective address signal RAS falls from the H level to the L level, and after buffering and amplifying the upper address input from the address bus 31a, the buffer amplifier 52a buffers and amplifies the upper address input from the address bus 31a. The buffer amplifier 53a is enabled only for the time before and after the lower effective address signal LAS falls from the H level to the L level, and after buffering and amplifying the lower address input from the address bus 31a, the buffer amplifier 53a outputs the lower address to the master bus MB1. The bidirectional buffer amplifier 54a is enabled after the time Δ has elapsed after LAS falls, and is de-enabled at the same time that πAS rises.

After buffering and amplifying the 8-bit data input from the data bus 32a, the data bus AD7-A of the master bus MB1
It buffers and amplifies 8-bit data input from data buses AD7-ADO of master bus MBI and then outputs it to data bus 32a. The buffer amplifier 55a is connected to the ready signal line R of the master bus MBI.
After buffering and amplifying the ready signal input from EADY,
It is output to the ready signal input terminal READY of CPtJIO& via the status bus 33a.

The lower layer microcomputer 2 includes a CPU I Ob, a decoder 11b, a timer 12b, a RAM 13b, a ROM 14b, and buffer amplifiers 20b, 51b, and 52b, each having the same functions as the corresponding modules of the microcomputer 1.

53b, 55b, a bidirectional buffer amplifier 54b1, and a signal generation circuit 40b, and further includes an input/output controller 15b, buffer amplifiers 21b, 62.6
3b, a DP-RAM 60, a decoder 61, latch circuits 64b, 65b, 66b, a bidirectional buffer amplifier 67b, and an oven collector type buffer amplifier 68b.

The decoder 11b sends a select signal SEL for enabling each module to the timer 12b, RAM 13, based on the address input from the address bus 31b.
b, ROM14b, input/output controller 15b1 or D
Output to P-RAM60.

A 3-bit lower hierarchy MC designation signal S2-8O specifying the allocation number of the lower hierarchy microcomputer 2 to the upper hierarchy microcomputer 1 is inputted to the input/output controller 15b via the buffer amplifier 21b. For example, if the assigned number of the microcomputer 2 is "1", the designation signal S2-5o of "ooo"
is input. In addition, the microcomputer 3 described later
When the 0 assigned number is °''2°', the designation signal 32-50 of "001" is input to the microcomputer 3.The same applies hereafter even when connecting a microcomputer in another lower hierarchy. So = 15.

The input/output controller 15b receives the input designation signal S2.
-3o to the decoder 61, and also monitors the data on the data bus 32b and sends an 8-bit processing status signal indicating whether or not the processing of the CPU 10b has been completed to the slave bus SB2 via the buffer amplifier 62.68b. Output to data bus AD7-ADO. Here, when the processing of the CPUs of the microcomputers 2 and 3 in the lower hierarchy is completed, the processing status signal is set to "oooooo".

In addition, the upper layer microcomputer l
Which microcomputer in the lower hierarchy 2.3
The microcomputer 2
The unfinished processing status signal output from the input/output controller 15b in the microcomputer 3 is set to "00000001" (the least significant bit is "1"), and the signal is output from the input/output controller (not shown) in the microcomputer 3. The processing status signal output when unfinished is “00000010”
(The second bit from the least significant bit is 11111.) Thereafter, even if a microcomputer of another lower hierarchy is connected, the above-mentioned unfinished processing status signal is set in the same way.

The DP-RAM 60 has two sets of access terminals, a first and a second access terminal, and has a storage capacity of 2 to 2 bytes, allowing access to the first and second access terminals from separate devices, as is well known. It is a RAM having a select signal input terminal SE.
When a select signal is input to L and data can be read or written, a ready signal is output from the ready signal output terminal READY, as is well known.

Here, among the first access terminals of the DP-RAM 60, the select signal input terminal SEL is connected to the select signal output terminal of the decoder llb, and the read/write signal input terminal R/'W is connected to the CPU 1 via the control bus 30b.
The ready signal output terminal READY is connected to the ready signal output terminal READY of the CPU 10b via the status bus 33b, and the 11-bit address terminals Al0-AO are connected to the read/write signal output terminal R/W of the CPU 10b.
It is connected to the lower 11 bits of the address bus 31b, and the 8-bit data terminal D7-Do is connected to the data bus 32b. On the other hand, among the second access terminals of the DP-RAM 60, the select signal input terminal SEL is connected to the select signal output terminal of the decoder 61, and the read/write signal input terminal R/W is connected to the slave bus SB2 via the latch circuit 64b. The ready signal output terminal READY is connected to the control bus R/W, and the ready signal output terminal READY is connected to the ready signal line READY of the slave bus SB2 via the buffer amplifier 63b. It is connected to the lower 3 bits of the output terminals of the latch circuit 65b, and is connected to the lower 8 bits of the address terminals.
Pins 1-A7-AO are connected to the output terminals of the latch circuit 66b, and data terminals D7-DO are connected to the first terminals of the bidirectional buffer amplifier 67b.

When the input terminals of the latch circuits 65b and 66b, the second terminal of the bidirectional buffer amplifier 67b, and the address valid signal HAS fall from the H level to the L level, a latch signal is output to the latch circuit 65b and the 8-bit After latching the upper address of , the lower address valid signal LA
When S falls from the H level to the L level, a latch signal is output to the latch circuit 66b to latch the 8-bit lower address. At this time, the buffer amplifier 65b
The top 5 of the 8-bit high-order address output from
The address of the bit is input to the decoder 61. In response, the decoder 61 outputs a total of 16 bits of address output from the buffer amplifiers 65b and 66b to the input/output controller 1 based on the input 5-bit address.
The designated address corresponding to the lower layer MC designation signal input from 5b (in the case of this microcomputer 2, the second
As shown in the address map in the figure, C) 4000 to 0
This is an address up to 47FF. ), and if it is the designated address, outputs the gate oven signal to the bidirectional buffer amplifier 67b and outputs the gate oven signal to the buffer amplifier 67b.
7b, the output terminals of the gapped collector type buffer amplifiers 68b are connected in parallel, and the data buses AD7-AD of the slave bus SB2 are connected in parallel.
Connected to O. Here, the output side of the buffer amplifier 68b is connected to the oven collector because the slave bus S
The B2 data bus is connected in parallel with the slave bus SB3 data bus of another microcomputer 3, and since data collision occurs during reading, this is to avoid damage to the buffer amplifier at this time. Therefore, the CPU 10a in the microcomputer 1 monitors the data on the data bus AD7-ADO of the master bus MBI, and when it becomes oooooooo''', the CPU 10a of all the microcomputers 2 and 3 in the lower hierarchy
It can be detected that the process has been completed.

The upper address valid signal HAS and lower address valid signal LAS on the control bus of slave bus SB2 are
The signal is input to the decoder 61 via the buffer amplifier 64b. The decoder 61 opens the top one. by this,
The data terminal D7-Do of the DP-RAM 60 and the data bus D7-Do of the slave bus SB2 are connected via a bidirectional buffer amplifier 67b, and data can be exchanged between the DP-RAM 60 and the CPU 10a in the microcomputer l. Become. At this time, the buffer amplifier 65b is connected to the address terminals Al0-AO of the DP-RAM60.
The lower 3 bits of the 8-bit address output from the output terminal of
The bit address is input. For example, the upper layer C
When the PU attempts to read the address '08800', the decoder 61 outputs an enable signal to the buffer amplifiers 62 and 68b to enable the buffer amplifiers 62 and 68b, and outputs the processing status signal output from the input/output controller 15b. Data bus AD of slave bus SB2
7-Output to ADQ.

The input terminal of the buffer amplifier 55b, each output terminal of the buffer amplifiers 5'l'b, 52b, and 53b, and one terminal of the bidirectional buffer amplifier 54b are connected to the sensor 70a and the actuator 7 via the master bus MB2.
It is connected to an input/output controller 72a, which is an interface circuit between the microcomputer 4a and the microcomputer 2.

The input/output controller 72a includes a RAM therein, and when data can be read or written to the RAM, a ready signal is sent to the CP via the master bus MB2, the buffer amplifier 55b, and the status bus 33b.
Output to U10b.

The detection signal output from the sensor 70a is input to the input/output controller 72a via an analog/digital conversion (hereinafter referred to as A/D conversion) circuit 71a, and is temporarily stored in the RAM in the input/output controller 72a. After being stored in the microcomputer 2, the read/write signal R/W from the CPU IQb of the microcomputer 2 is sent to the input/output controller I.
When input to the roller 72a, the accumulated detection data is read out to the CPU 10b in the microcomputer 2 via the data bus of the master bus MB2, the bidirectional buffer amplifier 54b, and the data bus 32b.

The amplifiers 51c, 52c to 54c are connected to the master bus MB3.
It is connected to an input/output controller 72b, which is an interface circuit between the sensor 70b and the actuator 74b, and the microcomputer 3 via the microcomputer 3. This input/output controller 72b is the input/output controller 7 described above.
It operates similarly to 2a.

The detection signal output from the sensor 70b is output to the input/output controller 72b via the A/D conversion circuit 71b.
On the other hand, control data output from the input/output controller 72b is transmitted to the actuator 7 via a D/A conversion circuit 73b.
4b and predetermined control is performed.

An example of the operation of the control system of FIG. 1 configured as described above will be explained for each item below.

(1) When the CPU Oa writes data to the DP-RAM 60 (2) When the CPU 10a reads data from the DP-RAM 60 (3) Operation of the entire control system Meanwhile, an L-level read/write signal R from the CPU l0b
/W is input to the input/output controller 72a, C
The result data calculated by PUl0b is transferred to the data bus 32.
b1 bidirectional buffer amplifier 54b and master bus MB2
is input to the input/output controller 72a via the data bus of
/A conversion. ) is output to the actuator 74a via the circuit 73a and predetermined control is performed.

The microcomputer 3 in the lower hierarchy is configured similarly to the microcomputer 2. Here, the buffer amplifier 63C in the microcomputer 3 is connected to the slave bus SB.
Further, the input terminal of the latch circuit 64c is connected to the control buses S, LAS, and R/W of the slave bus SB3, and further,
Buffer amplifiers 65c to 68c are slave bus SB3
data buses AD7-ADO. In addition, the input terminal of the buffer amplifier 55c and the buffer (1) C
When the PUlOa writes data to the DP-RAM 60, the CPU 10a outputs an L-level read/write signal R/W instructing data writing to the DP via the control bus 30a1, buffer amplifier 51a, master bus MB, L slave bus SB2, and buffer amplifier 64b. -RA
The address of the DP-RAM 60 to which the data is to be output and written to the read/write signal input terminal R/W of the second access terminal of the M60 (this address is from address 04000 shown in the address map in FIG. 2). 047FF, and this address is referred to as "04100'" for convenience.) is output to the buffer amplifiers 52a and 53a via the address bus 31a, and then the data to be written is output via the data bus 32a. It is output to the buffer amplifier 54a. Buffer amplifier 52a.

53a and 54a are an upper address valid signal HAS and a lower address valid signal L output from the signal generation circuit 40a.
As shown in FIG. 4, the latch circuit 65b is controlled by the AS, and the upper address, lower address, and data are sent in the order of time division from the data bus of the master bus MBI to the data bus of the slave bus SB2 in the microcomputer 2. .

66b and a bidirectional buffer amplifier 67b.

Based on the address of the upper 5 bits of the 8 bits output from the buffer amplifier 65b, the decoder 61
A total of 16 bits of address "04100"' output from the buffer amplifiers 65b and 66b are designated addresses (04000 to 047F as described above) corresponding to the lower layer MC designation signal input from the input/output controller 15b.
This is the address up to F. ).

At this time, since it is a designated address, the decoder 61 outputs a gate open signal to the bidirectional buffer amplifier 67b to enable the buffer amplifier 67b and open the gate. As a result, data on the data bus of slave bus SB2 is transferred to DP'-R via buffer amplifier 67b.
Address 08 in the AM60 data terminal address map
The address ranges from 000 to 087FF, and for convenience, this address will be referred to as "08100"'. At this point, the actual write address to the DP-RAM 60 is the address "100" of the lower 11 bits.

The CPU 10a sends an H-level read/write signal R/W instructing data reading to the DP-R via the control bus 30a, buffer amplifier 51a, master bus MB L slave bus SB2, and buffer amplifier 64b.
The address of the DPRAM 60 from which the data is read and output to the read/write signal input terminal R/W of the second access terminal of the AM 60 (this address is from address 04000 to 0 shown in the address map in FIG. 2).
47FFF, and as mentioned above, the actual write address to the DP-RAM 60 is ''.
100", so it becomes 1"o4100") is sent to the buffer amplifiers 52a and 53 via the address bus 31a.
Output to a. It is input to the rose D7-Do. At this time, the address terminals Al0-AO of the DP-RAM60 have
The lower 3 bits of the 8-bit address output from the output terminal of the buffer amplifier 65b and the buffer amplifier 6
Since a total of 11 bits of the 8-bit address output from 6b (in this case, "100" in hexadecimal notation) is input, the above data is written to this specified address in the DP-RAM 60. .

The data written to DP-RAM60 is
As is known, data can be read out via the other first access terminal of the DP-RAM 60, and data can therefore be transferred from the CPU 10a to the CPU 10b.

(2) When the CPU 10a reads data from the DP-RAM 60, the CPU 10b writes the data to be transferred to the CPU 10a in the DP-RAM 60 in advance through the first access terminal as is known. At this time, the address outputted from the CPU 10b is controlled by the upper address valid signal πAS and the lower address valid signal LAS outputted from the signal generation circuit 40a, and the address amplifiers 52a and 53a shown in FIG. The upper address and the lower address are time-divisionally output from the data bus of the master bus MBI via the data bus of the slave bus SB2 in the microcomputer 2 to the latch circuits 65b and 66b.

Based on the address of the upper 5 bits of the 8 bits output from the buffer amplifier 65b, the decoder 61
A total of 16 bits of address "04100'' outputted from the buffer amplifiers 65b and 66b are designated addresses (04000 to 047F as described above) corresponding to the lower layer MC designation signal inputted from the input/output controller 15b.
This is the address up to F. ).

At this time, since it is a designated address, the decoder 61 outputs a gate open signal to the bidirectional buffer amplifier 67b, enables the buffer amplifier 67b, and opens the gate. As a result, the data read from the data terminal D7-DO of the second access terminal of the DP-RAM 60 is transferred to the data bus of the bidirectional buffer amplifier 67b1, the slave bus SB2, and the master bus MB in the microcomputer l.
1 data bus, bidirectional buffer amplifier 54a1 and data bus 32a.

Therefore, data can be transferred from the CPU 10b to the CPU 1Oa.

The data exchange operations between the input/output controller 72a and the microcomputer 2 and between the input/output controller 72b and the microcomputer 3 are also similar to the operations between the microcomputers 1 and 2 described above. .

FIG. 3 is a diagram showing the relationship between the address map of the microcomputer 1 in the upper hierarchy and the address map of the microcomputer 2.3 in the lower hierarchy.

As shown in FIG.
- When reading or writing data to the RAM 60, addresses from 04000 to 047FF are used;
toa is the DP-RAM in the microcomputer 3 (
Not shown.

), addresses from 04800 to 049FF are used. On the other hand, the CP in the microcomputer 2 in the lower hierarchy
When U10b writes data to be transferred to the microcomputer 1 into the DP-RAM 60, the address oso
Addresses from oo to 087FF are used, and
A CPU (not shown) in the microcomputer 3 in the lower hierarchy.

) transfers the data to be transferred to the microcomputer l.
- When writing to RAM (not shown), address 08000 to 087, like the microcomputer 2.
Addresses up to FF are used. In this embodiment, as shown in the address map in FIG. 2, addresses are assigned so that a maximum of eight microcomputers in the lower hierarchy can be connected to one microcomputer 1 in the upper hierarchy. Is going.

(3) A detection signal output from the operation sensor 70a of the entire control system is input to the input/output controller 72a via the A/D conversion circuit 71a,
Furthermore, a detection signal output from the sensor 70b is input to the input/output controller 72b via the A/D conversion circuit 71b. The data of the detection signal (hereinafter referred to as detection data) is transferred from the input/output controller 72a to the CPU 10b in the microcomputer 2, and the detection data from the input/output controller 72b is transferred to the CPU (not shown) in the microcomputer 3. ) will be forwarded to.

Between the CPU 10a in the microcomputer 2 and the CPU 10a in the microcomputer 1, and between the CPU (not shown) in the microcomputer 3 and the CPU 1Oa in the microcomputer 1, the above-mentioned Exchange of data takes place.

After this, the CPU1Ob finally operates the actuator 7.
The CPU in the microcomputer 3 calculates control data for controlling the actuator 74b.
Calculate control data to control. CPU10b
outputs the calculated control data to the actuator 74a via the master bus MB2, the input/output controller 72a1, and the D/A conversion circuit 73a to perform predetermined control. , is output to the actuator 74b via the input/output controller 72b1 and the D/A conversion circuit 73b to perform predetermined control. As described above, the sensor 70a,
Based on the detection signal detected by 70b, predetermined control is performed on actuators 74a and 74b.

In the control system of this embodiment, the CPU 10a in the microcomputer 1 in the upper hierarchy and each CPU in the microcomputer 2.3 in the lower hierarchy are connected to the DP-RAM.
Since data is exchanged by connecting via 5Q, the address bus and data bus within each microcomputer can be separated, allowing each microcomputer to operate independently. Can be done. Therefore, compared to the conventional example shown in FIG. 7, the processing speed within each microcomputer can be greatly improved.

In the control system shown in Fig. m1, the master bus MB2.3 of the microcomputer 2.3. MB3 and slave bus SB
2. Since the SB3 has the same configuration, it can be easily connected to external devices such as input/output controllers 72a and 72b and other microcomputers 1.

In the control system shown in Fig. 1, the case where there are two microcomputers in the lower hierarchy is explained, but the invention is not limited to this, and it is possible to connect multiple microcomputers to microcomputer l and exchange data. You can.

In the control system of FIG. 1, the upper layer microcomputer l is the lower layer microcomputer 2.
Although the master bus MBIO3 of the microcomputer 103 in the lower hierarchy does not have a slave bus and a module related to the slave bus compared to the microcomputer 114.
15 slave buses 5B114. Connected to SBI 15. Furthermore, the mask hash MB l 04 of the microcomputer 104 is the microcomputer 116.
117(') Raku slave bus 5B116 to 5B117
connected to.

The sensors 121 to 126 are connected to the master bus MBIII of the microcomputer 111, the master bus MBII3 of the microcomputer 113, the master bus B102 of the microcomputer 102; the master bus MBl14 of the microcomputer 114, respectively. Master bus MB116 of the microcomputer 116. and connected to the master bus MB117 of the microcomputer 117.

Further, the actuators 131 to 135 are connected to the master bus B112. of the microcomputer 112, respectively. Master bus MB113 of the microcomputer 113. Master bus MB102 of the microcomputer 102. It may have the same configuration as the microcomputer 12.3.

FIG. 5 is a block diagram showing an example of a control system equipped with microcomputers configured in three hierarchies. Second layer microcomputers 101 to 104 having the same configuration as the computer 2-3, third layer microcomputers 111 to 117 having the same configuration as the microcomputers 2 and 3, and a sensor 121 that performs predetermined detection. and actuators 131 to 135 that perform predetermined control in response to control data.

In FIG. 5, a master bus MB100 of the microcomputer 100 connects the microcomputers 101 to 1
04 slave buses 5BIOI to 5B104. Further, the master bus MB 101 of the microcomputer 101 is connected to the microcomputers 111 to 1.
13 slave buses 5BIII to 5B113, and 36 = 15 master buses MB115. and connected to the master bus MB117 of the microcomputer 117.

In the control system configured as described above, after processing such as predetermined arithmetic processing is performed by the 12 microcomputers 100 to 104, 111 to 117 based on the detection data input from the sensors 121 to 126, , the control data is the actuators 131 to 135
The signal is output to and predetermined control is performed.

Although the control system of FIG. 5 is configured with three hierarchies of microcomputers, the present invention is not limited to this, and the microcomputers may be configured with four or more hierarchies as required. Here, the microcomputers used in the fourth hierarchy and above have the same configuration as the above-mentioned microcomputer 2.3.

FIG. 6 is a block diagram showing an example in which the present invention is applied to a control system for a four-wheeled vehicle. This control system includes a vehicle control microcomputer 200 that is a microcomputer in an upper layer, and an input processing microcomputer 201 that is a microcomputer in a lower layer.
．． Engine control microcomputer 202. l-transmission control microcomputer 203. A suspension control microcomputer 204 and a brake control microcomputer 205 are provided.

In FIG. 6, a vehicle control microcomputer 20
0 master bus MB200 is slave bus 5B201.0 of input processing microcomputer 201. Slave bus 5B2 of the engine control microcomputer 202
02. ) Slave lotus 5B203. of the transmission control microcomputer 203. Slave bus 5B20 of the suspension control microcomputer 204
4, and the slave bus 5B205 of the brake control microcomputer 205.

The driving wheel rotation speed sensor 211 outputs the driving wheel rotation speed data to the input processing microcomputer 201 via the master bus MB201, and the driven wheel sensor 212 outputs the driven wheel rotation speed data to the input processing microcomputer 201 via the master bus MB201. The engine rotation speed sensor 213 further outputs the engine rotation speed data to the input processing microcomputer 201 via the master bus MB201. The intake air amount sensor 214 outputs intake air amount data to the input processing microcomputer 201 via the master bus MB201, and the throttle opening sensor 215 outputs the throttle opening data to the master bus MB201.
Input processing microcomputer 20 via B201
Furthermore, the vehicle speed sensor 216 outputs vehicle speed data to the input geography microcomputer 201 via the master bus MB201.

The input processing microcomputer 201 temporarily stores each input data in an internal RAM, and then outputs the data to the vehicle control microcomputer 200. The vehicle control microcomputer 200 temporarily stores each input data in an internal RAM, and then outputs the data to each of the microcomputers 202 to 205 as necessary.

The exhaust sensor 217 sends rich lean data to the master bus M.
It is output to the engine control microcomputer 202 via B202. The engine control microcomputer 202 controls the fuel to control the air-fuel ratio within a predetermined range based on input rich lean data and engine rotation speed data and intake air amount data input from the vehicle control microcomputer 200. After calculating the injection amount, a fuel injection amount control signal is output to the fuel injection valve 218.

The gear position sensor 219 sends gear position data to the master bus M.
The oil temperature sensor 220 outputs the oil temperature data to the transmission control microcomputer 203 via the master bus MB203. Transmission control microcomputer 20
3 is a transmission control circuit after calculating shift data based on the input gear position data and oil temperature data, as well as the throttle opening sensor and vehicle speed data input from the microcomputer 200 for car M[J]. 22
Output to 1.

The steering angle sensor 22 of the steering wheel outputs the steering angle data of the steering wheel to the suspension control microcomputer 204 via the master bus MB204, and the stroke sensor 223 outputs the stroke data to the master bus MB204.
Microcomputer 2 for suspension control via
Output to 04.

Further, the foot brake switch 225 outputs a foot brake on signal to the suspension control microcomputer 204 via the master bus 204 and to the brake control microcomputer 205 via the master bus MB, 205. The suspension control microcomputer 204 calculates suspension control data based on the steering angle data of the steering wheel, the stroke data, and the brake on number i that are input, and then outputs the data to the suspension control circuit 224.

Parking brake switch 226 outputs a parking brake on signal to brake control microcomputer 205 via master bus MB205. The brake control microcomputer 205 performs, for example, slip suppression based on the input foot brake on signal, parking brake on signal, and driving wheel rotation speed data and driven wheel rotation speed data input from the vehicle control microcomputer 200. After calculating the driving wheel brake control data for controlling the driving wheel brake control circuit 22
Output to 7.

In the control system shown in FIG. 6 described above, each microcomputer 202 to 2 for controlling the four-wheel vehicle is
An example of control of 05 is shown below.

[Effects of the Invention] As detailed above, according to the present invention, the arithmetic processing section of each microcomputer is connected to another microcomputer or an external device via the dual port RAM, so that each microcomputer is A block diagram showing an example in which the arithmetic processing units of a computer operate independently. FIG. 7 is a block diagram of a conventional control system.

1.2.3...Microcomputer, 10a, 10
b-CPU.

31a, 31b...address bus, 32a, 32b...data bus, 60...DP-RAM.

72a, 72b...input/output controller, MBI, M
B2. MB3...master bus, SB2. SB3...
slave bus.

Patent applicant Mazda Motor Corporation representative Patent attorney Aohaku Aoha has one person, and as a result, the processing speed of the arithmetic processing section of each microcomputer can be improved compared to the conventional example.

Furthermore, if the configurations of the master bus and slave bus of each microcomputer are the same, there is an advantage that connection with other microcomputers or external devices is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control system equipped with three microcomputers, which is an embodiment of the present invention. FIG. 2 is a diagram showing an address map of the microcomputer shown in FIG. 1. FIG. 3 is a diagram showing the address map of the microcomputer shown in FIG. 1. 4 is a timing chart showing the control of the data bus of the control system of FIG. 1,

Claims (2)

[Claims] (1) A control device consisting of a plurality of microcomputers, each microcomputer having at least a bus for communicating data between an arithmetic processing unit and other microcomputers or external devices, and the bus is a master bus that is directly connected to another microcomputer or external device and is directly controlled by the arithmetic processing section, and a master bus that is connected to another microcomputer or external device via a dual port RAM, and that is or a slave bus whose data communication is controlled by an external device. (2) A control device having a plurality of microcomputers according to claim 1, wherein the master bus and the slave bus have the same configuration.