JPH02192388A - Frequency deciding circuit - Google Patents

Abstract

PURPOSE:To accurately decide whether the frequency relation between a chrominance subcarrier and a synchronous signal is a prescribed relation or not by providing a deciding means to decide the frequency relation between the the chrominance subcarrier and the synchronizing signal. CONSTITUTION:A composite video signal is supplied to an input terminal 31, and the composite video signal is supplied to a subtracting circuit 32 and supplied to a 1 frame delay circuit 33. The composite video signal supplied to the circuit 33 is delayed by 1 frame, after that supplied to the circuit 32, and subtracted from the composite video signal to be supplied to the terminal 31. The subtracted result is supplied through a switch 34 to a deciding circuit 35, and the level of the result is compared with the level of a reference value. Further, a deciding signal to indicate whether the composite video signal supplied to the terminal 31 is a standard signal or a non-standard signal is outputted to an output terminal 36. Thus, it can be accurately decided whether the frequency of the chrominance subcarrier and the frequency of the synchronous signal have the prescribed relation or not without the influence of a noise or the change of video contents.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a frequency determination method for determining whether the frequency relationship between a color subcarrier of a video signal and a synchronization signal is in a predetermined relationship. Regarding circuits.

(Prior Art) In the NTSC system, which is Japan's standard television broadcasting system, two color signals 1. Q and one luminance signal Y as 1
In order to combine into one composite video signal, two color signals 1. Q
A composite video signal is obtained by orthogonally modulating the color subcarrier of frequency fsc and frequency multiplexing the modulated output and the luminance signal Y. The modulated color signal C and composite video signal Z are shown in the following equations (1) and (2), respectively.

C-1・cos (2π conflict fsc @
t)+Q-s in (2π・Esc-t) −
(1) z-y+c...
(2) Here, the relationship between the color subcarrier frequency Esc and the horizontal synchronization frequency fHs field frequency fVs frame frequency f is expressed by the following equations (3), (4), and (5).

fsc-(455/2)-fH-(3)fH=(52
5/2) ・fv −(4)fv”2fp
-(5) By the way, as mentioned above, the luminance signal Y
When frequency multiplexing and transmitting the color signal C, it is necessary to separate the luminance signal Y and the color signal C on the receiving side.

As a Y/C separation circuit that separates the luminance signal Y and the color signal C, there is, for example, a circuit using a band pass filter (hereinafter referred to as BPF). That is, the center frequency Esc
The luminance signal Y and the color signal C are separated by extracting the color signal C from the composite video signal Z using the BPF and subtracting this extracted output from the composite video signal.

However, in the case of a configuration using this BPF, the luminance signal Y having a frequency near tsc is extracted as the color signal C, so cross color (a phenomenon in which the luminance signal Y leaks into the color signal C) and a decrease in resolution occur. It will happen.

Such a problem does not occur in a three-dimensional Y/C separation circuit. This three-dimensional Y/C separation circuit is shown in FIG.

The illustrated Y/C separation circuit uses a frame memory 12 and a subtraction circuit 13 to determine the difference between frames of the composite video signal supplied to the input terminal 11, and also uses a line memory 14 and a subtraction circuit 15 to determine the difference between the frames of the composite video signal supplied to the input terminal 11. Further, the motion detection circuit 16 detects the motion of the image for each pixel, and if the motion detection circuit 16 determines that the image is a moving image, the mixer circuit 17 selects the inter-line difference output and outputs a still image. If it is determined that the image is a picture, the inter-frame difference output is selected to output the color signal C to the output terminal 18.

According to this three-dimensional Y/C separation circuit, in a still image, subtraction is performed between pixels at the same position on the screen of the nth (n is a positive integer) frame and the (n+1)th frame, so There is no color or loss of resolution.

That is, from equations (3), (4), and (5), fsc and fF
The relationship with is fsc-(455kai525/2)fp-・c6). From this, it can be seen that the polarity of the color subcarrier is reversed between the n-th frame and the (n+1)-th frame. Therefore, if the composite video signal Z of the n-th frame is expressed by equation (2), the composite video signal Z' of the (n+1)th frame is expressed by the following equation 4%. ' is sampled at a frequency of 4 f sc. According to this figure, it can be seen that Y/C separation can be performed by performing the processing of the following equations (8) and (9).

Y-(Z+Z')/2......(8)C-(Z
-Z')/2... (9) As mentioned above, in order to prevent cross color interference and resolution degradation, Y/C
It is better to use a three-dimensional Y/C separation circuit as the separation circuit.

By the way, from the explanation of equation (6) above, in order for Y/C separation to be possible with a three-dimensional Y/C separation circuit, equation (3) must be satisfied.
), (4), and (5) must hold true.

However, at present, there are composite video signals that do not satisfy the above relationship, such as composite video signals from video tape recorders (hereinafter referred to as VTRs). Therefore, in order to perform three-dimensional Y/C separation, the composite video signal is expressed as shown in equation (3).

It is necessary to determine whether the relationships (4) and (5) are satisfied.

A conventional circuit for making this determination is shown in FIG.

Note that in the following explanation, equation (3) will be used.

A composite video signal that satisfies the relationships (4) and (5) is referred to as a standard signal, and a composite video signal that does not satisfy the relationships is referred to as a non-standard signal.

In FIG. 10, an input terminal 21 is supplied with a clock CK1 having a frequency of 2fsc, which is reproduced from a reference clock. This clock CK1 is divided into 455-5 by the frequency dividing circuit 22.
After being frequency-divided by 25, it is supplied to the phase comparator circuit 23. On the other hand, the input terminal 24 is supplied with a frame pulse FP reproduced from the composite video signal. This frame pulse FP
resets the frequency divider circuit 22 and is also supplied to the phase comparator circuit 23. This phase comparator circuit 23 is a frequency divider circuit 2
The phases of the frequency-divided output of 2 and the frame pulse FP are compared, and when they match, a high level signal is supplied to the output terminal 25, and when they do not match, a low level signal is supplied to the output terminal 25. Therefore, if the output of the phase comparison circuit 23 is at a high level, it can be determined that the composite video signal is a standard signal, and if the output is at a low level, it can be determined that it is a non-composite video signal.

In the case of the configuration shown in FIG. 10, if the jitter of the frame pulse FP becomes larger than one period of the clock CK, an erroneous determination occurs. Therefore, the jitter of frame pulse FP needs to be smaller than one cycle of clock CKl.

However, frame pulse FP is easily affected by noise and changes in video content, and its jitter range is limited to 1 of clock CK.
It is difficult to fit within the period.

Therefore, in conventional circuits, erroneous judgments occur when there is a lot of noise or when the video content changes rapidly.

(Problems to be Solved by the Invention) As described above, in conventional frequency determination circuits, the frame pulse FP is easily jittered due to the influence of noise and changes in video content, so there may be a lot of noise or There is a problem in that when the value changes, erroneous judgments are likely to occur.

Therefore, the present invention provides a frequency determination method that can accurately determine whether or not the frequency relationship between the color subcarrier transmission and the synchronization signal is in a predetermined relationship even when there is a lot of noise or the video content changes rapidly. The purpose is to provide circuits.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention calculates the difference between n (n is a positive integer) lines of a composite video signal only for the synchronization signal part, and According to the level of the calculation result, it is determined whether the color subcarrier frequency of the composite video signal and the synchronization signal frequency have a predetermined relationship.

(Function) According to the above configuration, the phase of the synchronization signal is always constant without being affected by noise or changes in video content. Therefore, when the frequency relationship between the carrier color signal frequency and the synchronization signal frequency is in a predetermined relationship, the differential output becomes O. On the other hand, if the predetermined frequency relationship does not exist, the differential output will not become O. Therefore, it is possible to determine whether or not a predetermined frequency relationship exists according to the level of the differential output.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, an input terminal 31 is supplied with a composite video signal. This composite video signal is supplied to a subtraction circuit 32 and also to a one frame delay circuit 33.

The composite video signal supplied to the one-frame delay circuit 33 is delayed by one frame, and then supplied to the subtraction circuit 32 and subtracted from the composite video signal supplied to the input terminal 31.

This subtraction result is supplied to the determination circuit 35 via the switch 34, and is compared in level with a reference value. As a result, a determination signal indicating whether the composite video signal supplied to the input terminal 31 is a standard signal or a non-standard signal is output to the output terminal 16.

The 1-frame delay circuit 33 is a shift register with 2, 455, and 525 stages, and has a clock CK of frequency 4f and C.
Driven by 2. As a result, the delay amount for one frame is obtained as shown in the following equation (10).

(1/4fsc)・2・455・525-1/ f p
(10) The clock CK is generated by the clock generation circuit 37 in synchronization with the color burst signal.

A control signal SW for controlling on/off of the switch 34 is generated by a control signal generation circuit 38.

This control signal generation circuit 38 generates a control signal SW in synchronization with the composite video signal. This control signal SW is a pulse signal that remains at a high level for a predetermined period of time in a vertical period. When the composite video signal is a standard signal, the high level period of the control signal SW is set to fall within the vertical synchronization signal period of the composite video signal.

FIG. 2 is a circuit diagram showing an example of a specific configuration of the determination circuit 35.

After unnecessary components are removed from the output of the switch 34 by an LPF 351, the absolute value is taken by an absolute value circuit 352. The output of the absolute value circuit 352 is integrated by an integrating circuit 353, and then compared in level with a reference value supplied to a terminal 356 by a comparing circuit 355.

This comparison result is latched by the latch circuit 357 in accordance with the latch pulse supplied to the terminal 358, and is supplied to the output terminal 36 as a determination signal. Note that the integration circuit 353 is reset every several frames by a reset pulse supplied to the terminal 354, and the comparison output is latched in the latch circuit 357 immediately before this reset.

FIG. 3 is a circuit diagram showing an example of a specific configuration of the control signal generation circuit 38.

The illustrated circuit includes a phase comparison circuit 382, a loop filter 3
83, voltage controlled oscillation circuit (hereinafter referred to as vCO) 384
, a horizontal counter 385 synchronizes the oscillation output of the VCO 384 with the synchronization signal separated by the synchronization separation circuit 381 from the composite video signal, and counts the oscillation output of the VC0384. A control signal SW is output by performing a logical operation on the count output by a logic circuit consisting of AND circuits 386, 387 and a JK flip-flop circuit 388.

Here, the operation in FIG. 1 will be explained with reference to FIGS. 4 and 5.

FIG. 4 is a waveform diagram showing signal waveforms of various parts when the composite video signal is a standard signal, and FIG. 5 is a waveform diagram when the composite video signal is a non-standard signal.

When the composite video signal is a standard signal, that is, when the composite video signal satisfies the above equations (3), (4), and (5),
The vertical synchronization signal VD of the composite video signal one frame before, which is output from the one frame delay circuit 33, is as shown in FIG.
As shown in b), it has the same phase as the vertical synchronizing signal VD of the composite video signal of the current frame supplied to the input terminal 31.

As a result, the interframe difference output from the subtraction circuit 32 becomes 0 during the vertical synchronization signal period. This is supplied to the determination circuit 35 via the switch 34 while the control signal SW shown in FIG. 4(d) is at a high level. As a result, the output of the switch 34 supplied to the determination circuit 35 is
As shown in FIG. 4(e), the value becomes O, and the integrated output never exceeds the reference value. Therefore, in this case, the determination circuit 35 outputs a determination result that the signal is a standard signal.

On the other hand, when the composite video signal supplied to the input terminal 11 is a non-standard signal, this composite video signal is expressed by the above equation (3), (
4) and (5) are not satisfied, the phase of the vertical synchronization signal VD of the composite synchronization signal one frame before outputted from the one frame delay circuit 33 is shown in FIGS. 5(a) and (b). As a result, the phase of the composite synchronization signal of the current frame supplied to the input terminal 31 does not match the vertical synchronization signal VD.

As a result, the differential output is as shown in FIG. 5(d).
Even the vertical synchronization signal part does not become 0. As a result, the input signal of the determination circuit 35 does not become 0 during the period when the control signal SW is at the /X level. As a result, a determination result indicating that the integral output exceeds the reference value and is a non-standard signal is obtained.

As described above, this embodiment calculates the difference between frames of a composite video signal and monitors the level of this difference output in the vertical synchronization period and in the vertical synchronization signal portion.
It is designed to perform non-standard judgments.

With this configuration, the phase of the vertical synchronization signal VD is constant regardless of noise or changes in video content, so even if there is a lot of noise or the video content changes drastically, it is possible to accurately determine standard/non-standard. can be done.

Further, according to the above configuration, the output of the subtraction circuit 32 can be used as the inter-frame difference output of the three-dimensional Y/C separation circuit.

FIG. 6 is a circuit diagram showing the configuration of a second embodiment of the invention.

In this embodiment, a sync separation circuit 41 is provided to separate a vertical sync signal VD from a composite video signal supplied to an input terminal 31, and an inter-frame difference of the sync separation output of this sync separation circuit 41 is obtained. be.

According to such a configuration, since the differential output does not include the differential output of the picture portion, the gate switch 34 as shown in FIG. 1 described above becomes unnecessary.

Further, since the difference between the synchronization separation outputs is obtained, as long as the synchronization separation outputs are stable, determination can be made without being affected by noise in the picture area.

FIG. 7 is a circuit diagram showing the configuration of a third embodiment of the present invention.

In this embodiment, a switch 42 is provided, and the synchronous separation output of the synchronous separation circuit 41 is selected as the manual power of the inter-frame difference calculating section only during the period when the switch 34 is turned on, and the synchronous separation output of the synchronous separation circuit 41 is supplied to the input terminal 31 during the other period. The system is designed to select a composite video signal.

According to such a configuration, like the embodiment shown in FIG.
It goes without saying that the judgment can be made without being affected by the noise of the picture period, and as in the embodiment shown in FIG.
It is possible to obtain the effect that the subtraction output of the subtraction circuit 32 can be used as the inter-frame difference output of the three-dimensional Y/C separation circuit.

Although several embodiments of the present invention have been described above, the present invention is not limited to the embodiments as described above.

For example, in the previous embodiment, a case was described in which it is determined whether fsc and fp (or fv) have a standard relationship, but this invention determines whether fsc and fH have a standard relationship. Of course, this method can also be applied to the case of determining. In this case, the difference between lines may be determined by setting the delay amount of the delay circuit to one horizontal period.

Furthermore, the present invention may be modified to calculate the difference between m (m is a positive integer) lines.

It goes without saying that this invention can be modified in many other ways without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is always possible to accurately determine whether or not the tsc and the synchronization signal frequency have a predetermined relationship, without being affected by noise or changes in video content. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing an example of a specific configuration of the determination circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing an example of a specific configuration of the control signal generation circuit, and FIGS. 4 and 5 are FIG. 1 is a signal waveform diagram for explaining the operation, FIG. 6 is a circuit diagram showing the configuration of a second embodiment of the present invention, FIG. 7 is a circuit diagram showing the configuration of a third embodiment, FIG. 8 is a circuit diagram showing the configuration of a three-dimensional Y/C separation circuit, FIG. 9 is a diagram for explaining the operation of FIG. 8, and FIG. 10 is a circuit diagram showing the configuration of a conventional frequency determination circuit. be. 31...Input terminal, 32...Subtraction circuit, 33...
1 frame delay circuit, 34.42... switch, 3.
5... Judgment circuit, 36... Output terminal, 37... Clock generation circuit, 38... Control signal generation circuit, 41...
...Synchronization separation circuit. Figure 1 Applicant's agent Patent attorney Takehiko Suzue Figure fsc Figure Figure

Claims (1)

[Claims] The difference between n (n is a positive integer) lines of a composite video signal,
The present invention includes a difference calculation means for calculating only the synchronization signal portion, and a determination means for determining whether or not the frequency relationship between the color subcarrier and the synchronization signal is in a predetermined relationship according to the output level of the difference calculation means. Characteristic frequency determination circuit.