JPH02192272A - Video image reduction circuit - Google Patents

Abstract

PURPOSE:To obtain a reduced picture without demodulation of a chroma signal and frequency conversion by using a 2nd sampling means to extract a color subcarrier sampled by a 1st sampling means while keeping the phase relation with the color subcarrier in matching with the reduction rate. CONSTITUTION:A luminance signal y2 and a chroma signal d2 being outputs of A/D converters 211, 311 are written in memories 212, 312 by write control circuits 213, 313 with sampling clocks f3, f4 respectively. That is, the luminance signal y2 for a period of 1/m (m is an integer being 2 or over) of that of a luminance signal y1 and the chroma signal d2 for a period of 1/m of that of a chroma signal d1 are written respectively in the memories 212, 312. When the written signals are read by readout control circuits 214, 314 from the memories 212, 312 respectively synchronously with the pulse signal f2, then a luminance signal y3 and a chroma signal d3 are obtained. Thus, a reduced picture is obtained without demodulating the chroma signal and applying frequency conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for displaying one or more originally reduced images on a television screen.

[Conventional technology]

In a composite video signal, the color information is a signal subjected to quadrature two-phase modulation, so the reduction of the video cannot be achieved by simple thinning sampling. Therefore, conventionally, one of the following two methods has been used.

The first method is widely used, in which the chroma signal is demodulated, the original color signal is reproduced, and then thinning sampling is performed (for example, "Television Technology", published by Denshi Gijutsu Publishing, July 1986 issue). p89-94).

The second method is to convert the color subcarrier frequency of the chroma signal in advance at the same ratio as the video reduction ratio, and restore it to the original value by thinning sampling. In the case of NTSC, the color subcarrier frequency is 3
．． 58MHz, if you want to reduce it by 1/2 now, it will be 1/2
．． All you have to do is convert it to 79MHz. However, after thinning, it is necessary to restore not only the frequency but also the phase information ("Television Technology J January 1987 issue, p. 20 to p. 24).

[Problem to be solved by the invention]

Among the conventional reduction circuits described above, the first method is suitable for mounting on a television. This is because televisions originally require demodulated color signals. However, when installed in a VTR or AV amplifier, etc., the right angle 2
A phase modulator is required. It is wasteful to use a demodulator and a converter to finally obtain a chroma signal, and there is a drawback that color shift is likely to occur during the demodulation/modulation process.

The second method is difficult to preserve phase information during frequency conversion,
The reduction ratio is substantially fixed to one. That is, there is a drawback that the reduction ratio cannot be made variable.

[Means to solve the problem]

The video reduction circuit of the present invention includes a first sampling means for obtaining a first data series by sampling the chroma component of the input video signal at a sampling frequency n times the color subcarrier (n is an integer of 3 or more). , when the reduction ratio of the video is 1/m (m is an integer of 2 or more), extract one set every m from the data set series in which the first data series is divided into n units, and create the second data series. a second sampling means for obtaining a luminance component of the input video signal at one of the sampling frequency;
a third sampling means for obtaining a third data series by sampling at a frequency of /m; and after once storing the second and third data series in a memory, each data series is stored in a frequency cycle of the sampling frequency; and an output means for outputting the output.

[Effect]

extracting from the first data series related to the color subcarriers an amount corresponding to the reduction rate while maintaining the phase relationship with the color subcarriers to obtain a second data series and storing it in a memory;
The luminance component is also sampled according to the reduction ratio to obtain a third data series and stored in the memory, and the stored second data series. The third data series is output as an output video signal at the sampled frequency.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the video reduction circuit of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment of FIG.

The Y/C separation circuit 101 receives an input video signal S1 and separates it into a luminance signal y1 and a chroma signal d1. The subcarrier generation circuit 102 receives the input video signal S1 and generates a color subcarrier f1 synchronized with the color burst of the input video signal. A quadrupling circuit 103 multiplies the color subcarrier f1 by four and outputs a pulse signal f2. The m-ary counter 104 is set in advance to be a ternary counter in this embodiment, and counts the color subcarrier f1 and outputs the carrier signal f every three counts.

Output. The gate circuit 105 outputs the pulse signal f2 as the sampling clock f4 while the carrier signal f is output. The m frequency divider 106 is preset to divide the frequency by 3, and divides the frequency of the pulse signal f2 by 3 and outputs the frequency as the sampling clock f. The A/D converter 211 converts the luminance signal y1 into a sampling clock f,
The luminance signal y2 is sampled, A/D converted, and output to the memory 212 as a luminance signal y2. The write control circuit 213 is
Luminance signal y! is written into the memory 212 in synchronization with the sampling clock fs. The read control circuit 214 reads the luminance signal y2 written in the memory 212 from the memory 212 in synchronization with the pulse signal f, and outputs it as the luminance signal y. The D/A converter 215 performs D/A conversion on the luminance signal y in synchronization with the pulse signal f2, and outputs it as a luminance signal y4. The A/D converter 311 samples the chroma signal d1 using the sampling clock f4, performs A/D conversion, and stores the chroma signal d2 in the memory 312.
Output to. The write control circuit 313 sends the chroma signal d2 to the memory 312 in synchronization with the sampling clock f4.
write to. The read control circuit 314 is connected to the memory 312
The chroma signal d2 written in is read out from the memory 312 in synchronization with the pulse signal f2 and output as the chroma signal d. The D/A converter 315 receives the pulse signal f2
The chroma signal d is subjected to D/A conversion in synchronization with the chroma signal d, and is output as a chroma signal d4. The Y/C mixing circuit 107 mixes the luminance signal y4 and the chroma signal d4 and outputs the mixture as an output video signal S2.

Next, the operation of this embodiment will be explained with reference to FIG.

Assuming that the chroma signal dl is sampled with the pulse signal f2, the chroma signals C1+c2+ to c23. ~ becomes. Also, assuming that the luminance signal y1 is sampled with the pulse signal f2, the luminance signal Z l hZ2h ~ +22
It becomes S+~. Since the carrier signal f3 is output for the period of the color subcarrier f1 every three counts of the color subcarrier f1, the gate circuit 105 becomes active during that period, and the pulse signal f2 is output as the sampling clock f4. The phase of the sampling clock f4 is defined at a predetermined position from the rising edge of the color subcarrier f1. For example, chroma signal CI+C
The rising edge of signal No. 13 coincides with the rising edge of color subcarrier f1. The luminance signal 721 and chroma signal d2, which are the outputs of the A/D converters 211 and 311, are the sampling clock f.
The signals are written into the memories 212 and 312 by the write control circuits 213 and 313 at s and f4, respectively. That is, the luminance signal y2 of only 173 periods of the luminance signal y1,
Note that the chroma signal d2 is only for 1/3 of the period of the chroma signal d1! 7212° and 312, respectively. When the read control circuits 214 and 314 read out the written information from the memories 212 and 312 in synchronization with the pulse signal f2, the luminance signal y1. The signal becomes di. In other words, the luminance signals z1~Z2+~, z231~ are reduced to 1/3, and the chroma signals CI+ C2+~c2
1. .about. is reduced to ⅓ while maintaining a constant phase relationship with the color subcarrier f1.

In this embodiment, the quadrupling circuit 103 is used, but it may be 3 times or more, and although the m-adic 1m frequency division is set to 3, it may be 2 or more depending on the reduction ratio.

The problem with this embodiment is that even though the sampling points of the luminance signal and the chroma signal are shifted, they are output at the same timing. Therefore, when considering the frequency band of color information included in the chroma signal, we found that in general receivers, the R-Y signal is 0.5MHz, the B-Y signal is 0.5MHz, and the B-Y signal is 0.5MHz.
A signal band of 0.5 MHz is used. On the other hand, the brightness has a band of 3 MHz or more. Therefore, the color signal change is about 1/6 of the brightness signal change, and the reduction ratio is 172.
There is no problem if it is about 174.

FIG. 3 is a block diagram showing a second embodiment of the invention.

Compared to the first embodiment, this embodiment has features in the parts up to the write control circuits 213 and 313, and a means for smoothing the image quality of the reduced image is added, but the other features are the same as in the first embodiment. It is the same as the example.

Regarding the luminance signal y1, the Y/C separation circuit 101 and the A/
A low pass filter 216 is inserted between the D converter 211 and the D converter 211 . Regarding the chroma signal d1, the shift register 316 delays the chroma signal d2 output from the A/D converter 311 by four pulses of the pulse signal f2, and outputs an output d5. The shift register 317 further delays the output of the shift register 316 by four pulses of the pulse signal f2 and outputs an output d. Adder 318 adds chroma signal d2 and output d6 of shift register 317. The averaging circuit 319 converts the addition result of the adder 318 into 172
output the average value. Adder 320 is averaging circuit 31
The output of 9 and the output d are added.

The averaging circuit 321 halves the addition result of the adder 320 and outputs an average value d. The m-adic counter 104 and the m-frequency divider 106 are each preset to ternary and frequency division by 3 as in the first embodiment. Therefore, write control circuit 2
13, 313 are luminance signals y2. Average value d7
is written into the memories 212 and 312.

Since the shift registers 316 and 317 are shifted by four pulses of the pulse signal f2, each sample data added by the adders 318 and 320 is at the same phase position from the reference phase f1, and the phase information is not disturbed. do not have.

FIG. 4 is a block diagram of another additional means for smoothing the image quality of the reduced image. This means is used by being inserted between the memory 312 and the D/A converter 315 in FIGS. 1 and 3. The configuration of this will be explained below. The output of the memory 312 is connected to one input of the adder circuit 403 and the shift register 401.
connected to.

The output of shift register 401 is connected to one input of adder circuit 406 and shift register 402 .

The output of shift register 402 is connected to the other input of adder circuit 403. The output of the adding circuit 403 is sent to the averaging circuit 404. Addition circuit 40 through polarity inversion circuit 405
6 is connected to the other input of 6.

The output of the adder circuit 406 passes through the averaging circuit 407 to D
/A converter 315. shift register 401
, 402 are configured to shift by two pulses of the pulse signal f2.

Next, the operation of this will be explained. Basically, it performs the same operation as the signal smoothing circuit composed of shift registers 316, 317 and adder circuits 318, 320 in FIG. The difference is that the number of shifts in the shift register is changed from 4 pulses to 2 pulses. When the number of shifts is two pulses, the positions of the input data of the adder circuit 403 and the output data of the shift register 401 are shifted by 180 degrees from the reference phase. Therefore, after averaging the output of the adder circuit 403, the polarity is inverted to artificially match the position from the reference phase.

The reason why the number of pulses of the shift register is shortened as described above is to prevent the band of the RF signal from becoming narrower than necessary. Comparing the bands of chroma signals on the write side and the read side of the memory 312, the band on the read side becomes wider in accordance with the reduction ratio. For example, if the reduction ratio is 172, the reading side will have twice the bandwidth. Therefore, it is necessary not to limit this band too much.

〔Effect of the invention〕

As explained above, the present invention allows the second sampling means to extract the color subcarrier sampled by the first sampling means according to the reduction ratio while maintaining the phase relationship with the color subcarrier, thereby producing a chroma signal. It is possible to obtain a reduced image without demodulating or frequency converting the chroma signal, which has the effect of reducing costs.Also, methods that demodulate and modulate chroma signals require hue matching during demodulation and modulation, but this method The invention does not require this and has the effect of reducing the number of adjustment steps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the video reduction circuit of the present invention, FIG. 2 is a time chart showing the operation of the embodiment of FIG. 1, and FIG. 3 is a block diagram showing the second embodiment. It is a diagram. FIG. 4 is a block diagram that is effective when added to FIGS. 1 and 3. 101...Y/C separation circuit, 102...
・Subcarrier generation circuit, 103... Quaternary multiplier circuit, 104... m-ary counter, 105...
...Gate circuit, 106...m frequency divider, 107
...Y/C mixer, 211°311...
・A/D converter, 212, 312...Memory,
213, 313...Write control circuit, 214
．． 314... Readout control circuit, 215°31
5...D/A converter, 216...Low pass filter, 316.317...Shift register, 318.320...Adder, 319,3
21... Averaging circuit, 401, 402...
...Shift register, 403.406...Addition circuit, 404,407...Averaging circuit, 405
...Polarity reversal circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] A first sampling means for obtaining a first data series by sampling a chroma component of an input video signal at a sampling frequency n times the color subcarrier (n is an integer of 3 or more); When the reduction rate of is 1/m (m is an integer of 2 or more), the first
a second sampling means for obtaining a second data series by extracting one set every m sets from a data set series in which n data series are divided;
a third sampling means for obtaining a third data series by sampling at a frequency of /m; and after once storing the second and third data series in a memory, each data series is stored in a frequency cycle of the sampling frequency; and an output means for outputting an image.