JP2997961B2 - Digital chroma signal encoder circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital chroma signal encoder circuit used in a video camera or the like.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional analog chroma signal encoder circuit.

In FIG. 4, reference numeral 11 denotes an image pickup unit of, for example, a video camera. The image pickup output of the image pickup unit is subjected to A / G / G / A correction after necessary processing by a CDS / AGC / gamma processing circuit 12, and then A / A / G / A correction is performed. The digital signal is sampled by the D converter 13 at the same sampling frequency as the clock frequency _fCK of the imaging unit 11 and converted into a digital signal. The digital signal processor (DSP) 14 converts the luminance signal Y and the color difference signals RY and BY into digital signals. And converts it into an analog signal by the D / A converter 15.

The color difference signals RY and BY other than the analog luminance signal Y are modulated in an analog encoder 16 by first and second subcarriers SC1 and SC2 whose phases are different from each other by 90 °. , Burst flag pulse
The chroma signal C is generated by mixing the burst signals generated from the (BFP).

FIG. 5 is a circuit diagram of an encoder for a digital chroma signal corresponding to the above-described analog chroma signal, and FIG. 6 is a diagram showing waveforms at various parts thereof.

In FIG. 5, for example, a CC of a video camera
D half the clock frequency f _CK for driving the charge-coupled device (), 1 / 2f _CK digital color difference signal R-Y of, B-Y
Are latched by a latch circuit (L) 25 driven by a clock signal (B). The clock signal (B) is obtained by delaying the signal (A) obtained by delaying f _CK / 2 by a delay time τ of several ns by the delay circuit (DL) 23 and quadrupling the subcarrier f _SC by the latch circuit (L) 24. of is obtained by latching the frequency 4f _SC, the output of the latch circuit (L) 25 (C) is f _CK / 2 and 4f _SC of noise at the phase difference overlap occurs, its location is latched by thinning The generation of noise is prevented.

[0007] The above, by the output (C) is mixing circuit 26 after mixing the burst flag pulse (BFP), is latched by the latch circuit (L) 27, the frequency of 4f _SC R-
The digital color difference signal (D) of Y, BY is obtained.

After the color difference signals-(RY) and-(BY) are generated by the color difference generation circuits 28A and 28B, the switch circuit
29, the color difference signals RY, BY,-(RY),-(B
−Y) is switched according to the control signals (E) and (F) to obtain a balanced modulated chroma signal (G). Here, the control signals (E) and (F) are obtained by dividing the frequency 4f _SC by the frequency divider 30 by 1 /.
4 and the latched signal (L) 31
° The signal is phase shifted.

The chroma signal (G) is, for example, a color difference signal RY, BY,-(RY),-
(BY), and when the image is of the PAL system, the color difference signal RY and-(RY) are inverted every other horizontal line.

[0010]

However, the configurations of the encoder circuits shown in FIGS. 4 and 5 have the following problems. That is, (a), in the configuration of the analog encoder circuit of FIG.
Even if it becomes, there are many peripheral capacitors, filters, etc.
In addition, a clamp circuit is required for DC reproduction, and the accuracy is reduced due to an offset or the like generated due to the clamp circuit. Therefore, a correction circuit is required, and S / N is inferior to digital signal processing.

[0011] (b), in the configuration of a digital encoder circuit of FIG. 5, when converting the frequency from f _CK to 4f _CK, by thinning out the overlap by comparing both phase, since replaced by one previous data, Digital color difference signal (D) shown in FIG.
As shown in the hatched area, there are places where some fields are thinned out or some areas are not thinned out, resulting in a phenomenon that the image surface is glaring between fields or between frames.

This phenomenon is caused by, for example, f
_This is because 4f _SC differs from _{CK in} phase depending on the field. If the phase of the course NTSC system is always constant, but the accuracy and 4f _SC of the latch circuit (L) 24, 25 in FIG. 5
Considering the jitter of, it is considered that the glare phenomenon occurs similarly.

Further, when the character mix circuit 21 and the blanking mix circuit 22 are provided before the frequency conversion as shown in FIG. 5, the edges of these characters and the screen side become glaring. Also, these circuits 21 and 22, for mixing in the digital luminance signal Y of f _CK, for example f
After frequency-converting the digital chrominance signal of _CK / 2 to 4f _SC and mixing characters and blanking signals,
A phase shift or a glare phenomenon occurs between the character of the luminance signal Y and the blanking signal.

(C) Control signal for switch circuit 29 in FIG.
(E) and (F) simply use a signal obtained by dividing the frequency of 4f _SC by で, so that the chroma signal (G) obtained by balanced modulation is f
The phase of the horizontal synchronization signal for _SC cannot be adjusted.

[0015] The present invention is, in view of the conventional problems as described above, to reduce the glare of the edge without the need for adjustment with a high precision, digital that enables phasing of the horizontal synchronizing signal for the subcarrier f _SC It is an object of the present invention to provide a digital chroma signal encoder circuit by signal processing.

[0016]

According to the present invention, a digital chrominance signal of f _CK / 2 is band-limited using a digital LPF (low-pass filter), and then converted to a digital chrominance signal of frequency 4f _SC to perform digital balanced modulation. Thus, a chroma signal is generated.

The color difference signal input to the digital LPF is a signal obtained by time-dividing RY and BY by the frequency of f _CK into one, and the clock frequency of the digital LPF is equivalent to f _CK. / 2.

Further, the frequency conversion from said f _CK to 4f _SC is by inserting a digital LPF in the preceding stage, f _CK and 4f _SC
Compared to the phase, where sampling is not performed at 4f _SC where the phase matches, thinned out and interpolated with the previous data, and also serves as a circuit that clips blanking periods other than burst signals after balanced modulation It is. In addition, 4f _SC
Is divided into f _SC every four fields in the NTSC system and every eight fields in the PAL system.

[0019]

According to the present invention, for example, a character mix or a blanking mix is composed of a digital LPF and f _CK / 2.
Since the processing is performed before the frequency conversion from ｆ to 4f _SC , it is possible to perform digital modulation that does not cause the glaring phenomenon of character edges and blanking edges, and
A composite video signal having no phase shift from the luminance signal can be obtained.

The color difference signals RY and BY have been conventionally subjected to BPF before frequency conversion in order to prevent mutual interference due to balanced modulation. However, the characteristics of a digital LPF inserted before frequency conversion are conventionally used. Is adjusted to the characteristics of the BPF, thereby realizing an encoder that can eliminate the glare phenomenon of the chroma signal edge between fields or between frames without deteriorating the image quality.

The digital LPF has a frequency of f _CK /
The digital color difference signals RY and BY are time-divided by the frequency f _CK and processed into a single signal, so that the number of circuits is reduced, and the frequency conversion circuit from f _CK to 4f _SC is also required.
Since the digital LPF is arranged at the preceding stage, the circuit scale is simplified. After balanced modulation, blanking periods other than the burst signal period are clipped, and the color difference signal flowing from the digital LPF into the blanking period is wiped out. Further, it is possible to obtain a high-quality composite video signal capable of adjusting the phase of the horizontal synchronization signal with respect to f _SC .

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 is a diagram showing the configuration of an encoder circuit for a digital chroma signal according to an embodiment of the present invention.
3 is a waveform diagram of a main part of FIG.

First, in FIG. 1, the same parts as those in FIG.
The digital color difference signals RY (A) and BY (B) of f _CK / 2 generated by the (DSP) 14 are alternately sampled by the color difference signal time division circuit 41 at the clock frequency f _CK ( C) is obtained.

The digital LPF is passed through a character mix circuit 42 and a blanking mix circuit (BL) 43.
Apply to 44. In this case, the signal is synchronized with the falling edge of the SEL signal (D) which has a phase with that of the signal (C). That is, by mixing in synchronism with the color difference signal RY, the generation of a pseudo signal in which edges are colored when the signal (C) is separated into RY and BY is prevented.

The digital LPF44, for example as shown in FIG. 3, by adding the signal delayed by two stages f _CK f _CK
/ 2 digital LPF. Here, the color difference signals RY and BY are about 1 to 1.
Bandwidth limited to 5MHz.

The output of the digital LPF 44 and the SEL signal (D) from the color difference signal time division circuit 41 are
Is supplied to, SEL signal (D) is latched by f _CK in the latch circuit (L) 451, a signal (F), and outputs the inverted signal (E) it. At this time, the signal (D) which is input to the frequency converter 45, the relationship between the time-division signal (C), the delay signal (C) is subjected to digital LPF44 is has become an even multiple of f _CK There must be.

The latch circuit (L) 452 converts the RY portion of the color difference signal time-divided by the color difference signal (E) into a latch circuit.
At (L) 453, the BY portion of the time-division color difference signal is latched by the signal (F) to obtain signals (G) and (H), respectively.

Further, the signal (G) is latched by the signal (F) in the latch circuit (L) 454 to obtain the signal (I). In this way, the generation of a false signal is prevented by matching the phases of the color difference signals RY and BY.

The signals (H) and (I) are obtained by converting the signal (F) into a delay circuit.
Using a signal (J) delayed by several ns in (DL) 455 and a signal (K) obtained by comparing the phase of 4f _SC with a latch circuit (L) 456, sampling is performed by latch circuits (L) 458 and 457, respectively. Obtain signals (M) and (L). From this, as in the case of FIG. 5, sampling is performed at 4f _SC to obtain frequency-converted color difference signals (O) and (N).
Generates a chroma signal.

The signals (P) and (Q) for controlling the digital balance modulator 46 are generated by the control signal generator 47. The difference from FIG. 6 is that the horizontal synchronizing signal HD and the vertical synchronizing signal VD , A field pulse is generated by a latch circuit (L) 471, a frame pulse is generated by a １ ／ frequency divider 472, and the switch circuit 473 uses the frame pulse in the case of NTSC and this frame pulse in the case of the PAL system. A pulse obtained by further dividing the frame pulse by に よ っ て by the divider 474 is selected, and its signal is used to select 1 / f of 4f _SC .
The phase of the horizontal synchronizing signal with respect to f _SC is adjusted by resetting the frequency divider 475.

That is, in the NTSC system, every 4f _SC ,
In the PAL system, the ４ frequency divider 475 is reset every eight fields. A frequency divider 476 is a 1/2 frequency divider of the horizontal synchronizing signal HD, and its output is a switch circuit (in the PAL system) for inverting and modulating the color difference signal RY for each horizontal line. SW) 477 is controlled. Of course, in the case of the PAL system, this switch circuit (SW)
477 is reset.

In the clip circuit 48, the digital LPF 44
In order to remove the color difference signal leaked during the blanking period, the burst flag pulse and the blanking pulse are clipped except for the burst signal period.

The digital chroma signal generated as described above is formed into an analog chroma signal via the D / A converter 15.

In the present invention, a digital chroma signal is formed as described above.
It can support up to eight digital video cameras.

[0036]

As described above in detail, the digital chroma signal encoder circuit according to the present invention uses f _CK / f _CK / D for digital balanced modulation necessary for forming a chroma signal.
Since the conversion circuit for converting the 2 digital color difference signals into the 4f _SC digital color difference signal is formed by combining the digital LPF and the clip circuit, the configuration is simplified.
The simplification and the time-division color difference signal are converted to digital L
Since the band is controlled by the PF, the circuit scale can be reduced.

Furthermore, since digital balanced modulation corresponding to the subcarrier and the horizontal synchronization signal is realized, a high-precision and high-quality chroma signal can be generated, and a great effect can be expected when used in signal processing of a color video camera or the like. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital chroma signal encoder circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram in each main part of FIG.

FIG. 3 is a diagram illustrating a configuration example of a digital LPF of FIG. 1;

FIG. 4 is a configuration diagram of a conventional analog encoder circuit.

FIG. 5 is a configuration diagram of a conventional digital encoder circuit.

FIG. 6 is a diagram showing signal waveforms at various parts in FIG. 5;

[Explanation of symbols]

11: imaging unit, 12: CDS / AGC / gamma processing circuit,
13 ... A / D converter, 14 ... Digital signal processor (DSP), 15 ... D / A converter, 41 ... Color difference signal time division circuit, 42 ... Character mix circuit, 43 ... Blanking mix circuit, 44 ... Digital LPF , 45…
Frequency converter, 46… Digital balanced modulator, 47… Balanced modulation control signal generator, 48… Clip circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 9/44-9/78

Claims (1)

(57) [Claims] In a video camera or the like using a CCD image pickup device, a CCD obtained by subjecting a captured image signal to A / D conversion using a CCD drive frequency and performing digital signal processing.
Color difference signals RY, BY of a half frequency of the driving frequency
Frequency conversion means for sampling at four times the subcarrier frequency for digitally balanced modulation, means for inserting a digital LPF before the frequency conversion means, and color difference signals R-Y, B
Means for passing a color difference signal obtained by alternately sampling -Y in a time-division manner, and a sub-adjuster for adjusting a horizontal synchronization phase of the color difference signals RY and BY converted to the quadruple subcarrier frequency with respect to the subcarrier signal. An encoder circuit for a digital chroma signal, comprising: carrier balance modulation means; and means for removing a color difference signal leaked during a blanking period by a digital LPF after balance modulation.