JPH0219017A - Ecl latch circuit - Google Patents

Abstract

PURPOSE:To simplify the clock device and to make the circuit operation stable by constituting the title circuit by parallel connection of a transistor(TR) applying a reference voltage to the opposite side to a feedback signal extraction side and a TR receiving a feedback signal. CONSTITUTION:A collector of a TR 14 constituting one of a couple of current switching paths forming an ECL circuit of a latch section 2 is coupled (collector dot) with a collector TR 13, and a level of an input, inverse of CLK is fed to a TR 11. A base of a TR 17 extracting a state output Q and a feedback signal is connected to a collector of the TR 14. The other current switching path of the ECL circuit of the latch section is constituted by the parallel connection between the TR 15 receiving a reference voltage VBB and the TR 16 receiving a feedback signal. Thus, the clock device is simplified and the circuit operation is made stable.

Description

[Detailed Description of the Invention] (Summary) This invention relates to an ECL (current switching type) latch circuit used in high-speed logic circuits of computers, etc.

The purpose is to simplify the clock mechanism in the ECL latch circuit and stabilize the operation of one circuit.

Each has a data input section and a latch section configured with a level shift type ECL circuit, and the EC of the data input section
The L circuit includes an input transistor connected in parallel to input data and a black signal, and an output transistor to which a reference voltage is applied. A level-shifted data signal is output from the collector of the transistor, and the ECL circuit of the latch section connects the collector of the transistor on the feedback signal extraction side to the collector of the reference voltage application side transistor of the data input section, and connects the collector of the transistor on the feedback signal extraction side to the collector of the transistor on the reference voltage application side of the data input section. The same clock that is input to the data input section is input to the base of the circuit, and a transistor for applying a reference voltage and a transistor for inputting a feedback signal are connected in parallel on the opposite side to the feedback signal extraction side.

[Industrial application field]

The present invention is based on ECL used in high-speed logic circuits of computers, etc.
(Relating to IIT flow switching type circuit.

In particular, the present invention provides a simple ECL run circuit that requires only a single clock.

[Conventional technology]

FIG. 5 shows a circuit diagram of a conventional ECL latch circuit.

In FIG. 5, 1 is a data input section, 2 is a launch section,
TRI to TR9 are transistors, D+ is a diode, R1 to R5 are resistors, CLK is a positive clock, CLK
is the negative clock, D is the launch input data, Q is the launch status output, VBB is the reference voltage, and VER is the power supply voltage for the current switch.

VTT represents the power supply voltage for eminter follower termination, and ■C8 represents the constant current control voltage.

Next, the operation of the circuit shown in FIG. 5 will be explained using the signal waveform diagram shown in FIG.

This circuit operates when the negative clock CLK is “0” (CLK
="1"), the latch input data D is sampled, and when CLK is 1"(CLK="0"), the sampled value is held.

That is, when the negative clock CLK input to the TRI of the data input section 1 is "O" and the latch input data D is 101, the TR3 is turned on. Since the low level collector voltage of TR3 at this time is applied as the base voltage of TR9 of the launch section 2, the Q output of TR9 becomes low level and TR6 is turned off. At this time, the positive clock CL
Since K is "1", TR5 is on and TR7 is off. Subsequently, when the positive clock CLK changes to "0"(CLK-"l"), both TR5 and TR6 are turned off, so TR7 is turned on and its state is maintained.

On the other hand, if the latch input data D is "1" when the negative clock CLK input to TRI is "0", TR2 is on and TR3 is off, the Q output of TR9 is high level and TR6 is on. .

Also, at this time, since the positive clock CLK is ``I'', TR5 is on. As a result, TR7 is turned off. Then, even if CLK changes to “0” (CLK-“1”
”), since TR6 was on, the off state of TR7 is maintained.

FIG. 7 is a circuit diagram of a bipolar clock driver for generating a negative clock CLK and a positive clock CLK used in the ECL latch circuit of FIG. 5 [Problem to be solved by the invention] Conventional ECL latch In the circuit, it is necessary to apply a negative clock and a positive clock to the data input section and the latch section separately, and therefore a driver that generates clocks of both positive and negative polarities as shown in FIG. 7 is required.

In addition, there is a difference in delay time due to the wiring length of the negative clock and the positive clock, the difference in the capacitance attached to the wiring, etc., and the ECL
There was a possibility that the operation of the launch circuit would become unstable.

The present invention aims to simplify the clock mechanism in the ECL circuit and stabilize the operation of the nine circuits.

[Means to solve the problem]

The present invention provides an EC of a latch section in a conventional latch circuit.
Swap the positions of the L clock input transistor and feedback signal input transistor.

The phase of the clock required in the latch section is inverted so that a clock having the same phase as that of the data input section can be used.

FIG. 1 is a principle diagram of the ECL launch circuit of the present invention.

In FIG. 1, l is a data input section, 2 is a latch section, and T
RII or TR17 are transistors.

D+ is a level clamp diode, R11 or R
13 is a resistor, CLK is a negative clock, D is data, Q is a status output, VBB is a reference voltage, VEE and VTT are power supply voltages, GND is ground, and i is a constant current.

Both the data input section 1 and the latch section 2 have a circuit configuration based on a level shift type ECL circuit.

One of the pair of current switching paths forming the ECL circuit of the data input section 1 is composed of transistors TRII and TR12 connected in parallel, each receiving CLK and D as inputs. When the level reaches , that transistor is turned on, and the transistor TR13 forming the other current switching path is turned off. The collector of the TR 13 serves as a signal extraction point to the launch section 2.

The collector of the transistor TR14, which constitutes one of the pair of current switching paths forming the ECL of the latch section 2, is coupled (collector dot) to the collector of TR13, and the CLK of the input of TRII is similarly input. Ru. The collector of TR14 is also connected to the base of a transistor TR17 for taking out the status output Q and feedback signal.

The other current switching path of the ECL circuit in the latch section is
It is constituted by a parallel connection of a transistor TR15 which inputs the reference voltage VBB and a transistor TR16 which inputs a feedback signal.

TR17 constitutes an emitter follower circuit, and the state output Q is taken out from its emitter and given as a feedback signal to the base of TR16.

As shown in Figure 2, the signal level of Q is the shifted signal level of CLK and D, and the high level VOH of Q is higher than the high level VOH of CLK and D, and the low level VOL is the same. be.

Therefore, when VOH of Q is applied to TR16, T
It becomes superior to the level of CI and K applied to R14, and can turn TR16 on and TR14 off.

[Effect]

The operation of the ECL latch circuit shown in FIG. 1 will be explained using the signal waveform diagram shown in FIG.

When CLK is "0", data D is sampled at the data input section 1, and when CLK is "11", the level of the sampled data D is held in the latch section 2.

In other words, if D=102 when CLK="0", TR
Both TR11 and TR12 are turned off, and TR13 is turned on. At this time, since TR14 is also off, Q becomes VOL, TR16 is off, and TR15 is on.

Next, when CLK="1", TR11 turns on and TR
13 is off and TR14 is on. For this reason, Q's VO
L, that is, “0” is held in the latch section 2.

On the other hand, if D=11'' when CLK="0", TR
II is off, but TR12 is on and TR1
3 is off. At this time, since TR14 is off, 3
Q becomes VOH and turns on TR16. followed by C
LK-11'', TRII is on, TR13 is off, and CLK VOH is applied to TR14, but under the control of Q VOH, TR16 is on and TR14 is
is in the off state, that is, 1″ is latched by the latch portion 2.

〔Example) FIG. 4 shows an LSI circuit according to one embodiment of the present invention.

In FIG. 4, 1 to 13 are ECL launch circuits to which the present invention is applied, 14 is a three-man powered OR circuit, and 15 is a three-man powered OR/NOR circuit.

The ECL launch circuits 11 to 13 (12 and 13 are the same as 11, so detailed circuit configurations are omitted) are the ECL launch circuits shown in FIG.
The functions of ET, SET, and Q have been added.

What are the levels of the RBSET, SET, and Q signals?

Same as the signal level of Q shown in FIG.

The level of the VOH is set higher than the VOH level of CLK and D.

RESET is a signal that sets the signal to "1" when CLK="1" and 5ET=10, and sets Q-"0".

SET is a signal that is set to "1" at CLK-"1" and RESET-"O" and sets Q="1".

Q is the inverse output of Q.

In the three-man OR circuit 14, CLKI is a clock pulse input that is the source of CLK. Also ENI, EN
2 is an enable signal for clock input control, and when both 5 and 9 are 0'', the 9 circuit 14 supplies CLK to each ECL latch circuit 11 to 13.

Dl, D2, D3 in the three-man OR/NOR circuit 15
is the data after D, and 1 circuit 15 is.

Take the OR logic of D=DI+02+03 and set each ECL latch circuit 11 to 1.
Supply to 3.

Two-man OR circuit 14 and three-man OR/NOR circuit 15
is of non-level shift type. RO in each of these circuits is a level shift resistor, and the shift amount ΔV=R
o produces zero i. The resistor RO, together with the collector resistor RC3, is prepared as an element resistor in the case of a mask slice LSI.

On the other hand, the ECL latch circuits 11 to 13 are of a level shift type, and Ro is inserted in only one current switching path along with RO3. Therefore, when configuring an ECL latch circuit, a common resistor can be used for both the level shift type and the non-level shift type, and there is no need to separately prepare a resistor with a special value.

By the way, in the ECL rough circuit 11, CLK="1"
When RESET-@1 is set, the transistor TA,
TB turns on at the same time, and the collector connection point Node C
At this point, a decrease in the level of (Ro+RC3)X2 i is about to occur. In this case, the collectors of TA and TB connected to the Nodec drop below their respective base potentials, causing a saturation phenomenon in which the base-collector direction becomes forward, so the clamp diode Di prevents an excessive level drop. . An extra emitter follower transistor can be used for this Di.

In the signal waveform diagram of FIG. 3, at the data hold point, CLK changes from "0" to "1'" when D-"0" is held.

In FIG. 4, TC changes from off to on, TD changes from on to off, and TA changes from off to on.

This movement of TD and TA is opposite to that of NodeC, but because the potential of NodeC cannot respond instantaneously due to the parasitic capacitance of the transistors and wiring connected to NodeC, D = “0”. can be held. If necessary, add a capacitor to the ModeC or TB emitter wiring (for example, Cadd as shown)
You can also make timing adjustments.

〔Effect of the invention〕

Since the ECL latch circuit according to the present invention requires only a single clock, it has the advantage of simplifying the clock driver and simplifying the wiring.

Moreover, it can operate more stably than conventional circuits.

Performance is also improved.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a signal level diagram in the circuit of the present invention, Figure 3 is a signal waveform diagram of the circuit of the present invention, and Figure 4 is a diagram of the signal waveform of the circuit of the present invention.
The figure is a circuit diagram of one embodiment of the present invention. FIG. 5 is a circuit diagram of a conventional ECL launch circuit, FIG. 6 is a signal waveform diagram of the conventional circuit, and FIG. 7 is a circuit diagram of a bipolar flock driver. In Figure 1. 1: Data input section 2: Raso 1000 parts TRII to TRl7:) Ransistor Di Two-level clamping diode R11 to R13: Resistor i: Constant current CLK: Negative clock D = Data Q: Status output VBB: Reference voltage patent

Claims (1)

[Claims] A data input section (1) and a latch section (2) are provided, each of which is configured with a level shift type ECL circuit, and the ECL circuit of the data input section (1) has a data (D) and It is equipped with parallel-connected input-side transistors that each receive a clock (@CLK@) as an input, and an output-side transistor to which a reference voltage is applied, and samples data (D) using the clock (@CLK@). , a level-shifted data signal is output from the collector of the output side transistor to which the reference voltage is applied, and the ECL circuit of the latch section (2) connects the collector of the transistor on the feedback signal extraction side to the above output of the data input section (1). The collector is coupled to the collector of the feedback signal extraction side transistor, and the same clock (@CLK@) input to the data input section (1) is input to the base of the feedback signal extraction side transistor, and the opposite side of the feedback signal extraction side is An ECL characterized in that a transistor for applying a reference voltage and a transistor for inputting a feedback signal are connected in parallel.
latch circuit.