JPH02189639A - Duplication switching device for control system - Google Patents

Duplication switching device for control system

Info

Publication number
JPH02189639A
JPH02189639A JP1009106A JP910689A JPH02189639A JP H02189639 A JPH02189639 A JP H02189639A JP 1009106 A JP1009106 A JP 1009106A JP 910689 A JP910689 A JP 910689A JP H02189639 A JPH02189639 A JP H02189639A
Authority
JP
Japan
Prior art keywords
section
output
input
switching
abnormality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1009106A
Other languages
Japanese (ja)
Other versions
JPH07117906B2 (en
Inventor
Koichi Sakagami
浩一 坂上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP1009106A priority Critical patent/JPH07117906B2/en
Publication of JPH02189639A publication Critical patent/JPH02189639A/en
Publication of JPH07117906B2 publication Critical patent/JPH07117906B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To prevent a data flow from being lacked or delayed by allowing a switching part included in an operation part to switch a driving system input part to a waiting system input device at the time of occurrence of abnormality in the driving system input part, and at the time of occurrence of abnormality in a driving system output part, allowing a switching part included in an output part to switch the driving system output part to a waiting system output part. CONSTITUTION:When abnormality is caused in the driving system input part 5, the abnormality is detected by an input data abnormality detecting means included in the operation part 1 and the driving system input part 5 causing the abnormality is switched to the waiting system input part 6 by the switching part 11 included in the operation part 1. When abnormality is caused in the driving system output part 2, the abnormality is detected by using an output data abnormality detecting means included in the output part 2 and the driving system output part 2 causing the abnormality is switched to the waiting system output part 3 by the switching parts 21, 31 included in the output parts 2, 3. Thus, a time delay due to switching is scarecely caused.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

本発明は、複数の検出信号を出力しつつ、複数の操作信
号を入力して制御される制御対象機器、稼動系、待機系
の2つの入力部であって、少な(ともそれぞれ同一の前
記検出信号を入力して同一のシリアルのデジタル入力信
号に変換する処理を前記検出信号の別に順次実行する入
力部、前記デジタル入力信号に所定の演算処理を施して
前記制御対象機器を制御するためのシリアルのデジタル
出力信号を出力する演算部、 稼動系、待機系の2つの出力部であって、少なくともそ
れぞれ同一の前記デジタル出力信号を入力して同一の前
記操作信号に変換する処理を前記操作信号の別に順次実
行する出力部、を備えた待機冗長形二重化制御システム
における前記入力部または出力部を稼動系から待機系へ
切換える二重化切換装置に関するもので、 特に前記切換えの際の処理の切換ねり時間を極力少なく
し得るようにした二重化切換装置に関する。 なお以下各図において同一の符号は同一、もしくは相当
部分を示す。
The present invention provides two input sections for control target equipment, an operating system, and a standby system that are controlled by inputting a plurality of operation signals while outputting a plurality of detection signals. an input unit that sequentially executes a process of inputting a signal and converting it into the same serial digital input signal for each of the detection signals; a serial unit that performs predetermined arithmetic processing on the digital input signal to control the controlled device; a calculation unit that outputs a digital output signal; two output units, an active system and a standby system, each inputting at least the same digital output signal and converting it into the same operation signal; This invention relates to a redundancy switching device for switching the input part or output part from the active system to the standby system in a standby redundant type redundant control system equipped with an output part that is executed sequentially, and in particular, the processing switching time during the switching. The present invention relates to a duplex switching device that can be made as small as possible.In the following figures, the same reference numerals indicate the same or equivalent parts.

【従来の技術】[Conventional technology]

第2図および第3図はおのおの従来のこの種の二重化切
換方式を説明するためのブロック回路図である。 第2図において、■は制御対象機器10からのアナログ
の入力データ7Aに基いて所定の演算を行い、この制御
対象機器10を制御するためのデジタルの出力データ8
Bを得る演算部で図外のCPUを備えている。入力デー
タ7Aは制御対象機器の運転状況を示すアナログデータ
で、制御対象機器10の複数の検出部7(71〜7n)
よりそれぞれ出力される。 5および6は図外のCPUを備えた同一の構成の入力部
で、それぞれ複数の検出部7からのアナログの入力デー
タ7Aを、互いに同期して切換動作を行うマルチプレク
サ(MPXとも略記する)5’C,6Gを介し順次切換
え入力したうえ、A/D変換器5b、6bを介しA/D
変換し、さらにこのA/D変換されたパラレルのデジタ
ルデータをパラレル/シリアル変換器5a、6aを介し
シリアルのデジタルデータ9八に変えて演算部1へ伝達
する。そして、この5と6とで稼動系と待機系の2系統
を構成している。この例では、5と6のうら一方の5を
稼動系入力部、他方の6を待機系入力部として使用する
ものとする。 2および3は図外のCPUを備えた同一の構成の出力部
で、それぞれ演算部1のシリアルがっデジタルの出力デ
ータ8Bを、シリアル/パラレル変換器2a、3aを介
し順次パラレルのデジタルデータに変換したうえ、この
変換データをD/A変換器2b、3bを介しD/A変換
し、さらにこの変換されたアナログデータを互いに同期
して切換動作を行うマルチプレクサ(MAX)を介し制
御対象機器10の複数の動作部4(41〜4n)へ順次
切換えて伝達する。そして、前記の入力部と同様に2と
3とで稼動系と待機系の2系統を構成しており、この例
では一方の2を稼動系出力部として、他方の3を待機系
出力部として使用するものとする。 12は演算部1に備えられた稼動系と待機系の切換部で
入力部及び出力部の切り換えが可能である。 稼動系の入力部5あるいは出力部2に異常が発生した場
合、演算部1に備えられた図外の入力データあるいは出
力データの異常検出手段を介して異常を検出し、演算部
1に備えられた切換部12によって、異常が発生した稼
動系の入力部5あるいは出力部2から、待機系の入力部
6あるいは出力部3へ切り換える。 次の第3図において、第2図と異なる点は、稼動系と待
機系とを切り換える切換部が、それぞれ入力部および出
力部における制御対象機器10に近い側に備えられてい
る点のみであり、稼動系入力部5には切換部51が待機
系入力部6には切換部61が、稼動系出力部2には切換
部21が、待機系出力部3には切換部31がそれぞれ備
えられている。 稼動系の入力部5あるいは出力部2に異常が発生した場
合、これらの入力部あるいは出力部に備えられた図外の
入力データあるいは出力データの異常検出手段を用いて
異常を検出し、異常の発生した稼動系の入力部5あるい
は出力部2を、これらの入力部5,6およびおよび出力
部2.3に備えられた切換部51.61および21.3
1によって、待機系の入力部6あるいは出力部3に切り
換える。
FIGS. 2 and 3 are block circuit diagrams for explaining this type of conventional duplex switching system. In FIG. 2, (■) performs a predetermined calculation based on analog input data 7A from the controlled device 10, and digital output data 8 is used to control the controlled device 10.
The arithmetic unit that obtains B is equipped with a CPU (not shown). The input data 7A is analog data indicating the operating status of the controlled device, and is input to the plurality of detection units 7 (71 to 7n) of the controlled device 10.
are output respectively. Reference numerals 5 and 6 designate input units having the same configuration and including a CPU (not shown), each of which is a multiplexer (also abbreviated as MPX) 5 that switches analog input data 7A from a plurality of detection units 7 in synchronization with each other. 'C, 6G, and then A/D converter 5b, 6b.
Further, the A/D converted parallel digital data is converted into serial digital data 98 via parallel/serial converters 5a and 6a, and is transmitted to the arithmetic unit 1. These 5 and 6 constitute two systems: an active system and a standby system. In this example, it is assumed that one of 5 and 6 is used as an active system input section, and the other 6 is used as a standby system input section. 2 and 3 are output units having the same configuration and equipped with a CPU (not shown), each of which sequentially converts the serial to digital output data 8B of the calculation unit 1 into parallel digital data via serial/parallel converters 2a and 3a. After the conversion, this converted data is D/A converted via the D/A converters 2b and 3b, and the converted analog data is sent to the controlled device 10 via a multiplexer (MAX) that performs switching operations in synchronization with each other. The information is sequentially switched and transmitted to the plurality of operating units 4 (41 to 4n). Similarly to the input section described above, 2 and 3 constitute two systems, an active system and a standby system, and in this example, one 2 is used as the active system output section, and the other 3 is used as the standby system output section. shall be used. Reference numeral 12 denotes a switching unit between an active system and a standby system, which is provided in the calculation unit 1 and is capable of switching between an input unit and an output unit. When an abnormality occurs in the input section 5 or the output section 2 of the operating system, the abnormality is detected through an abnormality detection means for input data or output data (not shown) provided in the calculation section 1, and The switching unit 12 switches from the input unit 5 or output unit 2 of the active system where the abnormality has occurred to the input unit 6 or output unit 3 of the standby system. The only difference between the following Fig. 3 and Fig. 2 is that the switching section for switching between the active system and the standby system is provided on the input section and output section, respectively, on the side closer to the controlled device 10. , the active system input section 5 is provided with a switching section 51, the standby system input section 6 is provided with a switching section 61, the active system output section 2 is provided with a switching section 21, and the standby system output section 3 is provided with a switching section 31. ing. If an abnormality occurs in the input section 5 or output section 2 of the operating system, the abnormality is detected using an input data or output data abnormality detection means (not shown) provided in these input sections or output sections, and the abnormality is detected. The input section 5 or output section 2 of the generated operating system is switched to the switching sections 51.61 and 21.3 provided in these input sections 5, 6 and output section 2.3.
1 to switch to the standby input section 6 or output section 3.

【発明が解決しようとする課題】 しかしながら前述の方式では次の問題がある。 まず第2図の方式では稼動系出力部2に異常があり、前
述の如く演算部l内の切換部12で待機系出力部3に切
り換える場合、演算部1から待機系出力部3の出力部ま
での間にシリアル/パラレル変換器3aやD/A変換器
3b等の処理に基づく時間遅れがあるため、異常が発生
し切換部12の切換えが完了してから操作部4まで出力
データ8Bが流れるには、ある期間を必要としその期間
、出力データが欠如してしまう。 一方、第3図の方式では稼動系入力部5に異常があり、
待機系入力部6に切換える場合、この方式では入力部5
,6内の切換部5L61で切換えるが、待機系入力部6
の入力端と演算部1との間にA/D変換器6bやパラレ
ル/シリアル変換器6a等の処理に基づく時間遅れがあ
るため、異常が発生し切換えが完了してから演算部1ま
で入力データ7八が流れるには、ある期間を必要としそ
の期間、入力データが欠如してしまう。 そこで、本発明の課題は稼動系から待機系に切換える際
、入力部と演算部との間、あるいは演算部と出力部との
間の各種の変換処理に基づく時間遅れに起因するデータ
の欠如を解消した制御システムの二重化切換装置を提供
することにある。
[Problems to be Solved by the Invention] However, the above-mentioned method has the following problems. First, in the method shown in FIG. 2, there is an abnormality in the active output section 2, and when switching to the standby output section 3 by the switching section 12 in the calculation section 1 as described above, the output section of the standby system output section 3 from the calculation section 1 Since there is a time delay based on the processing of the serial/parallel converter 3a, D/A converter 3b, etc., an abnormality occurs and the output data 8B is not sent to the operation unit 4 after the switching of the switching unit 12 is completed. It takes a certain period of time for the data to flow, and during that period, output data is missing. On the other hand, in the method shown in FIG. 3, there is an abnormality in the operating system input section 5.
When switching to the standby system input section 6, in this method, the input section 5
, 6, but the standby system input section 6
Because there is a time delay between the input terminal of the A/D converter 6b, parallel/serial converter 6a, etc. due to the processing of the A/D converter 6b, parallel/serial converter 6a, etc., the input to the calculation unit 1 will occur after an abnormality occurs and the switching is completed. A certain period is required for the data 78 to flow, and input data is missing during that period. Therefore, the problem of the present invention is to prevent data loss caused by time delays caused by various conversion processes between the input section and the calculation section or between the calculation section and the output section when switching from the active system to the standby system. An object of the present invention is to provide a redundant switching device for a control system that eliminates the problem.

【課題を解決するための手段】[Means to solve the problem]

前述の課題を解決するために、本発明の二重切換装置に
おいては、r(検出部7などから出力される)複数の検
出信号(入力データ7八など)を出力しつつ、複数の操
作信号(4Aなど)を入力して制御される制御対象機器
(10など)、稼動系、待機系の2つの入力部であって
、少なくともそれぞれ同一の前記検出信号を入力して同
一のシリアルのデジタル入力信号(9Aなど)に変換す
る処理を前記検出信号の別に順次実行する入力部(5,
6など)、 前記デジタル入力信号に所定の演算処理を施して前記制
御対象機器を制御するためのシリアルのデアタル出力信
号(出力データ8Bなど)を出力する演算部(1など)
、 稼動系、待機系の2つの出力部であって、少なくともそ
れぞれ同一の前記デジタル出力信号を入力して同一の前
記操作信号に変換する処理を前記操作信号の別に順次実
行する出力部(2,3など)、を備えた制御システムで
あって、 前記演算部と入力部との間に設けられ、前記演算部へ前
記デジタル入力信号を常時は前記稼動系入力部から入力
し、該入力部が異常のときは前記待機系入力部から切換
え入力する第1の切換手段(切換部11など)と、 前記出力部の出力側に設けられ、前記制御対象機器へ前
記操作信号を常時は前記稼動系出力部から出力し、該出
力部が異常のときは前記待機系出力部から切換え出力す
る第2の切換手段(切換部21.31など)と、を備え
たjものとする。
In order to solve the above-mentioned problems, the double switching device of the present invention outputs a plurality of detection signals (input data 78, etc.) (outputted from the detection section 7, etc.) and also outputs a plurality of operation signals. (4A, etc.) to control target equipment (10, etc.), an active system, and a standby system, each of which receives at least the same detection signal and receives the same serial digital input. An input unit (5,
6, etc.), a calculation unit (1, etc.) that performs predetermined calculation processing on the digital input signal and outputs a serial digital output signal (output data 8B, etc.) for controlling the device to be controlled;
, an output unit (2, 3, etc.), the control system is provided between the calculation section and the input section, the digital input signal is always input to the calculation section from the operation system input section, and the input section a first switching means (switching section 11, etc.) that switches input from the standby system input section when an abnormality occurs; A second switching means (switching section 21, 31, etc.) that outputs an output from the output section and switches the output from the standby output section when the output section is abnormal.

【作 用】[For use]

稼動系入力部および待機系入力部の演算部への入力端に
は、それぞれ同じ信号が出力されており、また稼動出力
部の切換部への出力端および待機系出力部の切換部の出
力端にも、それぞれ同じ信号が出力されているので、入
力部あるいは出力部の異常でこれらを稼動系から待機系
へ切換えても、この切換えによる処理の時間遅れは殆ど
ない。
The same signal is output to the input terminals of the operating system input section and the standby system input section to the calculation section, respectively, and the output terminal of the operating system output section to the switching section and the output terminal of the switching section of the standby system output section Since the same signal is output to both, even if these are switched from the active system to the standby system due to an abnormality in the input section or output section, there is almost no time delay in processing due to this switching.

【実施例】【Example】

第1図は本発明の一実施例を示すブロック回路図で第2
図、第3図に対応するものである。第1図において、1
は制御対象機器10からの入力データ7Aに基いて所定
の演算を行いこの制御対象機器10を制御するための出
力データ88を得る演算部であり、この演算部1には第
2図における切換部12に代り、稼動系入力部5と待機
系入力部6の切換のみを行う切換部11が設けられ、出
力部2゜3の切換は第3図と同様に行わないようにした
以外は第2図と同様に構成されている。 入力データ7Aは制御対象機器10の運転状況を示すア
ナログデータで、制御対象機器10の複数の検出部7(
71〜7n)よりそれぞれ出力される。稼動系入力部5
および待機系入力部6の構成や動作、およびこの入力5
,6と検出部7との接続は第2図の場合と全く同じであ
る。またこの入力5,6と検出部11との接続も、第2
図における入力部5゜6と切換部12との接続と全く同
様である。 また稼動系出力部2.待機系出力部3の構成や動作、お
よびこの出力部2.3と、演算部1および操作部4との
接続は第3図と全く同じである。 なお各切換部21.31は少なくともこの出力部2゜3
内でシリアルかつデジタルの出力データ8Bが操作信号
4八に変換された後にそれぞれ置かれるものとする。従
ってこの例では切換部21.31はそれぞれD/A変換
器2b、3bとマルチプレクサ2G、3Gとの間に設け
られている。 このように構成す葛ことにより、稼動系入力部5に異常
が発生した場合、演算部lに設けられた図外の入力デー
タの異常検出手段を用いて異常を検出し、異常が発生し
た稼動系入力部5を演算部1に設けられた切換部11に
よって待機系入力部6には切り換えるが、待機系入力部
6には入力データ7Aが到達している(即ち入力部6は
入力部5と同じシリアルのデジタルデータ9Aを切換部
11の入口に出力している)ため、切り換えによる時間
遅れはほとんどない。何となれば通常待機冗長形二重化
コンピータシステムにあっては、待機系は運転が停止し
ているのではな(、正規に運転されており、ただデータ
のみは稼動系を使用し待機系のデータは予備となってい
るため、入力データ7八は待機系入力部6の出力端に到
達しているからである。 また稼動系出力部2に異常が発生した場合、出力部2に
設けられた図外の出力データの異常検出手段を用いて異
常を検出し、異常が発生した稼動系出力部2を出力2.
3に備えられた切換部21゜31によって待機系出力部
3に切り換えるが、待機系出力部3の切換部31まで出
力データ8Bは到達している(即ち出力部3は切換部3
1の演算部1例の出力端に、出力部2が切換部21の演
算部1側の出力端に出力している信号と同じ出力信号を
出力している)ため、切り換えによる時間遅れはほとん
どない。 なお以上の実施例においては制御対象機器10がアナロ
グデータを授受するものとしたが、制御対象機器10が
直接パラレルのデジタルデータを授受する場合であって
も(従ってA/D変換器5b。 6bやD/A変換器2b、3bが省略される場合であっ
ても)、本発明が適用し得ることは明らかである。
FIG. 1 is a block circuit diagram showing one embodiment of the present invention.
This corresponds to FIG. In Figure 1, 1
is a calculation unit that performs a predetermined calculation based on the input data 7A from the controlled device 10 and obtains output data 88 for controlling the controlled device 10, and this calculation unit 1 includes the switching unit shown in FIG. 12 is replaced by a switching section 11 that only switches between the active system input section 5 and the standby system input section 6, and the switching section 11 is provided in place of the switching section 12, which only switches between the active system input section 5 and the standby system input section 6. The structure is similar to the one shown in the figure. The input data 7A is analog data that indicates the operating status of the controlled device 10, and the input data 7A is analog data indicating the operating status of the controlled device 10.
71 to 7n), respectively. Operating system input section 5
and the configuration and operation of the standby system input section 6, and this input 5.
, 6 and the detection unit 7 are exactly the same as in the case of FIG. In addition, the connection between these inputs 5 and 6 and the detection unit 11 is also connected to the second
The connection between the input section 5.6 and the switching section 12 in the figure is exactly the same. In addition, the operating system output section 2. The configuration and operation of the standby output section 3 and the connections between this output section 2.3 and the calculation section 1 and the operation section 4 are exactly the same as in FIG. Note that each switching section 21.31 is connected to at least this output section 2゜3.
It is assumed that the serial and digital output data 8B is converted into an operation signal 48 and placed therein. Therefore, in this example, the switching units 21.31 are provided between the D/A converters 2b, 3b and the multiplexers 2G, 3G, respectively. With this configuration, when an abnormality occurs in the operation system input section 5, the abnormality is detected using the input data abnormality detection means (not shown) provided in the calculation section l, and the operation system in which the abnormality has occurred is detected. The system input section 5 is switched to the standby system input section 6 by the switching section 11 provided in the calculation section 1, but the input data 7A has reached the standby system input section 6 (that is, the input section 6 is switched to the standby system input section 6). (The same serial digital data 9A is output to the entrance of the switching unit 11), so there is almost no time delay due to switching. In normal standby redundant redundant computer systems, the standby system is not operating (it is operating normally, but only the data is stored in the active system, and the data in the standby system is This is because the input data 78 has reached the output end of the standby system input section 6 because it is reserved.Furthermore, if an abnormality occurs in the active system output section 2, the input data 78 has reached the output terminal of the standby system input section 6. An abnormality is detected using an abnormality detection means of output data outside, and the operating system output unit 2 in which the abnormality has occurred is output 2.
However, the output data 8B has reached the switching unit 31 of the standby output unit 3 (that is, the output unit 3 has reached the switching unit 31 of the standby output unit 3).
(The output part 2 outputs the same output signal to the output terminal of the calculation part 1 of the switching part 21 as the output terminal of the calculation part 1 side of the switching part 21.) Therefore, there is almost no time delay due to switching. do not have. In the above embodiments, it is assumed that the controlled device 10 sends and receives analog data, but even if the controlled device 10 directly sends and receives parallel digital data (therefore, the A/D converter 5b. 6b It is clear that the present invention can be applied even if the D/A converters 2b and 3b are omitted).

【発明の効果】【Effect of the invention】

本発明によれば、稼動系入力部に異常が発生した場合は
演算部に備えられた切換部により待機系入力部に切換え
る、また稼動系出力部に異常が発生した場合は出力部に
備えられた切換部により待機系出力部に切換えることに
より、切換え時のデータの欠如を解消したのでデータの
流れが欠損したり遅れたりすることが防止される。 このことは、制御対象機器の運転に擾乱が入ることが無
くなり、特に精密運転制御が要求されるプラントの制御
など各種の精密運転制御が要求される装置に対しその効
果は大きい。
According to the present invention, when an abnormality occurs in the active system input section, the switching section provided in the calculation section switches to the standby system input section, and when an abnormality occurs in the active system output section, the switching section provided in the output section By switching to the standby output section using the switching section, the lack of data at the time of switching is eliminated, and data flow is prevented from being lost or delayed. This eliminates disturbances in the operation of the equipment to be controlled, and is particularly effective for devices that require various types of precise operational control, such as plant control that requires precise operational control.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック回路図、第2
図および第3図はそれぞれ第1図に対応する従来のブロ
ック回路図である。 i−一一一一演算部、2−・−稼動系出力部、3 −一
−−−待機系出力部、2a、3a  −・・・シリアル
/パラレル変換器、2b、3b  −・・−D/A変換
器、4 (41〜4n)操作部、5 ・−・−・稼動系
入力部、6−−−−−−待機系入力部、5a、6a  
−−・パラレル/シリアル変換器、5b、6b−・−A
/D変換器、20〜6C:マルチプレクサ、7(71〜
7n)  −・−検出部、8 −一−−−出力バッファ
、9−−−−一一人ノノバッファ、10−−一−−制御
対象機器、11.21.31・−・・−切換部、7A 
 −・入力データ、12: 七I十桑舎p
FIG. 1 is a block circuit diagram showing one embodiment of the present invention, and FIG.
3 and 3 are conventional block circuit diagrams corresponding to FIG. 1, respectively. i-1111 calculation section, 2---active system output section, 3-1--standby system output section, 2a, 3a --- serial/parallel converter, 2b, 3b ---D /A converter, 4 (41 to 4n) Operation section, 5 --- Active system input section, 6 --- Standby system input section, 5a, 6a
---Parallel/serial converter, 5b, 6b--A
/D converter, 20~6C: Multiplexer, 7 (71~
7n) ---Detection unit, 8--1---Output buffer, 9-----Each buffer, 10--1--Controlled device, 11.21.31--Switching section ,7A
-・Input data, 12: 7I Jukusha p

Claims (1)

【特許請求の範囲】 1)複数の検出信号を出力しつつ、複数の操作信号を入
力して制御される制御対象機器、 稼動系、待機系の2つの入力部であって、少なくともそ
れぞれ同一の前記検出信号を入力して同一のシリアルの
デジタル入力信号に変換する処理を前記検出信号の別に
順次実行する入力部、前記デジタル入力信号に所定の演
算処理を施して前記制御対象機器を制御するためのシリ
アルのデジタル出力信号を出力する演算部、 稼動系、待機系の2つの出力部であって、少なくともそ
れぞれ同一の前記デジタル出力信号を入力して同一の前
記操作信号に変換する処理を前記操作信号の別に順次実
行する出力部、を備えた制御システムであって、 前記演算部と入力部との間に設けられ、前記演算部へ前
記デジタル入力信号を常時は前記稼動系入力部から入力
し、該入力部が異常のときは前記待機系入力部から切換
え入力する第1の切換手段と、 前記出力部の出力側に設けられ、前記制御対象機器へ前
記操作信号を常時は前記稼動系出力部から出力し、該出
力部が異常のときは前記待機系出力部から切換え出力す
る第2の切換手段と、を備えたことを特徴とする制御シ
ステムの二重化切換装置。
[Scope of Claims] 1) A device to be controlled which is controlled by inputting a plurality of operation signals while outputting a plurality of detection signals, two input sections of an active system and a standby system, each of which has at least the same an input unit that sequentially executes a process of inputting the detection signal and converting it into the same serial digital input signal for each of the detection signals, and controlling the device to be controlled by performing predetermined arithmetic processing on the digital input signal; an arithmetic unit that outputs a serial digital output signal; and two output units, an active system and a standby system, each inputting at least the same digital output signal and converting it into the same operation signal. A control system comprising an output section that sequentially executes signals separately, the control system being provided between the arithmetic section and the input section, the digital input signal being always input to the arithmetic section from the operating system input section. , a first switching means for switching input from the standby system input section when the input section is abnormal; and a first switching means provided on the output side of the output section, which normally sends the operation signal to the control target device from the active system output. 1. A redundant switching device for a control system, comprising: second switching means for switching output from the standby output section when the output section is abnormal.
JP1009106A 1989-01-18 1989-01-18 Redundant switching device for control system Expired - Lifetime JPH07117906B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1009106A JPH07117906B2 (en) 1989-01-18 1989-01-18 Redundant switching device for control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1009106A JPH07117906B2 (en) 1989-01-18 1989-01-18 Redundant switching device for control system

Publications (2)

Publication Number Publication Date
JPH02189639A true JPH02189639A (en) 1990-07-25
JPH07117906B2 JPH07117906B2 (en) 1995-12-18

Family

ID=11711380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1009106A Expired - Lifetime JPH07117906B2 (en) 1989-01-18 1989-01-18 Redundant switching device for control system

Country Status (1)

Country Link
JP (1) JPH07117906B2 (en)

Also Published As

Publication number Publication date
JPH07117906B2 (en) 1995-12-18

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