JPH01101735A - Analog-digital conversion duplexing circuit - Google Patents

Abstract

PURPOSE:To avoid a double trouble and to improve reliability by duplexing an analog-digital converting circuit, parallely processing an analog input point respectively by 1/2 at a normal time and processing all analog input points with a normal circuit when any one of the circuits is abnormal. CONSTITUTION:The analog input point is parallely processed at a high speed respectively by 1/2 at the normal time with utilizing duplexed analog-digital converting circuits 4 and 14. Reference input signals 6 and 16 are inputted to the idle channel of analog switches 5 and 15 and data, which are after the A-D conversion is ended, of the reference input signals 6 and 16 are cyclicly supervised. When the data are out of a reference range, the said A-D converting circuits 4 and 14 are judged to be abnormal. When either the A-D converting circuits 4 or 14 is judged to be abnormal, the remaining normal circuit is used. Thus, the duplexed analog-digital converter is effectively operated and the high speed is maintained by parallel operation at the normal time. Then, when either of the circuits is abnormal, the normal circuit executes the operation instead of the abnormal circuit and the double trouble can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual analog-to-digital conversion circuit in a digital control device using a processor such as a microcomputer.

[Conventional technology]

A conventional circuit of this type is shown in FIG.

In the figure, A1 to An are external analog input signals, (11 is composed of a semiconductor switch, etc., and according to channel selection signals 81 to
(2) is a sample-and-hold amplifier (hereinafter referred to as "amplifier") with excellent holding performance;
mode is the mode control signal of the S/H amplifier (2); An analog digital converter (hereinafter referred to as an A-D converter) converts the signals D1 to Dg, and control 1 is the above-mentioned A-D converter (
3) issues a conversion start command, and control 2 sends a control signal to read the data after conversion, (
4) is an analog-digital conversion circuit.

Next, the operation will be explained. The dynamic fμ when inputting the first analog input signal Ai (i=l to n) will be explained. First, the S/H amplifier (2) is set to sample mode by the control signal mode, and the first channel of the multiplexer circuit 111 is made conductive by the channel selection signal 31-strong. As described above, the analog input signal A1 is sent out as the output of the multiplexer circuit (11), and is input to the A-D converter (31) via the s7H amplifier (2).
After the propagation delay time of the analog input signal due to the control signal modeicJ, if the amplifier (2) is put into the hold mode, the input voltage at that point is held, and the held voltage is input to the A-D converter (31). Next, proceed to A above.
-D converter (31, control signal control
When the control signal 0ontr012 issues an instruction to start the conversion, and after the conversion is completed, the control signal 0ontr012 issues an instruction to read the data after the conversion, and the digital signals qDI to De are sent to the system bus.

[Problem that the invention seeks to solve]

Generally, in digital control devices, input/output circuits are required to have high reliability and high operating speed.

Is there a way to improve reliability by duplicating the analog-to-digital conversion circuit as shown in Figure 2, so that one operates all the time and the other operates as a standby circuit?In this method, the standby circuit only operates when a failure occurs. It doesn't work, so it's not efficient.

This invention was made to solve the above-mentioned problems by effectively operating a duplicated analog-to-digital converter and allowing it to operate in parallel during normal operation. :d
Highly reliable gamma narrow-to-digital conversion system that maintains high speed and operates at a speed of about 2 times.■ When either circuit is abnormal, the normal circuit takes over the operation of the abnormal circuit, avoiding major failures. It provides a heavy circuit.

Means for Solving the L Problem] The analog-to-digital conversion circuit according to the present invention utilizes a duplicated analog-to-digital conversion circuit to process analog input points in parallel at high speed one by one during normal operation.
This shows a concrete measure to process all analog input points with a normal circuit when one of the circuits is abnormal.

[Effect]

In this invention, the analog-to-digital conversion circuit is duplicated, and by periodically monitoring each conversion circuit, an abnormality is discovered, and when an abnormality occurs, a normal circuit is used to process all analog input points. This is what I did.

This operation flowchart is shown in Figure %IJ3.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.
In the figure, AI-An is an external analog input signal, +51. (151 is the analog input signal A1
~Group of A1~A- and A-+1~A, which are divided into two halves
an analog switch to select one of n groups;
control 4 is a selection signal for the analog switch, m, (tυ is a multiplexer circuit that sequentially sends out the analog input signal in a time-division manner according to the channel selection signal S5-8m, 12), t17J is a signal 7'c with excellent holding performance. S/H amplifier, mode is the above S/H
Amplifier i2). (136D mode F:7 nt 0-)v
Signal, 131, (13c said multiplexer +11
．． (An A-D converter, co
ntrol 1 is the A-D converter +31. Issue a conversion start command to Q3 and control 2. cont,
rol 3 is a control signal for reading data after conversion, +4+, (t4) is an A-D conversion circuit, +61
, eel is the bar D conversion circuit +41. c14) is a reference input signal for detecting an abnormality, and (71 is an inverter circuit).

Next, the operation will be explained. First, the first and second
+lth analog input signal Ai, A+1 (1=
The operation when inputting 1 to -) will be explained.

An analog switch (5:) outputs a control signal control 4 so that groups A1 to A- can be selected from the two divided analog input signals.

At this time, the selection signal of the analog switch (L51) is inverted due to the ishiverter (7), and the analog input signal group A-+1-An is selected in the analog switch 1!19.In this state, the S/ 'H amplifier +2)
．． Q3 is set to the sample mode by the cositrol signal mode, and the channel selection signals 8l-8co are used to conduct the first channel of the multiplexer circuit (11, αυ and the first channel of -NA).The analog input signal A1,
A--)-1 is a multiplexer circuit (11, which sends out the output of αυ and output, S/H7>P+2). After the propagation delay time of the analog input signal by the multiplexer circuit (11, αυ and SA amplifier 12+, H), the S/H amplifier ( 2+, (12) is set to hold mode, the input voltage at that point is held, and the held voltage is input to the A-D converter (: minus, α floor).

Subsequently, the A-reverse converter 131 (13) is commanded to start conversion using the control signal control 1, and after the conversion is completed, the control signal control 2 is sent.
, 3 individually issues an instruction to read the data after conversion, the converted digital signals Dl-DI are sent to the system bus at A-I) converter +31 and (131).The above process is explained in the flowchart. The result is as shown in Fig. 4.

During normal operation, channel selection, S/H amplifier mode selection, and A-D converter conversion start commands operate simultaneously for both A-D converter circuits, and are executed in chronological order only when reading data after conversion. It operates at high speed.

Next, the operation in the event of an abnormality will be explained. Analog switch +5+, (reference input signal 161 to the vacant channel of 1ω)
11E9 is input, and periodically monitors the reference input signal +61, the data after the A-D conversion of (16) is completed, and if it falls outside the reference range, the corresponding A-D conversion circuit (41
Determine ゜round as abnormal. A-D conversion circuit +41. (14
If any of the circuits 1 is determined to be abnormal, the remaining normal circuits are used to control the control signal control.
AI-A- of the analog input signal is controlled by l4.
The analog input AI-wAn is input in the same way as in the normal case by alternately selecting the group A-1 to A-An. As an example, FIG. 5 shows an A-D conversion flowchart when the A-D conversion circuit (4) becomes abnormal.

In the above embodiment, it is determined whether or not the A-D conversion circuit is abnormal by inputting a reference input signal into an empty channel of an analog switch and monitoring the digital value after A-D conversion. If there is no channel, the regular analog input signal and the reference input signal may be switched in a time-division manner, or the status of the A-0 converter itself may be used to determine an abnormality.

〔Effect of the invention〕

As described above, according to the present invention, the analog-to-digital conversion circuit is duplicated, and the number of analog input points is reduced to 2 during normal operation.
Parallel processing is performed one by one, and if any circuit is abnormal, all analog input points are processed by the normal circuit.
Under normal conditions, even if either one becomes abnormal, the speed will be about 2, but a highly reliable system will not result in a serious failure.

[Brief explanation of the drawing]

Figure 1 is a dual analog-to-digital conversion circuit diagram according to an embodiment of the present invention, Figure 2 is a conventional circuit diagram, and Figures 3, 4, and 5 are schematic operation flowcharts of the above embodiments. , an operation flowchart during normal times, and an operation flowchart during abnormal times. In the figure, fil, [11 is a multiplexer circuit, (2) and (12) are sample and hold amplifiers,
+31, (13 is analog-digital converter, 1
4+, (14) is an analog-digital conversion circuit,! 5
+ and (15) are analog switches, 16+ and (Le are reference inputs, and (7) is an isciverter circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Analog switch, multiplexer, sample
The analog-to-digital conversion circuit consisting of a hold amplifier and an analog-to-digital converter is duplicated, and each of these analog-to-digital conversion circuits is periodically monitored and has a means for detecting abnormalities.During normal operation, the number of analog input points is reduced to one.
/2 parallel processing is performed, and if either analog-to-digital conversion circuit fails, the failed circuit is not used, and all analog input points are processed by the normal analog-to-digital conversion circuit. Analog-digital conversion duplex circuit. (2) As a means for discovering an abnormality in an analog-to-digital conversion circuit, an abnormality is discovered by inputting a reference input into an empty input channel and monitoring its digital conversion value. 2. The analog-digital duplex circuit according to item 1.