JPH02189632A - Information processor - Google Patents

Abstract

PURPOSE:To paritially rewrite a microprogram in a device which can not be separated from a system while operating an operating system (OS) by executing a microinstruction stored in the 2nd control storage (CS) simultaneously with the rewriting of a microprogram in the 1st CS by the microinstruction of the 2nd CS. CONSTITUTION:Plural rewriting microinstructions are stored in the 1st CS 101 for storing an ordinary microprogram and the 2nd CS 104 having the same capacity as the 1st CS 101. In the case of executing the microinstruction of a CS address to be rewritten, the microinstruction of the 2nd CS 104 is executed simultaneously with the rewriting of the microprogram of the 1st CS 101 by the microinstruction of the 2nd CS 104. Consequently, the microprogram of the device which can not be separated from the system can be partially rewritten while operating the CS.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device that operates under microprogram control.

[Conventional technology]

Conventionally, when applying a batch to microb[]grams of a device that cannot be separated during O8 operation in a user's system,
I used the following methods:

i. Stop the OS, apply the batch to the target microprogram, and then start the O8 again.

2. If the microinstructions to be batched are as shown in the example below, use a debugging tool supported by ServiceBase.

(b) When there is only one microinstruction; (b) When there are multiple microinstructions, but they are not connected as a series of sequences, and two or more instructions do not exist in one event.

Examples of depacking tools mentioned here include the following tools. The service processor receives the CS address specified by manual input from the console and the image of the microinstruction to be rewritten, and expands it on the main memory. When the service processor notifies the target device, the device uses its own microprogram to retrieve the expanded data from main memory and rewrite the microinstruction at the specified CS address with the specified image. . In this case, the number of microinstructions that can be processed at a time is 1
It is a command.

[Problem to be solved by the invention]

The above-mentioned conventional technology has the following drawbacks.

First, if the service processor does not support debugging tools, O8 must be temporarily stopped. Further, even if the system is operated in dual mode, performance will be degraded by separating the CPU or input/output processing device of one system.

Second, even if the service processor supports debugging tools, if there are multiple microinstructions to be batched and they are connected as a sequence, you may need to rewrite one microinstruction and then rewrite all the microinstructions to be batched. If a microinstruction that has already been rewritten is executed before the microinstruction is rewritten, the sequence of the microprogram will be disrupted.

As mentioned above, a batch can be applied to a microprogram of a device that cannot be separated during O8 operation when the batch consists of only one microinstruction, or when multiple microinstructions are used together in one event. Only when it doesn't exist.

(Means for Solving the Problems) The information processing device of the present invention has the same capacity as the first control memory in which the original microprogram is stored, and some of the microinstructions are for rewriting. a second control memory storing a plurality of secondary microinstructions having rewrite flags indicating that the microinstruction is being executed; a rewrite start flag that is set in response to an instruction from the service processor; 2
means for reading a microinstruction from a second control memory; and when both the rewrite flag and the rewrite start flag in the secondary microinstruction are valid, the microinstruction in the first control memory is read out from the secondary microinstruction; At the same time as rewriting with an instruction, means for executing the secondary microinstruction, the number of microinstructions whose rewriting flag is set according to an instruction from the service processor, and the number of microinstructions whose rewriting flag is read from the second control memory r: , i rewriting bit. and count value control means for invalidating the rewriting start flag when the number of valid microinstructions matches.

[Effect]

In the present invention, a second control memory (C8) having the same capacity as the first control memory (C8) that stores the original microprogram stores a plurality of rewriting microinstructions and executes the microinstruction at the CS address to be rewritten. When doing so, the microprogram of the first C8 is rewritten with the microinstructions of the second C8, and at the same time the microinstructions of the second C8 are executed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the information processing device of the present invention, and FIG. 2 shows the configuration of the second C81 in the target device 204.
FIG. 3 is a block diagram showing the flow of data and communication when storing rewriting microinstructions in 04. FIG.
S address.

A diagram showing the data format after expanding the rewriting microinstruction onto the main memory 203, FIG. 4 is the second C8
This is a timing chart when the microinstruction of the first C8101 is rewritten with the rewriting microinstruction in 104.

The original microprogram is stored in C3101. Address register 102 holds the address of C8101. CS register 103 holds microinstructions read from C8101. A plurality of microinstructions for rewriting are stored in the C8104. Address register 105 holds the address of C8104. The CS register 106 holds the rewriting microinstruction read from the C8104. The address control circuit 107 receives the instruction sequence control part and next address part of the microinstruction being executed from the selector 108, and generates the address of the microinstruction to be executed next.

The selector 108 receives microinstructions from the CS register 103 and the CS register 106, and outputs the AND circuit 114.
If the output is “O”, select the output of CS address register 103, and if the output is “1”, select CS address register 1
06 is selected and sent to the microinstruction execution unit and address control circuit 107. The selector 109 receives the CS address sent from the address control circuit 107 and the memory read register 113, and sets the reweighting start flag 1.
If 12 is "0", the upper bit of the memory read register 113 is selected, and if it is 1", the output of the address control circuit 107 is selected and sent to the address register 105. The counter value control circuit 110 is rewritten by the service processor 202. Every time a microinstruction setting communication is received, the counter value is incremented by 1, and the message bit 1 is sent to the CS register 106.
Every time a microinstruction for which 14 is valid is read, the above counter value is decremented by 1, and when the above counter value becomes 0'', the counter fIO signal 11 is set to the rewrite start flag 112.
Send 5. The rewrite bit 111 is a bit that indicates that the microinstruction is a rewriting microinstruction. The rewriting start flag 112 is an F/F that is set by an instruction from the service block [1 setter 202] and reset by the counter value O signal 115 when starting rewriting the C3104 microinstruction from the C3lOI microinstruction. . Memory read register 11
A register 3 holds data read from the main memory 203 and sends it to the selector 109 and C8104. The AND circuit 114 ANDs the value of the rewrite bit 111 in the CS register 106 and the rewrite start flag 112, and sends the result to the selector 108 as a select signal.
8101 as a write enable signal 116.

Next, the operation of storing a rewriting microinstruction in the C8104 will be explained in detail using FIGS. 2 and 3.

First, the address of the C8 to be rewritten and the image of the microinstruction are manually input from the console 201. The service processor 202 receives and receives the data.
Expand to main memory 203.

The data is expanded on the main memory 203 in a format as shown in FIG. Then, the service block 9202 notifies the target device 204 that the rewrite microinstruction has been prepared on the main memory 203. The target device 204 that received the above notification retrieves the data from the main memory 203, and C8104
Stores the rewritten microinstruction at the specified address in the service program [1 setter 202
Notify. The above operation is repeated for the number of microinstructions to be rewritten.

Next, the operation of rewriting the microinstructions in the C8101 with the microinstructions in the C3IO4 will be described in detail with reference to FIG. Here, a rewriting microinstruction is already stored in the C8104, and the counter value control circuit 1
10 holds the number of microinstructions taken into the C3104.

First, the rewrite start flag 112 is set in response to an instruction from the service processor 202. At this time, selector 1
09 switches the option from the output of the memory read register 113 to the output of the address control circuit 107. From now on, the address of the microinstruction being executed is set in the address register 105 in the same manner as in the address register 102.

Then, when the instruction sequence moves to the address corresponding to the rewriting microinstruction, the rewriting microinstruction is read into the CS register 106, so the rewriting bit 111 becomes valid, and the output of the AND circuit 114 becomes "0".
"→"1". Next, the selector 108 switches the selection from the CS register 103 bs to the CS register 106, and at the same time as the rewriting microinstruction is executed, the write enable signal 116 causes the C8101 microinstruction to change to the rewriting microinstruction. Then, the counter value held by the counter value control circuit 110 is incremented by -1 by the rewrite bit 111.
This is shown in the timing chart in the figure.

The above operation is repeated every time the address corresponding to the rewriting microinstruction is executed, and when the number of rewriting microinstructions stored in the C8104 is repeated, the counter la
O message @115 becomes valid and replacement start flag 11
2 is reset, and the rewriting of the microinstruction is completed.

〔Effect of the invention〕

As explained above, the present invention provides a second O8 having the same capacity as the first C8 which stores the original microb [1 gram].
A plurality of micro-instructions for rewriting are stored in the memory, and when executing the micro-instruction at the CS address to be rewritten, the micro-instruction in the first C8 is rewritten with the micro-instruction in the second C8, and at the same time, the above-mentioned micro-instruction in the second O8 is executed. By executing this, you will have the following effects:

(1) A microb of a device that cannot be separated from the system while O8 is in operation [1 gram can be partially rewritten while O8 is in operation.

(2) Microphone [] of the above device [1 gram] -
A plurality of microinstructions connected as a sequence can be rewritten during O8 operation.

(3) When there are multiple events that are processed as a series of sequences in the microprogram of the above device,
A portion of each event can be rewritten during O8 operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the information processing device of the present invention, and FIG.
FIG. 3 is a block diagram showing the flow of data and communication when a rewriting microinstruction is stored in 104. FIG. 3 shows the CS address received by the service processor 202 from the console 201. A diagram showing the data format when expanding the rewriting microinstruction to the main memory 203, FIG. 4 is the second C31
This is a timing chart when the microinstruction of the first C3101 is rewritten using the rewriting microinstruction in C3101. 101...C8, 102...Address register, 1
03...CS register, 104...C8, 105.
...Address register, 106...CS register, 1
07...Address control circuit, 108...Selector,
1゜9... Selector, 110... Counter value control circuit, 111... Rewriting bit, 112... Rewriting start flag, 113... Memory read register, 1
DESCRIPTION OF SYMBOLS 14... AND circuit, 115... Counter value O signal, 116... Write enable signal, 201... Console, 202... Service processor, 203...
...Main memory, 204...Customer-facing device.

Claims (1)

[Scope of Claims] 1. In an information processing device that operates under microprogram control, the memory has the same capacity as the first control memory in which the original microprogram is stored, and the microinstruction is included in a portion of the microinstruction for rewriting. A second control memory stores multiple secondary microinstructions with a rewrite flag indicating that the microinstruction is being executed, a rewrite start flag that is set by an instruction from the service processor, and a second control memory that corresponds to the same address as the microinstruction being executed. 2 above
means for reading the next microinstruction from the second control memory; and when the rewriting flag and the rewriting start flag in the secondary microinstruction are both valid, reading the microinstruction in the first control memory from the secondary microinstruction; A means for executing the secondary microinstruction at the same time as the rewriting by the instruction, the number of microinstructions whose rewriting flag is set by an instruction from the service processor, and the microinstruction whose rewriting bit is valid read from the second control memory. An information processing device comprising: count value control means for disabling a rewriting start flag when the number of instructions matches.