JPH02189614A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPH02189614A
JPH02189614A JP1009154A JP915489A JPH02189614A JP H02189614 A JPH02189614 A JP H02189614A JP 1009154 A JP1009154 A JP 1009154A JP 915489 A JP915489 A JP 915489A JP H02189614 A JPH02189614 A JP H02189614A
Authority
JP
Japan
Prior art keywords
chip
power supply
power
input terminal
raised
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1009154A
Other languages
Japanese (ja)
Inventor
Shigeru Yamagishi
山岸 繁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1009154A priority Critical patent/JPH02189614A/en
Publication of JPH02189614A publication Critical patent/JPH02189614A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent an IC chip from generating malfunction at the time of turning on a power supply by supplying power from a power supply input terminal for directly supplying power to the 1st IC chip to the 2nd IC chip to be driven with a delay from the 1st IC chip at the time of turning on the power supply through a delay means. CONSTITUTION:Although the power supply Vcc of an IC chip 1 is immediately raised when the voltage of the power supply input terminal 4 is raised by an external power supply, the power supply Vcc of an IC chip 2 is raised up to a regulated value after a prescribed delay time because of the existence of the delay means 3. Since the external power supply side does not require a function for controlling the power supply starting order, a normal external power supply can be used, and since the power supply input terminal with the same voltage can be used in common by plural chips, the number of terminals can be reduced. Since the power supply rise of the IC chip 2 is delayed from that of the IC chip 1 as a matter of course and the power ON reset of the IC chip has been already executed, malfunction such as the miswriting of the IC chip 2 is not generated by the random output of the IC chip 1.

Description

【発明の詳細な説明】 〔発明の概要〕 2以上のICチップを同一基板上に搭載した半導体回路
装置に関し、 電源投入時のICチップの誤動作を防止することを目的
とし、 基板上に2以上の独立したICチップを搭載し、該IC
チップ間で信号の授受を行う半導体回路装置において、
電源投入時に第1のICチップより遅れて動作させる第
2のICチップに対し、該第1のICチップに直接電源
を供給する電源入力端子から遅延手段を介して電源を供
給するように構成する。
[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor circuit device in which two or more IC chips are mounted on the same substrate, the purpose of this invention is to prevent malfunction of the IC chips when power is turned on. Equipped with an independent IC chip, the IC
In semiconductor circuit devices that exchange signals between chips,
The second IC chip is configured to be operated later than the first IC chip when the power is turned on, and power is supplied from the power input terminal that directly supplies power to the first IC chip via the delay means. .

〔産業上の利用分野〕[Industrial application field]

本発明は、2以上の独立したICチップを同一基板上に
搭載した半導体回路装置に関する。
The present invention relates to a semiconductor circuit device in which two or more independent IC chips are mounted on the same substrate.

cpu <中央処理装置’) 、RAM (ランダム・
アクセス・メモリ)、周辺回路等のIC(半導体集積回
路)を各々独立したチップに形成して、これらを同じ支
持基板上に搭載する半導体回路装置は、例えばマルチチ
ップのICカードとして実用化されようとしている。こ
の場合、電源投入時の誤動作を防止するために、各チッ
プの電源投入に順序付けを行う必要がある。
cpu <central processing unit'), RAM (random
A semiconductor circuit device in which ICs (semiconductor integrated circuits) such as access memory) and peripheral circuits are formed on independent chips and mounted on the same support substrate will be put to practical use, for example, as a multi-chip IC card. It is said that In this case, in order to prevent malfunctions when the power is turned on, it is necessary to order the power-on of each chip.

〔従来の技術〕[Conventional technology]

第3図は従来のマルチチップICカードの一例で、1.
2は独立したICチップ、20は共通の支持基板(カー
ド)である、ICチップ1は例えばCPUであり、IC
チップ2はCPUによってデータの読み書きが行われる
E2FROM (電気的に書き込み/消去可能なプログ
ラマブル続出し専用メモリ)である。各チップ1.2に
対しては電源入力端子4.5の他にアース端子6、デー
タ等の入出力端子7〜10が設けられている。
FIG. 3 shows an example of a conventional multi-chip IC card.
2 is an independent IC chip; 20 is a common support substrate (card); IC chip 1 is, for example, a CPU;
The chip 2 is an E2FROM (electrically writable/erasable programmable read-only memory) in which data is read and written by the CPU. Each chip 1.2 is provided with a power input terminal 4.5, a ground terminal 6, and input/output terminals 7-10 for data and the like.

このようなICカードでは、ICチップ2の電源投入順
序Cチップ1より早いと、ICチ・ノブ1がパワーオン
リセットされる前の不測の出力でICチップ2に誤書込
みする可能性がある。このため等の理由で従来は独立し
た電源入力端子4.5を設け、外部電源の立上りに順序
付けをしている。
In such an IC card, if the power-on order of the IC chip 2 is earlier than that of the C-chip 1, there is a possibility that an unexpected output before the IC chip 1 is power-on-reset may cause erroneous writing to the IC chip 2. For this reason and other reasons, conventionally, independent power input terminals 4 and 5 are provided to order the rise of the external power supply.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、外部電源の立上りに順序付けをするには
、外部電源装置側に制御回路を設ける必要があり、−船
釣な電源装置を通用できない難点がある。また、同じ電
圧の電源Vccを受けるのに複数の電源入力端子4.5
を必要とするので、チップ数の増加に伴ない端子数が増
加する欠点がある。
However, in order to order the start-up of the external power supply, it is necessary to provide a control circuit on the external power supply side, which has the disadvantage that it cannot be used with a power supply installed on a boat. In addition, multiple power supply input terminals 4.5 are required to receive the power supply Vcc of the same voltage.
Therefore, there is a drawback that the number of terminals increases as the number of chips increases.

本発明は内部的に電源立上りの順序付けを行うことによ
り、外部での制御を不要にし、且つ電源入力端子が少な
くて済むようにするものである。
The present invention internally orders the rise of the power supply, thereby eliminating the need for external control and reducing the number of power supply input terminals.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理図で、第3図との相違点はICチ
ップ2の電源入力端子5を省き、代りにrcチ7ブ1の
電源入力端子4から遅延手段3を介してICチップ2へ
電源V、ccを供給するようにした点である。尚、IC
チップ1,2と遅延手段3は、同種のICチップや遅延
手段がある場合、それらを代表したものである。
FIG. 1 is a diagram showing the principle of the present invention. The difference from FIG. 3 is that the power input terminal 5 of the IC chip 2 is omitted, and instead, the IC The point is that power supplies V and cc are supplied to the chip 2. In addition, I.C.
Chips 1 and 2 and delay means 3 are representative of the same type of IC chips and delay means, if any.

〔作 用〕[For production]

第1図において、電源入力端子4の電圧を外部電源によ
って立上げると、ICチップ1の電源Vccは直ちに立
上る。しかし、ICチップ2の電源Vccは遅延手段3
があるため所定の遅延時間後に規定値まで立上る。
In FIG. 1, when the voltage of the power input terminal 4 is raised by an external power supply, the power supply Vcc of the IC chip 1 is immediately raised. However, the power supply Vcc of the IC chip 2 is
Therefore, it rises to the specified value after a predetermined delay time.

このため外部電源側に電源投入順序を制御する機能を必
要としないので、通常の外部電源を使用できる。また、
同じ電圧の電源入力端子を複数のチップで共用できるの
で、少ない端子で済む利点がある。勿論、ICチップ2
の電源立上りはICチップ1の電源立上りより遅(、I
Cチップ1がパワーオンリセットされた後であるから、
ICチップ1のランダム出力によりICチップ2が誤書
込みなどの誤動作をする恐れはない。
Therefore, there is no need for the external power supply to have a function to control the order in which the power is turned on, so a normal external power supply can be used. Also,
Since multiple chips can share a power input terminal with the same voltage, there is an advantage that fewer terminals are required. Of course, IC chip 2
The power rise of the IC chip 1 is slower than the power rise of the IC chip 1 (, I
This is after the C chip 1 has been power-on reset.
There is no fear that the IC chip 2 will malfunction such as erroneous writing due to the random output of the IC chip 1.

〔実施例〕〔Example〕

第2図は本発明の一実施例を示す要部回路図で、遅延手
段3の一例を示している。本例は電源入力端子4からI
Cチップ2の電源入力端子に至る配線21に抵抗Rと分
布容量Cを持たせて適度な時定数の積分回路を構成した
ものである。この積分回路による遅延時間は、入力がt
oで立上ってから出力が規定値に達するtlまでの時間
差(1゜−1(1)であり、これはC,Hの値で任意に
設定できる。
FIG. 2 is a main circuit diagram showing an embodiment of the present invention, and shows an example of the delay means 3. In FIG. In this example, from power input terminal 4 to I
The wiring 21 leading to the power input terminal of the C chip 2 has a resistance R and a distributed capacitance C to constitute an integrating circuit with an appropriate time constant. The delay time due to this integration circuit is
The time difference (1°-1(1)) from rising at o to tl when the output reaches the specified value, can be arbitrarily set by the values of C and H.

この遅延手段はトランジスタと組合せてもよい。This delay means may be combined with a transistor.

即ちICチップ2の電源端子を電源入力端子4へ接続す
る配線21中に該トランジスタを挿入し、第2図の遅延
手段の出力で該トランジスタのベース電流を制御して、
所定の遅延後に該トランジスタがオンになり、ICチッ
プ2が電源入力端子4より給電されるようにする。この
方式では遅延手段3による電力消費を低減できる。
That is, the transistor is inserted into the wiring 21 connecting the power supply terminal of the IC chip 2 to the power supply input terminal 4, and the base current of the transistor is controlled by the output of the delay means shown in FIG.
After a predetermined delay, the transistor is turned on and the IC chip 2 is powered from the power input terminal 4. With this method, power consumption by the delay means 3 can be reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によれば、2つ以上のICチッ
プを用いた半導体回路装置において、電源入力端子を増
やすことなく各ICチップへの電源投入順序を制御でき
るので、電源投入直後の回路動作も確実を期すことが出
来、係る半導体回路装置の性能向上に寄与するところが
大きい。
As explained above, according to the present invention, in a semiconductor circuit device using two or more IC chips, it is possible to control the order in which power is applied to each IC chip without increasing the number of power input terminals, so that the circuit immediately after power is turned on can be controlled. Operation can also be ensured, which greatly contributes to improving the performance of such semiconductor circuit devices.

【図面の簡単な説明】 第1図は本発明の原理説明図、 第2図は本発明の実施例を示す説明図、第3図は従来の
マルチチップ■ Cカードの構成 図である。 図中、 1゜ 2はICチップ、 3は遅延手段、 は電源入力端子、 20は基板である。 出 願 人
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a configuration diagram of a conventional multi-chip ■C card. In the figure, 1.2 is an IC chip, 3 is a delay means, is a power input terminal, and 20 is a board. applicant

Claims (1)

【特許請求の範囲】[Claims] 1、基板(20)上に2以上の独立したICチップ(1
、2)を搭載し、該ICチップ(1、2)間で信号の授
受を行う半導体回路装置において、電源投入時に第1の
ICチップ(1)より遅れて動作させる第2のICチッ
プ(2)に対し、該第1のICチップ(1)に直接電源
を供給する電源入力端子(4)から遅延手段(3)を介
して電源を供給するようにしてなることを特徴とする半
導体回路装置。
1. Two or more independent IC chips (1
. ), a semiconductor circuit device characterized in that power is supplied from a power input terminal (4) that directly supplies power to the first IC chip (1) via a delay means (3). .
JP1009154A 1989-01-18 1989-01-18 Semiconductor circuit device Pending JPH02189614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1009154A JPH02189614A (en) 1989-01-18 1989-01-18 Semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1009154A JPH02189614A (en) 1989-01-18 1989-01-18 Semiconductor circuit device

Publications (1)

Publication Number Publication Date
JPH02189614A true JPH02189614A (en) 1990-07-25

Family

ID=11712702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1009154A Pending JPH02189614A (en) 1989-01-18 1989-01-18 Semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPH02189614A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444006U (en) * 1990-08-20 1992-04-14
JP2001246054A (en) * 2000-03-06 2001-09-11 Sophia Co Ltd Game machine
US6329852B1 (en) 1999-06-23 2001-12-11 Hyundai Electronics Industries Co., Inc. Power on reset circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444006U (en) * 1990-08-20 1992-04-14
US6329852B1 (en) 1999-06-23 2001-12-11 Hyundai Electronics Industries Co., Inc. Power on reset circuit
JP2001246054A (en) * 2000-03-06 2001-09-11 Sophia Co Ltd Game machine

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