US7796459B2 - Memory voltage control circuit - Google Patents
Memory voltage control circuit Download PDFInfo
- Publication number
- US7796459B2 US7796459B2 US12/057,377 US5737708A US7796459B2 US 7796459 B2 US7796459 B2 US 7796459B2 US 5737708 A US5737708 A US 5737708A US 7796459 B2 US7796459 B2 US 7796459B2
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- US
- United States
- Prior art keywords
- fet
- slot
- memory
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Definitions
- the present invention relates to control circuits, and particularly to a memory voltage control circuit.
- a typical personal computer is comprised of a motherboard, interface cards, and peripheral accessories.
- the motherboard is the heart of the personal computer.
- the motherboard In addition to the central processing unit (CPU), the chip set and slots for installing the interface cards, the motherboard also includes slots for installing memory modules.
- CPU central processing unit
- the motherboard In addition to the central processing unit (CPU), the chip set and slots for installing the interface cards, the motherboard also includes slots for installing memory modules.
- DDR2 Double Data Ram II
- DDR3 Double Data Ram III
- DDR2s are cheaper than DDR3s, DDR2s are still in demand in the market to be used on the main board.
- the difference in operating DDR2 versus DDR3 includes the following: DDR2 utilizes 1.8V VDD and 0.9V VTT, while DDR3 utilizes 1.5V VDD and 0.75V VTT.
- DDR2 utilizes 1.8V VDD and 0.9V VTT
- DDR3 utilizes 1.5V VDD and 0.75V VTT.
- no motherboard is compatible with both DDR3 and DDR2.
- An exemplary memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit.
- the two slots are able to efficiently process different memory types.
- the control circuit receives memory identification signals from the two slots.
- the control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals.
- the memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot.
- FIG. 1 is a block diagram of a memory voltage control circuit in accordance with an exemplary embodiment of the present invention.
- FIG. 2 is a circuit diagram of FIG. 1 .
- a memory voltage control circuit in accordance with an exemplary embodiment of the present invention includes a control circuit 10 , a voltage conversion circuit 20 , a switch circuit 30 , a first slot 40 (for receiving a DDR2 memory for example), and a second slot 50 (for receiving a DDR3 memory for example).
- the control circuit 10 receives memory identification signals from the two slots 40 , 50 and controls the output of the voltage conversion circuit 20 based on the memory identification signals.
- the memory identification signal of the second slot 50 determines whether the switch circuit 30 is to be turned on or off. This will control whether the output of the voltage conversion circuit 20 will go to the first slot 40 or the second slot 50 .
- the control circuit 10 includes five resistors R 1 -R 5 and two field effect transistors (FETs) Q 1 and Q 2 .
- the gate of the FET Q 1 is connected to a memory identification pin GNDDET of the first slot 40 , and connected to the system standby power source 5V_SB_SYS via the resistor R 1 .
- the source of the FET Q 1 is grounded.
- the drain of the FET Q 1 is connected to the system standby power source 5V_SB_SYS via the resistor R 2 .
- a memory identification pin GNDDET of the second slot 50 is connected to the drain of the FET Q 1 and the gate of the FET Q 2 .
- the source of the FET Q 2 is grounded.
- the drain of the FET Q 2 is grounded via the resistors R 3 and R 4 connected in series.
- a node between the resistors R 3 and R 4 is connected to an output N of the voltage conversion circuit 20 via the resistor R 5 .
- the voltage conversion circuit 20 includes four FETs Q 3 ⁇ Q 6 , three resistors R 6 ⁇ R 8 , three capacitors C 1 ⁇ C 3 , and two inductances L 1 and L 2 .
- the gate of the FET Q 3 is connected to the gate of the FET Q 4 , as well as a gating pin VRAM_UGATE of a power regulator (not shown) via the resistor R 6 .
- a node between the drain of the FET Q 3 and the drain of the FET Q 4 is grounded via the capacitor C 1 , and is also connected to a dual power source 5V_DUAL via the inductance L 1 .
- a node between the source of the FET Q 3 and the drain of the FET Q 5 is connected to a node between the source of the FET Q 4 and the drain of the FET Q 6 , and grounded via the resistor R 8 and the capacitor C 2 connected in series, and connected to the output N via the inductance L 2 .
- the output N is grounded via the capacitor C 3 .
- the gate of the FET Q 5 is connected to the gate of the FET Q 6 , and is also connected to a gating pin VRAM_LGATE of the power regulator via the resistor R 7 .
- the sources of the FETs Q 5 and Q 6 are grounded.
- the gating pins VRAM_UGATE and VRAM_LGATE of the power regulator respectively receive control signals to the voltage conversion circuit 20 .
- the switch circuit 30 includes three FETs Q 7 ⁇ Q 9 , three resistors R 9 ⁇ R 11 , and two diodes D 1 and D 2 .
- the gate of the FET Q 7 is connected to a memory identification pin GNDDET of the second slot 50 .
- the sources of the FETs Q 7 and Q 8 are grounded.
- the drain of the FET Q 7 is connected to the gate of the FET Q 8 , and connected to the anode of the diode D 1 via the resistor R 9 .
- the anode of the diode D 1 is connected to the system standby power source 5V_SB_SYS.
- the anode of the diode D 2 is connected to a system power source 12V_SYS.
- a node between the cathode of the diode D 1 and the cathode of the diode D 2 is connected to a node between the drain of the FET Q 8 and the gate of the FET Q 9 via the resistor R 10 .
- the drain of the FET Q 9 is connected to the power input pin P of the second slot 50 and the output N.
- the source of the FET Q 9 is connected to the power input pin P of the first slot 40 , and grounded via the resistor R 11 .
- the memory identification pin GNDDET of the second slot 50 When only the DDR3 memory is plugged into the second slot 50 , the memory identification pin GNDDET of the second slot 50 outputs a low level memory identification signal.
- the FET Q 1 is turned on.
- the FET Q 2 is turned off.
- the FETs Q 7 and Q 9 are turned off.
- the FET Q 8 is turned on.
- the voltage conversion circuit 20 outputs a 1.5V voltage to the power input pin P of the second slot 50 via the voltage divider resistors R 4 and R 5 .
- the memory identification pin GNDDET of the first slot 40 When only the DDR2 memory is plugged into the first slot 40 , the memory identification pin GNDDET of the first slot 40 outputs a low level memory identification signal.
- the FET Q 1 is turned off.
- the FET Q 2 is turned on.
- the FETs Q 7 and Q 9 are turned on.
- the FET Q 8 is turned off.
- the voltage conversion circuit 20 outputs a 1.8V voltage to the power input pin P of the first slot 40 via the voltage divider resistors R 3 , R 4 , and R 5 .
- the memory identification pin GNDDET of both slots 40 , 50 output a low level memory identification signal.
- the FETs Q 1 and Q 2 are turned off.
- the FETs Q 7 and Q 9 are turned off.
- the FET Q 8 is turned on.
- the voltage conversion circuit 20 outputs a 1.5V voltage to the power input pin P of the second slot 50 .
- the motherboard functions normally.
- the control circuit 10 of the memory voltage control circuit receives memory identification signals from the two slots 40 , 50 and controls the output voltage of the voltage conversion circuit 20 accordingly based on the memory identification signals. At the same time, the memory identification signals determine whether the switch circuit 30 is to be turned on or off. In turn, this governs whether the output voltage of the voltage conversion circuit 20 goes to slot 40 or slot 50 .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Electronic Switches (AREA)
- Dram (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200710203217 | 2007-12-19 | ||
CN200710203217.2 | 2007-12-19 | ||
CNA2007102032172A CN101464716A (en) | 2007-12-19 | 2007-12-19 | Internal memory voltage control circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090161472A1 US20090161472A1 (en) | 2009-06-25 |
US7796459B2 true US7796459B2 (en) | 2010-09-14 |
Family
ID=40788451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/057,377 Expired - Fee Related US7796459B2 (en) | 2007-12-19 | 2008-03-28 | Memory voltage control circuit |
Country Status (2)
Country | Link |
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US (1) | US7796459B2 (en) |
CN (1) | CN101464716A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9379613B1 (en) * | 2014-12-18 | 2016-06-28 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Power supply circuit and notebook computer including the same |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102009002191B4 (en) * | 2009-04-03 | 2012-07-12 | Infineon Technologies Ag | Power semiconductor module, power semiconductor module assembly, and method of making a power semiconductor module assembly |
CN102193617A (en) * | 2010-03-17 | 2011-09-21 | 鸿富锦精密工业(深圳)有限公司 | Power control circuit |
JP6048171B2 (en) * | 2013-01-30 | 2016-12-21 | ブラザー工業株式会社 | Image processing device |
CN105652994A (en) * | 2014-11-11 | 2016-06-08 | 鸿富锦精密工业(武汉)有限公司 | Voltage switching device |
CN106251904A (en) * | 2016-07-26 | 2016-12-21 | 深圳市智微智能科技开发有限公司 | Memory voltage regulating method and circuit |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020003740A1 (en) * | 2000-01-04 | 2002-01-10 | Nai-Shung Chang | System for automatic generation of suitable voltage source on motherboard |
US6621754B1 (en) * | 2002-07-10 | 2003-09-16 | Micro-Star Int'l Co., Ltd. | Memory interface control circuit |
US7301847B2 (en) * | 2004-03-12 | 2007-11-27 | Wistron Corp. | Method and device for a main board commonly associated with DDR2 or DDR1 |
US20080225499A1 (en) * | 2007-03-15 | 2008-09-18 | Terence Chin Kee Meng | Selectively supporting different memory technologies on a single motherboard |
US20090046418A1 (en) * | 2007-08-17 | 2009-02-19 | Hon Hai Precision Industry Co., Ltd. | Motherboard for supporting different types of memories |
-
2007
- 2007-12-19 CN CNA2007102032172A patent/CN101464716A/en active Pending
-
2008
- 2008-03-28 US US12/057,377 patent/US7796459B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020003740A1 (en) * | 2000-01-04 | 2002-01-10 | Nai-Shung Chang | System for automatic generation of suitable voltage source on motherboard |
US6621754B1 (en) * | 2002-07-10 | 2003-09-16 | Micro-Star Int'l Co., Ltd. | Memory interface control circuit |
US7301847B2 (en) * | 2004-03-12 | 2007-11-27 | Wistron Corp. | Method and device for a main board commonly associated with DDR2 or DDR1 |
US20080225499A1 (en) * | 2007-03-15 | 2008-09-18 | Terence Chin Kee Meng | Selectively supporting different memory technologies on a single motherboard |
US20090046418A1 (en) * | 2007-08-17 | 2009-02-19 | Hon Hai Precision Industry Co., Ltd. | Motherboard for supporting different types of memories |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9379613B1 (en) * | 2014-12-18 | 2016-06-28 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Power supply circuit and notebook computer including the same |
Also Published As
Publication number | Publication date |
---|---|
US20090161472A1 (en) | 2009-06-25 |
CN101464716A (en) | 2009-06-24 |
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AS | Assignment |
Owner name: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, NING;QIAN, CHENG;HUANG, YONG-ZHAO;REEL/FRAME:020715/0460 Effective date: 20080108 Owner name: HON HAI PRECISION INDUSTRY CO., LTD.,TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, NING;QIAN, CHENG;HUANG, YONG-ZHAO;REEL/FRAME:020715/0460 Effective date: 20080108 Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WANG, NING;QIAN, CHENG;HUANG, YONG-ZHAO;REEL/FRAME:020715/0460 Effective date: 20080108 |
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Year of fee payment: 4 |
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Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.) |
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LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
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STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
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FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20180914 |