JPH02189530A - Camera equipped with resetting function for control means - Google Patents

Abstract

PURPOSE:To operate a camera normally by outputting a reset signal from one CPU to the other CPU when the power source is turned on in the case of runaway of one CPU. CONSTITUTION:A reset circuit is connected to a sub-CPU 4 and when the reset circuit resets the sub-CPU 4 in the case of applying the power source 34, the sub-CPU 4 outputs the reset signal to the main CPU 2 to be reset. Further, when a specific response signal to a monitoring signal for handling the un expected runaway of one of the CPUs 2 and 4 is not inputted to one CPU, the CPU outputs the reset signal to the other CPU. Consequently, the CPU which is abnormal can be reset.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention enables the camera to operate normally by appropriately resetting the CPU that is installed in the camera and controls the camera's operation and processes information. The present invention relates to a camera having a reset function of a control means as described above.

[Conventional technology]

To make photography easier.

Cameras, especially compact cameras, that are equipped with automatic exposure functions, autofocus functions, automatic film feeding functions, automatic flash firing functions, etc. are becoming popular. It also has a date function that imprints the shooting date and time onto the film frames.

This type of camera has a main CPU that controls the operations of the automatic exposure circuit, autofocus circuit, film feeding means, shutter drive means, strobe circuit, etc. so that they operate according to an appropriate sequence, and a main CPU that controls the date function. In addition to having a clock circuit for this purpose, the camera is equipped with two CPUs, including a sub-CPU that displays the date on a liquid crystal display means for imprinting the film and for monitoring.

These two CPUs are connected by an information line, but in the past, the main CI'U was in charge of controlling camera operations, the sub CPU was in charge of the date function, and the data was sent from the main CPU in conjunction with the camera's release operation. The date is imprinted by the sub CPU based on the output signal. Main CPU
The sub-CPUs and sub-CPUs operate independently, and there is no means for dealing with malfunctions in one of them.

[Problem that the invention seeks to solve]

However, during camera operation, noise is generated from the film feeding motor and the zoom motor of the photographic lens, and the camera is also subject to static electricity, strobe noise, external noise, and the like. When these noises affect the CPU,
There is a risk that the CPU will run out of control. In particular, the main CPU
When the camera goes out of control, the information processing of the number of film shots, automatic exposure, autofocus, etc. will be affected.1 For example, the camera may end up rewinding the film even though there is still enough film remaining. There is a risk that an inconvenience may occur, such as the release button not being released even though it is pressed.

In such a case, it is necessary to reset the CPU to stop the runaway, but conventional methods do not have a special reset means, so if a runaway occurs, the power battery must be removed and the CPU can be stopped. After that, the power supply battery is loaded and the power is turned on again.

For this reason, it is conceivable to provide the camera with a button for resetting the CPU, but if the photographer carelessly operates the button, information such as the number of film sheets will be erased, and the number of films loaded will be lost. I end up doing something like doing a first frame set like I used to do. For this reason, it is not preferable to allow the photographer to perform a reset operation easily.

Therefore, the present invention provides a camera equipped with a reset function of the control means, which allows a main CPU and a sub-CPU to be connected to each other, and by discovering an abnormality in the CPU in advance, a CPU in which an abnormality has occurred can be reset. is intended to provide.

[Means for solving problems]

In order to achieve the above object, the camera equipped with the reset function of the control means according to the present invention has a main CPU responsible for controlling the operation of the camera and a sub CPU responsible for the date function as a reset function when the power is turned on. In the camera equipped with the above-mentioned camera, a reset circuit is connected to the sub-CPU, and when the sub-CPU is reset by the reset circuit when the power is turned on, a reset signal is output from the sub-CPU to the main CPU. In addition, in order to cope with the case where the CPU unexpectedly goes out of control, a monitoring signal is output from at least one of the sub CPU and the main CPU to the other at predetermined time intervals. , when a predetermined response signal to the monitoring signal is not input to one of the CPUs in E, the other CPU is reset by outputting a reset signal from the one CPU to the other CPU. Further, when an interrupt control request is made to cause the camera to perform a predetermined operation, the sub-CPU and A monitoring signal is output from at least one of the main CPUs to the other, and a predetermined response signal in response to the monitoring signal is sent to the one of the main CPUs.
The feature is that when the signal is not input to U, the one CPU outputs a reset signal to the other CPU, thereby resetting the other CPU.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A camera equipped with a reset function of a control means according to the present invention will be specifically described below based on the illustrated embodiment.

FIG. 1 is a schematic block diagram showing the control mechanism of this camera, which consists of a main CPU 2 and a sub CPU 4.
It is mainly composed of two CPUs. The main CPU 2 is placed on the side of the camera body, and the sub CPU 4 is placed on the back cover of the camera.

As shown in FIG. 1, the main CPU 2 includes various operating switches 6, an autofocus (AF) circuit 8, an autoexposure (AE) circuit 10. Lens driving means 12, shutter driving means 14, film feeding means 16, strobe circuit 18
, the zoom driving means 20, etc., and necessary information is exchanged.

The operation switch 6 includes a shutter button, a zoom switch, and the like. The AF circuit 8 exchanges distance measurement data obtained by measuring the distance to the subject with the main CPU 2. The AE circuit 10 exchanges photometric data obtained by measuring subject brightness with the main CPU 2. The lens U moving means 12 drives the photographing lens to the in-focus position at the time of release based on distance measurement data obtained by the AF circuit 8. The shutter driving means 14 controls the aperture, shutter speed, etc. at the time of release based on the photometric data obtained by the AE circuit 10. The film feeding means 16 feeds the film to the first frame when the film is loaded, winds the film one frame after release in preparation for the next shooting, and rewinds the film after all frames have been shot. It is something. The strobe circuit 18 causes the strobe to emit light, and the strobe also emits light when the brightness is insufficient based on the photometric data obtained by the AE circuit 10. The zoom driving means 20 moves the photographing lens forward and backward along the optical axis in order to change the photographing magnification in a camera equipped with a zoom mechanism.

For example, when the shutter button is pushed in to take a picture, the first stage switch is turned on when it is pushed in about half way, the AF circuit 8 measures the distance, the AE circuit 10 measures the light, and the distance measurement data and Photometric data is acquired. Furthermore, when the shutter button is pressed, the second stage switch is turned on, the photographing lens is driven by the lens driving means 12 to focus, and the shutter opening circuit 14 releases the shutter to expose the film. After the release, the film is wound up by the film feeding means 16.

The sub CPU 4 receives and processes information sent by operating various mode set switches 22, and provides the processed information to the main CPU 2 via a serial transfer line 25 in the form of a serial signal.

Various modes include automatic shooting mode, self-shooting mode, and strobe shooting mode. Also, the main CPU
The information processed in step 2 is received as a serial signal via a serial transfer line 25, and is processed and stored. That is, the main CPU 2 does not save information, and the sub CPU 4 does not save the information. Furthermore, the sub-CPU 4 is provided with a clock circuit, which stores the date and time, and sends a command to imprint the date on the film as necessary. Further, a liquid crystal display means (LCD) 24 is connected to the sub CPU 4.
This LCD 24 is driven by U4. This LCD
In the information displayed by 24.

Film number information (number of shots taken or remaining number)
, 24a, film feed information 24b, date/time information 24c, strobe light! 1I24d, strobe non-flash information 24e, daytime sync ° (forced strobe flash) information 24f, self-shooting information 24g, distant view/night view shooting information 24h, close-up shooting information 241, remaining battery level information 24
j, date/time imprint information 24, etc.

The reset signal output port of the sub CPU 4 is connected to the reset port 2a of the main CPU 2 by a main reset information line 26, and the sub reset port 4a of the sub CPU 4 is connected to the main CPU 2 by a sub reset information line 28.
connected to the reset signal output port of the main CPU
Each of them is reset by a reset signal sent from the CPU 2 or the sub CPU 4.

Next, the reset function when the power is turned on will be explained based on FIGS. 2 and 3. As shown in FIG. 2, the output signal of the reset circuit 30 is input to the sub-reset port 4a of the sub-CPU 4. In addition, the main CPU
Information 1s28 for inputting a reset signal from 2 to the sub-reset port 4a is omitted. A power supply battery 34 is connected to the reset circuit 30 via a main switch 32.
In addition, this power supply battery 34 is used for the main CPU 2 and sub CPU 4.
The power supply is closed.

Then, the power supply battery 34 is loaded and the main switch 32 is turned on (step 301), and the I10 port is initially set (step 302).

When the sub CPU 4 is initialized, its OA port 4
A reset signal is output from b (step 303).
, this reset signal is input to the reset port 2a of the main CPU 2. A program that outputs a reset signal is included in the initial processing after the main CPU 2 is reset, and after the reset is performed, the sub CPU
A reset completion signal is output to IA port 4C of No.4. Then, in step 304, the sub CPU 4 determines whether or not this reset completion signal is received. If the reset completion signal is input, the sub CPU 4 executes a program that performs normal processing in step 305.

If the reset completion signal is not input to the sub CPU 4, the determination in step 304 is repeated for a predetermined time (step 306); if the predetermined time has elapsed, the process returns to step 303 and the reset signal is sent to the main CPU 2 again. will be output.

Note that if the reset completion signal is not obtained from the main CPU 2, there is an abnormality in the main CPU 2, and appropriate photography will not be performed.
None of the sub CPUs 4 execute normal programs.

Next, based on FIGS. 4 and 5, a description will be given of monitoring at predetermined time intervals in order to reset the CPU when it suddenly goes out of control. As shown in Figure 4, sub CP
The output signal strength of the reset circuit 30 is input to the sub-reset port 4a of U4 via a diode 36.

A reset signal is input from the main CPU 2 to the sub-reset port 4a via an information line 28 and a diode 38. A power battery 34 is connected to the reset circuit 30 via a main switch 32, and this power battery 34
is used as a power source for the main CPU 2 and sub CPU 4.

When the sub CPU 4 is executing a normal program and a predetermined time has elapsed, interrupt control is performed (step 501). As a result, from sub CPU4 to main C
The CPU 2 is accessed (step 502), and a response signal is requested from the main CPU 2. The exchange of these information can benefit serial data transfer.

In step 503, the presence or absence of this response signal is determined, and if the response signal is input to the sub CPU 4, a normal program is executed (step 506).

When there is no response signal from the main CPU2.

After waiting for the elapse of a predetermined time (step 504), the sub CPU 4 outputs a reset signal to the main CPU 2 (step 505). In other words, if a predetermined response signal is not input from the main CPU 2 to the sub CPU 4, it is considered that the main CPU 2 has gone out of control and is not performing the predetermined arithmetic processing.
Main CP outputs a reset signal (step 505)
This will prevent U2 from going out of control.

In addition, in this embodiment, from the sub CPU 4 to the main CPU 2
Although we explained the case when accessing the main CPU
2, the status of the sub CPU 4 can be monitored by programming in the same way.

Next, based on FIGS. 6a and 6b, the main CPU
The monitoring for resetting 2 will be explained.

When the mode set switch 22 for flash photography mode, self-photography mode, ]] middle synchronization mode, etc. is operated, 2-interrupt control processing is started (step 601).
, First, the main CPU 2 is accessed from the sub CPU 4 (step 602).

In the main CPU 2, interrupt control processing is started by access from the sub CPU 4 (step 611).
If it is in a normal operating state, it outputs a response signal in response (step 612) and performs interrupt processing for interrupt control (step 613). In addition, the main CP in this case
Information is exchanged between U2 and sub CPU 4 using serial signals.

On the other hand, the sub CPU 4 determines whether or not there is the response signal from the main CPU 2 (step 603), and if the signal is input to the sub CPU 4, an interrupt control program is executed (step 606).

When there is no response signal from the main CPU2.

After waiting for a predetermined time to elapse (step 604), the sub CPU 4 outputs a reset signal to the main CPU 2 (step 605). In other words, if the predetermined response signal is not input from the main CI U2 to the sub CPU 4, it is considered that the main CPU U2 has gone out of control and is not performing the predetermined arithmetic processing, so a reset signal is output. (step 505) to prevent the main CPU 2 from running out of control. If, for example, the self-timer mode is set according to the mode set switch 22 operated in step 606, the program returns to the normal program after the self-photographing process is completed (step 607).

In addition, in this embodiment, from the sub CPU U4 to the main CPU
We explained the case of accessing U2, but main C
By programming the PU2 in the same way, the status of the sub CPU4 can be monitored. In this case, a monitoring signal is output when an operating switch 6 such as a shutter button or a zoom switch is operated in connection with the main CPU 2.

〔Effect of the invention〕

As explained above, according to the camera equipped with the reset function of the control means according to the present invention, when the power is turned on, one CPU outputs a reset signal to the other CPU. The CPU is reliably reset and the camera can operate normally.

Also, since one CPU monitors the other CPU at predetermined intervals, if the other CPU is out of control due to the influence of external noise, the other CPU can be reset. It will be restored to normal operation. Moreover, if both CPUs mutually monitor each other, even if one of them goes out of control, the normal program can be quickly restored. Note that after outputting a reset signal from one CPU to the other CPU,
If one CPU provides the other CPU with the information regarding the camera status stored in the memory, the other CPU can
The PU can be returned to the state immediately before the runaway.

In addition, when various mode set switches and activation switches are operated, one CP tJ monitors the other CPU, and if the other CPU goes out of control and there is an abnormality, it is reset, so the mode set switch When the mode or activation switch is operated, photography can be reliably performed in that mode.

[Brief explanation of the drawing]

The drawings show a preferred embodiment of a camera having a reset function of the control means according to the present invention, and FIG. 1 is a schematic block diagram showing the control mechanism of this camera. 2 and 3 are diagrams for explaining the reset function when the power is turned on, with FIG. 2 being a schematic circuit diagram and FIG. 3 being a flowchart. 4 and 5 are diagrams for explaining a reset function that monitors CPU runaway at predetermined time intervals and resets the CPU when an abnormality occurs. FIG. 4 is a schematic circuit diagram, and FIG. It is a flowchart. 6a and 6b are diagrams for explaining the reset function when an interrupt control request is made by operating the mode set switch etc. in order to operate the camera in a predetermined manner. Flowchart of Processing FIG. 6b is a flowchart of processing by the main CPU 2. 2...Main CPU 2a...Main reset port 4...Sub CPU 4a...Sub reset port 6...Activation switch 22...Mode set switch 24...L CD 30...Reset Circuit 32... Main switch 34... Power supply battery 2nd CPU-84 Figure 6a

Claims (3)

[Claims] (1) In a camera equipped with a main CPU that controls camera operations and a sub CPU that performs a date function, a reset circuit is connected to the sub CPU, and when the sub CPU is reset by the reset circuit when the power is turned on, A camera having a reset function of a control means, characterized in that the sub CPU outputs a reset signal to the main CPU, thereby resetting the main CPU. (2) In a camera equipped with a main CPU that controls camera operations and a sub CPU that performs a date function, at least one of the sub CPU and the main CPU outputs a monitoring signal to the other at predetermined intervals. , if a predetermined response signal to the monitoring signal is not input to the one CPU, the one CPU
A camera equipped with a reset function of a control means, characterized in that the other CPU is reset by outputting a reset signal from the U to the other CPU. (3) In a camera equipped with a main CPU that controls camera operations and a sub CPU that performs a date function, when an interrupt control request is made to cause the camera to perform a predetermined operation, the sub CPU and main CPU
At least one of the PUs outputs a monitoring signal to the other CPU, and if a predetermined response signal to the monitoring signal is not input to the one CPU, the one CPU
A camera equipped with a reset function of a control means, characterized in that the other CPU is reset by outputting a reset signal from the U to the other CPU.