JP2575056B2 - Camera having information signal confirmation means - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applicable to a case where information is exchanged by serial transfer between a plurality of CPUs mounted on a camera and controlling operation of the camera and processing information. The present invention relates to a camera having means for confirming whether the information is appropriate.

[Conventional technology]

2. Description of the Related Art Cameras equipped with an automatic exposure function, an automatic focus function, an automatic film feeding function, a flash automatic light emission function, and the like, in particular, a compact camera, have been widely used in order to easily perform photography. A date function for imprinting the shooting date and time on the film frame is also provided.

In this type of camera, a main CPU that controls the operation of an automatic exposure circuit and an auto focus circuit, a film feeding unit, a shutter driving unit, a strobe circuit, and the like are operated according to an appropriate sequence, and a date function is controlled. For this purpose, a clock circuit is provided, and two CPUs are mounted: a sub-CPU for displaying the date on liquid crystal display means for imprinting a film and a monitor.

Conventionally, information on operation control of a camera, such as display of the number of films, flash emission, self-photographing, etc., is displayed on the camera body side, and information on date and time is displayed on the back cover of the camera. That is, liquid crystal display means are provided at two places, the camera body side and the back cover, and circuits for driving these are provided.
However, providing two liquid crystal display means and a drive circuit results in a complicated configuration, and the camera operator is required to obtain necessary information from each display means, which is complicated. For this reason, the display means for displaying information related to the operation of the camera and the display means for displaying date information are collectively arranged in one place,
There is one in which such information is controlled by a sub CPU (Japanese Patent Laid-Open No. 63-80238).

[Problems to be solved by the invention]

When the liquid crystal display means and the driving circuit are integrated in one place as described above, it is necessary to exchange information regarding the camera operation between the main CPU that controls the operation of the camera and the sub CPU for the date function and display control. Occurs. For each piece of information, it is conceivable to connect the respective I / O ports of the main CPU and sub CPU with information lines to transfer information in parallel, but the number of information lines becomes large and complicated. Will be. Therefore, it is preferable that this information exchange be performed by serial transfer.

However, in the operation of the camera, noise is generated from the film feeding motor and the zoom driving motor of the photographing lens, and the camera receives static electricity, strobe noise, external noise, and the like. If these noises synchronize with the clock pulse, information exchange between the main CPU and the sub CPU cannot be performed properly.

In view of the above, the present invention provides an information signal confirming means capable of determining whether or not information to be transferred is accurate when information is exchanged between two CPUs mounted on the camera by serial transfer. It is an object of the present invention to provide a camera having:

[Means for solving the problem]

For the above purpose, the camera having the information signal confirming means according to the present invention has a main CP which controls the operation of the camera.
U and a sub CPU that performs the date function.
In a camera that exchanges information between a CPU and a sub CPU by serial transfer, when information is provided from one of the main CPU and the sub CPU to the other CPU, only one The two signals are transmitted, the second signal of the two signals is obtained by inverting the first signal, and the other CPU is transmitted by comparing the two signals. It is characterized by determining whether the information is correct.

[Embodiment] A camera having an information signal confirmation unit according to the present invention will be specifically described below based on the illustrated embodiment.

FIG. 1 is a schematic block diagram showing a control mechanism of this camera. This camera has two CPs, a main CPU 2 and a sub CPU 4.
It is composed mainly of U. The main CPU 2 is arranged on the camera body side, and the sub CPU 4 is arranged on the camera back cover.

As shown in FIG. 1, the main CPU 2 includes various operation switches 6, an auto focus (AF) circuit 8, an automatic exposure (A)
E) Circuit 10, lens driving means 12, shutter driving means 1
4. Signals are exchanged with the film feeding means 16, the strobe circuit 18, the zoom driving means 20 and the like to exchange necessary information. The operation switch 6 includes a shutter button, a zoom switch, and the like. The AF circuit 8 exchanges distance measurement data obtained by measuring the distance to the subject with the main CPU 2. The AE circuit 10 transmits and receives photometric data obtained by measuring the luminance of the subject to and from the main CPU 2. The lens driving means 12 drives the photographing lens to the in-focus position at the time of release based on the distance measurement data obtained by the AF circuit 8. The shutter driving unit 14 controls the aperture, shutter speed, and the like at the time of release, based on the photometric data obtained by the AE circuit 10. The film feeding means 16 feeds the film to the first frame when the film is loaded, winds up the film by one frame after the release to prepare for the next photographing, and rewinds the film after all the frames have been photographed. Things. The strobe circuit 18 emits a strobe, and the strobe emits light even when the luminance is insufficient due to the photometry data obtained by the AE circuit 10. The zoom driving means 20 moves the photographing lens along the optical axis in order to change the photographing magnification with a camera having a zoom mechanism.

For example, when the shutter button is depressed for photographing, the first-stage switch is turned on when the shutter button is depressed to almost half, the distance is measured by the AF circuit 8, the photometry is performed by the AE circuit 10, and the distance measurement data and photometry are measured. Data is obtained. Further, when the shutter button is depressed, the second-stage switch is turned ON, the photographing lens is driven by the lens driving means 12, and the lens is focused, and the shutter is released by the shutter driving circuit 14 to expose the film. After the release, the film is wound up by the film feeding means 16.

The sub CPU 4 receives and processes information transmitted by operating the various mode set switches 22, and provides the processed information to the main CPU 2 via a serial transfer line 25 by a serial signal. The various modes include an automatic shooting mode, a self shooting mode, and a flash shooting mode. Also, the information processed by the main CPU 2 is received as a serial signal via the serial transfer line 25, processed, and stored. That is, information is not stored in the main CPU 2, and the storage is performed by the sub CPU 4. Further, the sub CPU 4 is provided with a clock circuit, which stores a date and time, and sends a command for imprinting the date and the like on the film as needed. Further, a liquid crystal display (LCD) 24 is connected to the sub CPU 4, and the LCD 24 is driven by the sub CPU 4. The information displayed by the LCD 24 includes film number information (the number of photographed or remaining images) 24a, film feed information 24b, date / time information 24c, strobe light emission information 24d, and strobe non-lighting information 24.
e, Daytime synchro (forced flash) information 24f, Self shooting information 24g, Far / Night view shooting information 24h, Close-up shooting information 24
i, Battery level information 24j, Date / time imprint information 24
and k.

The reset signal output port of the sub CPU 4 is
The main reset information line 26 is connected to the reset port 2a of the CPU 2 and the sub reset port 4a of the sub CPU 4 is connected to the reset signal output port of the main CPU 2 by the sub reset information line 28, and is transmitted from the main CPU 2 or the sub CPU 4. Each is reset by a reset signal.

FIG. 2 is a table showing an example of an information signal transmission mode.

SIo1 indicates a case where camera information is transmitted from the main CPU 2 to the sub CPU 4. For example, when the camera is released and shooting is completed, the film is wound up by one frame in preparation for the next shooting. Information such as the number of shots of the film being used and the number of shots of the film is a sub CP
It is stored in U4, and the film winding control is the main
Since the processing is performed by the CPU 2, information indicating that the film has been wound up by one frame is provided from the main CPU 2 to the sub CPU 4. As shown in the column of SIo1 in FIG. 2, a command including data not to be transmitted from the main CPU 2 is output. The sub CPU 4 stores this signal. Furthermore, from the main CPU2,
A signal (check sum) equal to the output signal is output. In the sub CPU 4, the stored first signal and 2
Check the checksum output at the second time, and if they are equal, judge that the output information has been transmitted normally, and send a command and checksum to the main CPU 2 indicating that the information was received properly. Output. If noise is mixed in the information signal, the command output from the main CPU 2 and the checksum will be different, and in this case, a retransmission request signal will be output from the sub CPU 4 to the main CPU 2. .

The command and the checksum may be transmitted as the same signal.However, in order to detect a hardware failure such as disconnection or short-circuit of the signal line, the checksum is inverted from the command. It is desirable that In other words, in the case of an 8-bit signal, if the command outputs data with “10010101”, the checksum is a signal inverted to “01101010”. Sub CPU4
Then, it is possible to determine that there is no abnormality in the output information signal when each digit of the command and the checksum is "1". If there is a hardware failure such as disconnection or short circuit of the signal line, the received command and data are both equal to “00000000” or “1111”.
1111 ", so that it is possible to detect an abnormality.

SIo2 indicates a case where the main CPU 2 requests the sub CPU 4 for necessary information. For example, when the mode set switch 22 is operated, it is necessary to operate the camera according to the mode.
CPU2 requests sub CPU4 to output. As shown in the column of SIo2 in FIG. 2, INFO corresponding to the information requested from the main CPU 2 is output, and further a checksum is output. In the same manner as described above, the sub CPU 4 compares INfo with the checksum, and if the signals are equal, determines that the signal has been normally received and outputs the status and checksum relating to the requested information. If the signal is abnormal due to noise, the sub CPU 4 sends the retransmission request signal to the main CP.
Output to U2.

SIo3 indicates a case where a series of information is provided from the main CPU2 to the sub CPU4. In this case, a signal relating to each information is output continuously for several bytes. SIo3
Then, as shown in FIG. 2, a header and a checksum for transmitting a series of information are output. The header outputs a message indicating that a series of information is to be transmitted and, for example, the number of bytes to be transmitted regarding the information. The sub CPU 4 compares the header with the checksum, and if they do not match, requests retransmission. If there is no abnormality, the sub CPU 4 performs main
Receives information sent from CPU2.

Next, the operation procedure will be described based on the flowcharts shown in FIGS.

First, transmission and reception of an 8-bit signal will be described with reference to FIG. When an 8-bit signal transfer is started from the main CPU 2 (step 401), the signal DSR to that effect is set to 0 to serially transfer information to the sub CPU 4 (step 40).
2) This is serially transferred to the sub CPU 4 and waits for the reception signal DTR to be output from the sub CPU 4 (step 4).
03).

When the DSR signal is input from the main CPU 2, the sub CPU 4 prepares for serial transfer (step 422), sets the DTR signal to 0, and transmits it to the main CPU 2 (step 42).
3). If the main CPU 2 receives this DTR signal,
Serially transfer the necessary information to CPU4 (step 40
4), set DSR signal to 1 and send to sub CPU4 (step
405).

On the other hand, the sub CPU 4 waits for the end of the serial transfer of necessary information (step 424), and if the transfer is completed, waits for a further predetermined time (step 425) to determine the DSR (step 426). At this time, if the DSR is 1, the transfer preparation signal DTR is set to 1 (step 427), the serial transfer end processing is performed (step 428), and the process ends normally (step 42).
9).

When DTR is set to 1 by the sub CPU 4 in the main CPU 2 (step 406), the serial transfer process is terminated (step 407) and the process is normally terminated (step 408).

If the DTR is not set to 0 in step 423 of the sub CPU 4 even if the predetermined time has elapsed in step 403, an error is set (step 409), and the process in a state where the serial transfer is interrupted is performed (step 411). ) The interruption ends (step 412). If the DTR is not set to 1 in step 427 of the sub CPU 4 even if the predetermined time has elapsed in step 406,
After the error is set (step 410), the operation is terminated (step 412).

In step 424 of the sub CPU 4, if the serial transfer is not completed even after the lapse of the predetermined time, the DTR is set to 1 after further waiting for the predetermined time (step 431), the serial transfer is interrupted, and step 432) is interrupted (Step 43
3).

If the DSR remains at 0 in step 426 of the sub CPU 4, the interruption ends (step 433). This is the DSR
Is set to 1 when the serial transfer of the main CPU 2 is completed, and this is sent to the sub CPU 4.
In some cases, the transfer is determined to be completed in step 424 even though the serial transfer is not completed after being transmitted to U4.
In this case, the transferred information is inappropriate, and the DSR remains 0, so this is determined in step 426. That is, the sub CPU 4 terminates the interruption (step 433) whether the transfer of information is too slow (step 424) or too early (step 426).

An operation procedure for confirming whether or not the information provided by performing the 8-bit transfer as described above is normal will be described with reference to FIG.

FIG. 3 shows a case where the main CPU 2 needs to obtain a reception signal from the sub CPU 4, that is, in FIG.
The case indicated by o2 is shown. When SIo1 or SIo2 starts (step 301), the error counter and the error flag are cleared (step 302). Then D
TR is determined (step 303), and when this becomes 1, 8
A bit signal is output (step 304). Step 3
If the DTR is 0 in 03, the previous processing in the sub CPU 4 has not been completed, and the process waits until this is completed.

When signal output starts (step 304), the sub CPU
At 4, a serial signal is received (step 322).

After transferring the first 8-bit signal, the main CPU 2 waits for a predetermined time to elapse (step 305), and transfers the second signal (step 306). As described above, it is preferable that the second signal is obtained by inverting the first signal.

The sub CPU 4 receives the first 8-bit signal (step 322), stores it and waits for a predetermined time (step 323) to receive the second 8-bit signal (step 324). Then, the first and second signals are compared (step 325), and processing is performed according to information based on the signals. Then, an 8-bit signal is transferred to the main CPU 2 (step 326), and if a predetermined time has elapsed (step 327), a second signal is output (step 3).
28). Then, after performing the process according to the information transferred from the main CPU 2 (step 329), the process ends (step 330).

After the second transfer of the 8-bit signal is completed (step 306), the main CPU 2 waits for a lapse of a predetermined time (step 307) and receives the signal transferred from the sub CPU 4 twice for a predetermined time. Yes (Steps 308-31
0). Then, a process according to the information transferred from the sub CPU 4 is performed (step 311), and after a predetermined time has passed, the process is normally terminated (step 312) (step 313).

In the main CPU 2, if the DTR does not become 1 after a predetermined time has elapsed in step 303, it is determined that the processing being performed in the sub CPU 4 has not been completed, and an error flag is set (step 314), the process ends with an error (step 317). If there is an abnormality in signal transmission / reception, the error counter is incremented (step 315), and the value of the counter is determined (step 31).
6). If the value of the counter is equal to or smaller than the predetermined value n, the process returns to step 303 and the data is transferred again. If the error counter becomes equal to or larger than the predetermined value n, the process ends with an error (step 317). If an error signal is output from the sub CPU 4 or if the information output from the sub CPU 4 is inappropriate, it is determined in step 311 that a retransmission request or checksum error has occurred, and the error counter is incremented in step 315. Increment.

On the other hand, in the sub CPU 4, when there is an abnormality in the transmission and reception of the signal in the processing of the steps 322, 324, 326, and 328, the interruption ends respectively (step 330).

When information is provided by SIo3, the sub CP
That is determined in step 325 of U4.
Receives information transferred from the main CPU 2 according to the header.

〔The invention's effect〕

As described above, according to the camera having the information signal confirming means according to the present invention, the first signal is compared with the second signal obtained by inverting the first signal, so that the first signal is compared with the second signal. Is mixed, and if there is a difference in the inversion state between the first signal and the second signal, it can be easily determined that an abnormality has occurred. That is, each digit of the first signal and each digit of the second signal are added, and when each digit of the result is “1”, it is determined that there is no abnormality in the output information, and any of the addition results is determined. If the digit is not "1", it is determined that there is an abnormality in the information. Therefore, it is possible to easily confirm the information to be transferred.

Further, since the second signal is inverted with respect to the first signal, the first and second signals are, for example, “0000”.
If they become equal to “0000” or “11111111”, it is possible to detect that there is a hardware failure such as disconnection or short circuit of the signal line, and it is possible to smoothly control the operation of the camera and the like.

[Brief description of the drawings]

The drawings show a preferred embodiment of the present invention, and FIG. 1 is a schematic block diagram showing a control mechanism of a camera having the checking means. FIG. 2 is a table showing an example of an information signal transmission mode.
FIG. 3 is a flowchart for explaining an operation procedure regarding transmission and reception of information between two CPUs of the camera.
FIG. 4 is a flowchart for explaining an operation procedure when one signal is transmitted and received. 2 Main CPU 4 Sub CPU 6 Operation switch 22 Mode set switch 24 LCD

Claims (1)

(57) [Claims] 1. A camera comprising: a main CPU for controlling operation of a camera; and a sub CPU for performing a date function, wherein information between the main CPU and the sub CPU is exchanged by serial transfer. When information is provided from one of the CPUs to the other CPU, two signals are transmitted for one piece of information, and a second signal of the two signals is used as a first signal. Wherein the other CPU compares the two signals to determine whether or not the transmitted information is correct.