JPH02189416A - Displacement measuring apparatus - Google Patents

Abstract

PURPOSE:To measure phase difference by multiplying a reference signal or a measured signal in a PLL circuit, and sampling the contents of a frequency division counter when another signal rises up or falls down. CONSTITUTION:A phase comparator 1, an LPF 2, a voltage controlled oscillator 3 and a frequency division counter 4 constitute a PLL circuit. A reference logic signal REF is inputted. A clock signal CLK whose frequency is obtained by multiplying the signal of the signal RFF is obtained. A latch pulse generator 5 receives a measured logic signal and generates a latch pulse Pl which is synchronized with the signal CLK when said signal falls down. The pulse Pl is inputted into a latch circuit 8 as a latch pulse Pl1 through a delay circuit 6. The upper 2 bits of the output data of the circuit 8 are latched with a latch circuit 9. In an up/down (U/D) pulse generator 10, the sampling data at the previous time and this time are compared. The output of an U/D counter 11 is latched with a latch circuit 12 based on a signal Pl2 through a delay circuit 7. In an operating circuit 14, the quantity of displacement is obtained based on the initial phase data.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for determining the phase angle θ of a detection signal of sin θ and cos θ.
The present invention relates to a displacement measuring device that measures the amount of displacement based on changes in .

[Conventional technology]

Detectors such as linear encoders and rotary encoders are used to accurately measure length, angle, or other physical displacement amounts.

These detectors have a detection signal obtained by converting the amount of displacement of a scale or the like into an angle θ of sin θ and cos θ having a phase difference of 90 degrees.

If this detection signal is used, it is possible to measure the direction of displacement and the displacement m, but as it is, only a resolution of 2π/4 can be obtained.

An example of a method for increasing resolution will be explained with reference to FIG.

In FIG. 3, the detector 15 outputs two-phase detection signals sin θ and cos θ whose phase angle θ changes depending on the displacement. When the amount of change in the phase angle θ by 2π is defined as the detection pitch d, the amount of displacement Δl is expressed by the following equation.

Δ、! -Mountain”・d・・・・・・・・・(+
)2π However, θ. : initial phase angle θl : phase angle after displacement reference signal generator 19 generates two-phase signal sin of angular frequency ω
art, outputs CO8ωt.

The multipliers 16 and 17 multiply the detection signal and the reference signal, and the subtracter 18 subtracts the output of the multipliers 16 and 17, thereby obtaining the measurement signal M shown in the following equation. .

M = (COSθ−cos ωt) −(sinθ0
sin ωt) = cos(ωt 10) l
−・・・・・・・・・(2) Therefore, the reference signal COS
Since the phase difference between ωt and the measurement signal M becomes the detected phase angle θ, by measuring this and calculating the equation (1), it is possible to measure the displacement Δl.

MMfi signal cosωt and measurement signal M are comparator 2
0゜2I causes logic signals REF and MEAS, respectively.
The period T1 of the reference logic signal REF is measured by the period counting circuit 24 using the clock signal sent from the clock generator 26 and sent to the phase calculator 27.

Reference logic signal REF, measurement logic signal ME
AS is sent to the rising pulse generators 22 and 23, respectively, and the rising pulse signals of both signals are sent to the time difference counting circuit 25, which calculates the time T2 between the rising pulse signals.
is measured using a clock signal and sent to the phase calculator 27.

The phase calculator 27 calculates the phase difference θ from the period data T1 and the time difference data T using the following equation.

θ=-1-×2π ・・・・・・・・・・・・
(3) T+ Here, T≧T2, and as it is, it is impossible to measure a change of 2I or more, so when the phase difference θ changes from 0 to 2π, 2π is subtracted, and the change from 2π to 0. If so, add 2π. Furthermore, the initial phase difference is θ. The amount of change Δβ is measured using the following formula.

△i-00-“d 2yr ・・・・・・・・・・(4)
[Problems to be Solved by the Invention] The above-mentioned method of measuring time requires measuring the period and time difference of the signal and performing arithmetic processing, which results in a complicated circuit configuration and a time-consuming process. Therefore, the data sampling time becomes longer. For this reason, if the displacement speed is high and the phase change is severe, the direction of the phase change cannot be determined, making measurement impossible.

An object of the present invention is to provide a displacement measuring device that can perform high-speed real-time measurement by phase measurement that does not require complicated circuits or arithmetic processing.

[Means to solve the problem]

To achieve this objective, the present invention provides a detection signal sin θ
In a displacement measuring device that measures the amount of displacement from a change in the phase angle θ of θ and cos θ, the amount of relative displacement with respect to the measurement object is expressed as
A detector that outputs a phase detection signal, a circuit that generates reference signals sin ωt and cosmt of angular frequency ω, and a circuit that generates the detection signals sin θ and cos θ and the reference signal sin ωt.
and cosωt, a circuit that generates a measurement signal having a phase angle θ different from the reference signal, a PLL circuit that multiplies either the reference signal or the measurement signal, and a PLL circuit that is synchronized with the other of the reference signal or the measurement signal. a first sampling circuit that holds the contents of a frequency division counter of the PLL circuit;
A second sampling circuit that holds the previous sampling data of the first sampling circuit, and a change that exceeds the multiplication number of the PLL circuit and a change direction are determined from the data of the first and second sampling circuits. , an up/down counter that performs addition/subtraction according to the direction of change;
[Function] In the present invention, the content of the frequency division counter of the PLL circuit is determined by the phase of the signal. The content of the frequency dividing counter is sampled in synchronization with the rising edge of the other of the reference signal or the measurement signal, and up/down counting and addition/subtraction are performed from the previous sampling data and the current sampling data. Thereby, a phase difference of 2π or more can be easily determined, and the direction of phase change can be determined without requiring complicated circuits or calculations.

〔Example] Hereinafter, the present invention will be specifically explained based on Examples.

FIG. 1 is a block diagram showing an embodiment of the displacement measuring device of the present invention, and FIG. 2 is a timing chart of signals of each part thereof.

Note that from the detector 15 to the comparator 20 in FIG.
．． The process of detecting the reference logic signal REF and the measurement logic signal MEAS by the means up to 21 is the same as that of the conventional example shown in FIG. 3, and therefore the description thereof will be omitted.

In FIG. 1, a phase comparator l, a low pass filter 2.
v? The L pressure control oscillator 3 and the frequency division counter 4 (frequency division ratio N=2') constitute a PLL circuit, and the reference logic signal R
EF (frequency ro) is input, and the reference logic signal RE
Frequency f of F. A clock signal CLK having a frequency fe is obtained by multiplying the frequency by 24. Top output fc of branch counter 4
/2' is synchronized with the reference logic signal REF, so the output of the frequency division counter 4 is nothing but the phase of the reference logic signal REF divided by 24.

The latch pulse generator 5 receives the measurement logic signal MEAS and generates a latch pulse P synchronized with the clock signal CLK at the falling edge of the signal. latch pulse P,
passes through a delay circuit 6 having an appropriate delay time and is input to a latch circuit 8 as a latch pulse PL'l. The latch circuit 8 converts the contents of the frequency division counter 4 into a latch pulse Pt.
Retained by 'l. The data held in the latch circuit 8 is the reference logic signal REF and the measurement logic signal MEAS.
This is the phase difference information between them measured with a resolution of 2π/24. The upper two bits of the output data of the latch circuit 8 are input to the latch circuit 9. Therefore, the latch circuit 9 holds the previous sampling data.

The up/down pulse generator 10 compares the previous sampling data D, -1 and the current sampling data D, and determines that I) t-+ is 00. Down pulse when DL is 11, D, + is 11. When D is 00, an up pulse is output. In the timing chart in Figure 2,
Time t1. t2. t1. t4. The latch pulse P is output from the latch pulse generator 5 at time tS, but at time t3
When latch pulse P/ is output, Dt-1 becomes 00
．． Since Dt becomes 11, a down pulse is output.

The up/down counter 11 counts up/down pulses. That is, the data of the latch circuit 8 is 0.
With data of ~2π, any further change will be determined by the up/down pulse generator lO and counted by the up/down counter 11. The output of the up/down counter 11 has a slight time delay compared to the output of the latch circuit 8, so the latch pulse P is passed through the delay circuit 7 with an appropriate delay time and the signal Pi'2 is sent to the latch circuit. Retained by 12.

The output data θ of the latch circuit 12 obtained in this way
. ATA corresponds to a phase change of 2π or more with a resolution of 2π/24 phase difference between the reference logic signal REF and the measurement logic signal MEAS, and is measured. The arithmetic circuit 14 receives initial phase data θ. flA? The amount of change from □ is determined, and the amount of displacement Δp is determined using the following equation.

Δf=(θDATA−〇.oAtA) X d/2'・
(5) In this example, the measurement data θ
DATA is the phase difference itself, and the displacement position Δl can be found only by calculating the equation (5).

Note that the error detector 13 detects the previous upper two bits d, ,
d, and the upper two bits of the current data D, , D3, and if the relationship between the two data is the following four, an error signal ERROR is output.

Table 1 That is, the phase 2π is divided into four quadrants, and if there is a change in two quadrants between the previous data and the current data, an error is detected.

[Effect of Hathu]

As explained above, the present invention multiplies the reference clock signal or measurement logic signal by the PLI circuit, and the PLL circuit multiplies the reference clock signal or the measurement logic signal.
Utilizing the fact that the contents of the circuit's frequency division counter represent the phase information of the signal, the phase can be detected using conventional time measurement by sampling the contents of the frequency division counter when the other signal rises or falls. This method makes it possible to measure phase differences in real time without the need for complex circuitry or processing that involves measuring periods and time differences and performing calculations. In addition, in the conventional method, the resolution changes depending on the clock frequency relative to the signal frequency, but in the present invention, the PLL follows the signal frequency fluctuation, so
This has the advantage that there is no change in resolution due to fluctuations in signal frequency, and it is determined by the frequency division ratio and can be kept constant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of signals of each part thereof, and FIG. 3 is a block diagram of a conventional example. ■Two-phase comparator 2: Low-pass filter 3: Voltage controlled oscillator 4, frequency division counter 5: Latch pulse generator 6.7: Delay circuit 8.9, 12: Latch times V each 10 near-bu/down pulse generator 11 Near sub/down counter 13; Error detector 14: Arithmetic circuit

Claims (1)

[Claims] 1. In a displacement measuring device that measures the amount of displacement from a change in the phase angle θ of the detection signals sin θ and cos θ, the amount of relative displacement with respect to the object to be measured is output as two-phase detection signals of sin θ and cos θ. a circuit that generates reference signals sin ωt and cos ωt with an angular frequency ω, and a circuit that generates the detection signals sin θ and cos θ and the reference signal sin ω
From t and cosωt, the phase angle is θ with respect to the reference signal.
a circuit that generates different measurement signals; a PLL circuit that multiplies either the reference signal or the measurement signal; and a PLL circuit that holds the contents of a frequency division counter of the PLL circuit in synchronization with the other of the reference signal or the measurement signal. a first sampling circuit; a second sampling circuit that retains the previous sampling data of the first sampling circuit; and a second sampling circuit that retains the previous sampling data of the first sampling circuit; Displacement measurement comprising: an up/down counter that discriminates change and change direction and performs addition/subtraction according to the change direction; and a displacement calculation circuit that calculates the amount of displacement from the data of the first sampling circuit and the data of the up/down counter. Device.