JPS62211512A - Rotational position detector - Google Patents

Abstract

PURPOSE:To detect the rotational position with simple constitution without the influence of a detection delay even at the time of rotating at high speed by providing a voltage impression circuit to supply the offset voltage in proportion to the speed to a PI adjuster of a phase-locked loop circuit. CONSTITUTION:A latch circuit 7 is provided and a coefficient multiplier 6 to output the offset voltage in proportion to the rotating speed and an adder 56 to add the offset voltage and the output of a phase comparison circuit 51 are provided. In this way, a signal thetao=0 can be detected from an overflow of a N digit counter 2, etc., and the output of a N digit counter 55 can be sampled for every signal thetao=0 using this signal. On the other hand, the circuit 51 outputs a phase difference between the signals theta and thetao+thetaM and the adjuster 52 adjusts the input voltage of a VCO 53 so that the phase difference is made zero. A prescribed detecting error epsilon of a positional signal by dead time is inputted to the input of the adjuster 52 as the offset voltage via the adder 56 and when the signal theta is sampled in the signal thetao=0 by a prescribed formula, an output signal is made thetaM-epsilon and the detecting error epsilon is added to this and the detecting error can be compensated regardless of the speed.

Description

[Detailed description of the invention] [Industrial application field].

The present invention relates to a position detecting device for a rotating body that includes a resolver and a phase-locked loop (PLL) circuit that demodulates its output signal, and particularly to improvements thereof.

[Conventional technology]

As one type of detection device for detecting the position of a rotating body, one using a synchro electric machine such as a resolver and a so-called PLL circuit is known.

FIG. 2 is a block diagram showing a conventional example of a position detecting device. In the figure, 1 is a reference signal oscillator, 2 is a counter (frequency divider), 6 is an excitation circuit consisting of a read-only memory (ROM), a digital/analog (D/A) converter, an amplifier, etc., and 4 is not shown. Resolver 5 is mechanically coupled to a rotating body, and reference numeral 5 denotes a phase comparator circuit 51. A regulator 52, such as a proportional-integral (PI) regulator. A PLL circuit includes a voltage controlled oscillator (VCO) 53.2, a lease signal generation circuit 54, and a counter (frequency divider) 55, 8 is a digital subtraction circuit, and 9 is a sine wave table.

The reference pulse train output from the reference signal oscillator 1 is converted into a phase signal by the N-ary counter 2, and converted into a two-phase sine wave signal by the excitation circuit 3, which excites the resolver 4. Now, if these two symbols are expressed as , then the output signal of the resolver 4 will be (however, θM is the angle formed between the stator and rotor of the resolver), and this can be expressed using the well-known PLL circuit 5. demodulate using That is, the output signal of the counter 55 in the PLL circuit 5 has the phase of the signal output from the two-bit sign generation circuit 54, and if this is θ, then the steady state where the resolver 4 is rotating at a constant speed is assumed. So,
θ−θO+θM ・・・・・・(3
). Therefore, by subtracting the signal of the counter 55 in the PLL circuit 5 and the signal of the excitation counter 2 by the digital subtraction circuit 8, the rotational position of the resolver 4 can be detected.

The characteristics of this method are that the position signal can be detected digitally and that the resolution can be arbitrarily changed depending on the number of counts of the counter. However, when the resolution is increased, the second
The digital subtraction circuit 8 shown in the figure becomes complicated, and if the position signal is to be detected using sine wave data such as 5i119M, CQSθM, a sine inverse table 9 is provided at the output of the digital subtraction circuit 8. It has the disadvantage that the capacity becomes large.

As a method to improve these drawbacks, there is a method (sampling method) of detecting θ(1=G and outputting a position signal only at this time).In other words, when outputting θlζ as it is, While latching the output of 55 using the θ0-00 signal as a clock, 5iIlθM,
When outputting the sine wave data of CO3θM, it is sufficient to latch the output of the 1LIk + ” table of the 2-bit sign generation circuit 54 (in this case, the ROM table 9 is not required, so this is particularly advantageous). can be greatly simplified.

[Problem that the invention seeks to solve]

However, the position signal obtained by this method is
Since the sample value is output as θM at the time of θ0-0, a detection delay occurs due to dead time.

FIG. 3 is for explaining this, and is an explanatory diagram showing the relationship between time and position. That is, if the object to be detected is rotating at a constant speed, its position will be a straight line as shown by ■ in the figure. On the other hand, the detected value outputs the actual position only at the sample time (see the mark above the straight line), and during the period τ0 it continues to output the detected value at the previous sample time, so the detected value is It becomes step-like as shown in ■.

When the average value of this staircase waveform is calculated, it becomes a straight line parallel to the actual position ■ as shown in the figure, and the distance between the two straight lines in the vertical axis direction of ■ is the average detection error C due to dead time. Become. As is clear from the figure, as the rotation speed increases, the amount of movement within one sample period increases, so there is a proportional relationship between rotation speed and detection error, and the method shown in Figure 2 It can be seen that when the position is detected using sample values at 00-0, the detection error increases as the rotational speed increases with respect to the excitation frequency of the resolver.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a rotational position detection device which has a simple circuit configuration and is free from the effects of detection delay (detection dead time) even during high-speed rotation.

[Means for solving problems]

A voltage application circuit is provided to apply an offset voltage proportional to the speed to the PI regulator of the PLL circuit.

[Effect]

By inputting an offset voltage proportional to the speed to the PI adjuster of the PLL circuit, the effect of dead time due to sampling is compensated for.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

As is clear from the figure, this is achieved by replacing the digital subtraction circuit 8 in Figure 2 with the latch circuit 7, and also adding a coefficient unit 6 that outputs an offset voltage proportional to the rotational speed.
The feature is that an adder 56 for adding the offset pressure and the output of the phase comparator circuit 51 is newly provided.

Incidentally, in such a device, it is common to detect the rotational position and rotational speed at the same time, so if such a configuration is adopted, there is no need to provide a special speed detector. Furthermore, the rotational speed signal used here has a polarity, but this is because the detection error due to dead time is spatially different between normal rotation and reverse rotation. Note that θo-0 can be easily detected from the overflow of the N-ary counter 2, and using this, the output of the N-ary counter 55 is
It becomes possible to sample every o==Q.

In other words, the method of outputting the position signal only when θO=O, as shown in FIG. 2, is a type of sampling method.
The sample time corresponds to one period of the excitation signal, which is called τ. Then, the dead time detection error C is τO g−P−N・−・2π (4) where N is the rotation speed and P is the number of resolver pole pairs.
It is expressed as

On the other hand, the phase comparator circuit 51 in the PLL circuit 5 has θ and θΩ+
The PI regulator 52 outputs a phase difference of θM and adjusts the input voltage of the VCO 53 so that it becomes zero. When an offset voltage called Sense is inputted to the input of the PI controller 52 via the adder 56 (in a steady state where N is constant), θ-(θθ+θM)+ε-〇,°, θ■00+θM"...・
In (5), when θ is sampled when θ0=0, the output signal becomes θM-ε, and by adding the detection error ε due to dead time to this, the detection error can be compensated regardless of the speed. In the above, it is assumed that the phase difference signal is directly output from the output of the phase comparator circuit 51, but a generally known phase comparator circuit uses a vector rotator, and in this case, the output is sinΔθ( However, Δθ−θ
-(θ.+6M)), and in this case, the coefficient multiplier cannot completely compensate, but in the case of Saku-, it becomes sinε-C,
Since the relationship in equation (5) above holds true, there is practically no problem with a coefficient unit. Further, since other points are the same as those in FIG. 2, explanations will be omitted.

〔Effect of the invention〕

According to this invention, the conventional one has an offset proportional to the rotation speed)! By simply adding a simple circuit such as applying pressure, it is possible to compensate for the detection delay of the position signal outputted as a sample, and this brings about the advantage that an inexpensive and accurate position detection device can be obtained.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional example of a rotational position detection device, and Fig. 3 is a block diagram showing a detection error due to sampling. It is an explanatory diagram. Code explanation 1...Reference signal oscillator, 2,55...
N-ary counter, 3... Excitation circuit, 4...
・Resolver, 5... Phase-locked loop (
PLL) circuit, 51... phase comparison circuit, 52.
...PI controller, 56...Voltage controlled oscillator (VCO), 54...2 Lease code generation circuit, 5
6... Adder, 6... Coefficient unit, 7...
... Latch circuit, 8 ... Digital subtraction circuit, 9 ... Sine wave table.

Claims (1)

[Claims] an excitation system that excites the resolver, which includes a resolver attached to a rotating body, a reference signal oscillator that generates a reference signal of a predetermined frequency, a frequency divider that divides the frequency of the reference signal and outputs a reference phase signal, and an excitation circuit; , a regulator that outputs a voltage signal according to an input signal, a voltage controlled oscillator that outputs a frequency signal according to the voltage signal, a frequency divider that divides the frequency signal at a predetermined frequency division ratio, and the frequency divider. A resolver comprising a two-phase signal generator that generates a two-phase signal according to an output frequency, and a phase comparator that detects a phase difference between the two-phase signal and the output of the resolver and supplies the phase difference signal as an input to the regulator. a phase-locked loop (PLL) circuit that demodulates the output; a latch circuit that latches the output of the frequency divider in the PLL circuit every time the phase angle of the reference phase signal reaches zero; and a latch circuit that latches the output of the frequency divider in the PLL circuit; A rotational position detection device comprising: a voltage application circuit that applies an offset voltage proportional to speed.